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| 5685x digitial signal controller freescale.com dsp5 685xum rev. 4 07 /2005 5685x user manual 18 17 16 15 14 13 12 5685x user manual
this manual is one of a set of three documents. for complete product inform ation, it is necessary to have all three documents. they are: dsp56800e reference manual, dsp5685x user manual, and technical data sheet. home page: http://www.freescale.com order this document as dsp56f85xum - rev 4.0 june, 2005 summary of changes and updates: clarified hi8 chapter table 16-1 converted to freescale format table of contents table of contents, rev. 4 i freescale semiconductor chapter 1 5685x overview 1.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 5685x family description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.1 5685x key family features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 5685x family architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4 56800e core description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.4.1 key features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.4.2 56800e core enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.4.3 system architecture and peripheral interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.4.4 56800e core block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.4.5 address buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.4.6 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 7 1.4.7 data arithmetic logic unit (data alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.4.8 address generation unit (agu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.4.9 program controller and hardware looping unit . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.4.10 bit manipulation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.4.11 enhanced on-chip emulation (eonce) module . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4.12 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.4.13 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.4.14 ipbus bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2 1.5 system bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.5.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 23 1.5.2 ipbus bridge (ipbb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.6 5685x memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 5 1.6.1 program sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.6.2 data sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.6.3 boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.7 56853 peripheral blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.8 56854 peripheral blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.9 56855 peripheral blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.10 56857 peripheral blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.11 56858 peripheral blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1.12 peripheral descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1.12.1 external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1.12.2 general purpose input/output port (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 1.12.3 serial communications interface (sci). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 5685x digital signal controller user manual, rev. 4 freescale semiconductor ii 1.12.4 enhanced synchronous serial interface (essi) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.12.5 quad timer (tmr) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.12.6 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 1.12.7 host interface 8 (hi8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.12.8 cop/watchdog timer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.12.9 time of day. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 32 1.12.10 system integration module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 1.12.11 jtag/enhanced once port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 1.12.12 six-channel dma controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.12.13 peripheral interrupts/interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 1.13 56800e programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 chapter 2 pin descriptions 2.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 signal and package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3 power, ground and peripheral signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 chapter 3 memory (mem) 3.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 program boot rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.1 boot mode 0: bootstrap from byte-wide external memory . . . . . . . . . . . . . . . . . . 3-4 3.2.2 boot mode 1: bootstrap from spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.3 boot mode 2: normal expanded mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.4 boot mode 3: development expanded mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.5 boot mode 4: bootstrap from host port?single strobe clocking . . . . . . . . . . . . . 3-5 3.2.6 boot mode 5: bootstrap from host port?dual strobe clocking . . . . . . . . . . . . . . . 3-5 3.2.7 boot mode 6: bootstrap from sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.8 boot mode 7: reserved for future use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -6 3.3.1 memory register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.2 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 chapter 4 system integration module (sim) 4.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table of contents, rev. 4 iii freescale semiconductor 4.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -6 4.4.1 sim interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.6 register descriptions (sys_base = $1fff08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.6.1 sim control register (scr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.6.2 sim software control data 1 (scd1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.6.3 sim software control data 2 (scd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.7 clock generation concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.8 generated clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.9 power mode controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.10 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 chapter 5 external memory interface (emi) 5.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3.1 core interface detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.6 register descriptions (emi_base = $1ffe40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.6.1 chip select base address registers 0?3 (csbar0 ?csbar3 ). . . . . . . . . . . . . . . 5-7 5.6.2 chip select option registers 0?3 (csor0?csor3). . . . . . . . . . . . . . . . . . . . . . . 5-8 5.6.3 chip select timing control registers 0?3 (cstc0?cstc3) . . . . . . . . . . . . . . . . 5-10 5.6.4 bus control register (bcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.7 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.7.1 read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.7.2 write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 7 5.1 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.1 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 chapter 6 on-chip clock synthesis (occs) 6.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.1 occs features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2 osc (oscillator) circuit detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.1 using an external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.2 using an external active clock source below 4 mhz . . . . . . . . . . . . . . . . . . . . . . 6-6 5685x digital signal controller user manual, rev. 4 freescale semiconductor iv 6.2.3 using an external active clock source above 4 mhz . . . . . . . . . . . . . . . . . . . . . . 6-7 6.2.4 stop mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.3 pll (phase locked loop) circuit detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.3.1 phase frequency detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.3.2 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.3.3 loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.3.4 voltage controlled oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.3.5 down counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.3.6 pll lock time user notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.4 cgm functional detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.4.1 pll frequency lock detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.5 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.6 register descriptions (cgm_base = $1fff10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.6.1 clock generation module (cgm) control register . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.6.2 clock generation module (cgm) divide-by register . . . . . . . . . . . . . . . . . . . . . 6-15 6.6.3 clock generation module (cgm) time-of-day register. . . . . . . . . . . . . . . . . . . . 6-16 6.7 occs resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6 6.8 occs interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 7 chapter 7 power-on reset (por) and computer operating properly (cop) 7.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4 method of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.5 computer operating properly (cop) module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.5.1 cop functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.5.2 time-out specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.5.3 cop after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.4 wait mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.5 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.6 debug mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.6 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 6 7.7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.8 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 table of contents, rev. 4 v freescale semiconductor 7.9 register descriptions (cop_base = $1fffd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.9.1 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.9.2 cop time-out register (copto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.9.3 cop counter register (copctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.10 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.11 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.12 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 chapter 8 interrupt controller (itcn) 8.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.7 register descriptions (itcn_base = $1fff20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.7.1 interrupt priority register 0 (ipr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.7.2 interrupt priority register 1 (ipr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.7.3 interrupt priority register 2 (ipr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.7.4 interrupt priority register 3 (ipr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.7.5 interrupt priority register 4 (ipr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.7.6 interrupt priority register 5 (ipr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.7.7 interrupt priority register 6 (ipr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 8.7.8 interrupt priority register 7 (ipr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.7.9 interrupt priority register 8 (ipr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 8.7.10 vector base address register (vba) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25 8.7.11 fast interrupt match registers (fim0 and fim1) . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 8.7.12 fast interrupt vector address registers (fival0, fivah0, fival1, fivah1) . . 8-27 8.7.13 fast interrupt 1 vector address low register (fival1). . . . . . . . . . . . . . . . . . . . 8-28 8.7.14 fast interrupt 1 vector address high register (fivah1) . . . . . . . . . . . . . . . . . . . 8-28 8.7.15 irq pending registers (irqp0, irqp1, irqp 2, irqp3, irqp4) . . . . . . . . . . . . 8-29 8.7.16 interrupt control register (ictl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 8.7.17 interrupt vector map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.8 wait and stop mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35 8.9 host control interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35 8.10 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8.10.1 reset handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8.10.2 itcn after reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 5685x digital signal controller user manual, rev. 4 freescale semiconductor vi 8.11.1 interrupt handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8.11.2 interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 7 chapter 9 direct memory access (dma) 9.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.4 module memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5 dma controller block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.6 register descriptions (dma_ bases = $1ffec0, $1ffec8, $1ffed0, $1ffed8, $1ffee0, $1ffee8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.6.1 dma transfer control (dmatc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.6.2 dma circular queue size (dmacqs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.6.3 dma transfer count (dmacnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.6.4 dma destination address low (dmadal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.6.5 dma destination side address high (dmadah) . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.6.6 dma source address low (dmasal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.6.7 dma source address high (dmasah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.7 programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.1 peripheral-to-memory dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.2 memory-to-memory dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.7.3 peripheral-to-memory circular queue dma operation . . . . . . . . . . . . . . . . . . . . 9-15 chapter 10 serial communications interface (sci) 10.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0-4 10.4 external pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4.1 transmit data (txd) pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.4.2 receiver data (rxd) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.5 module memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.6.1 data frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.6.2 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.6.3 sci transmitter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.6.4 sci receiver block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.6.5 single wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.6.6 loop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 table of contents, rev. 4 vii freescale semiconductor 10.7 dma operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 1 10.7.1 transmit dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.7.2 receive dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.7.3 receiver wake up with dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.8 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.8.1 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 2 10.8.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 2 10.8.3 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 2 10.8.4 wait mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.9 sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) 10-23 10.9.1 sci baud rate (scibr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.9.2 sci control register (scicr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.9.3 sci control register 2 (scicr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.9.4 sci status register (scisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.9.5 sci data register (scidr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.10 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.11 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.12 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.12.1 transmitter empty interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.12.2 transmitter idle interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.12.3 receiver full interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.12.4 receive error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.12.5 receiver idle interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 chapter 11 serial peripheral interface (spi) 11.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3 spi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 -5 11.4.1 master in/slave out (miso) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.2 master out/slave in (mosi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.3 serial clock (sclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.4 slave select (ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.5 external i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 -6 11.6 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11- 7 11.6.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.6.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11- 8 11.6.3 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.6.4 wired or mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 5685x digital signal controller user manual, rev. 4 freescale semiconductor viii 11.7 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.1 data transmission length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.7.2 data shift ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.7.3 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.7.4 transmission format when cpha = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.7.5 transmission format when cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.7.6 transmission initiation latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.8 transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.9 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 -17 11.9.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.9.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.10 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.11 spi register descriptions (spi_base = $1fffe8). . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11.11.1 spi status and control register (spscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11.11.2 spi data size and control register (spdscr) . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.11.3 spi data receive register (spdrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.11.4 spi data transmit register (spdtr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.12 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.13 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 chapter 12 enhanced synchronous serial interface (essi) 12.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -4 12.3.1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.2 external signals descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4 essi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12.5.1 normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12.5.2 network mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.5.3 synchronous/asynchronous operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.5.4 network mode with mask registers implemented . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.6 essi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12.7 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 12.8 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00). . . . . 12-26 12.8.1 essi transmit registers (stx0, stx1, stx2) . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 12.8.2 essi transmit fifo registers (txfifo0, txfifo1, txfifo2) . . . . . . . . . . . . 12-27 12.8.3 essi transmit shift registers (txsr0, txsr 1, txsr2) . . . . . . . . . . . . . . . . . 12-28 12.8.4 essi receive register (srx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 table of contents, rev. 4 ix freescale semiconductor 12.8.5 essi receive fifo register (rxfifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 12.8.6 essi receive shift register (rxsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12.8.7 essi status register (ssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 12.8.8 essi control register 2 (scr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 12.8.9 essi control register 3 (scr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 12.8.10 essi control register 4 (scr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47 12.8.11 essi transmit and receive control registers (stxcr, srxcr) . . . . . . . . . . . 12-50 12.8.12 time slot register (stsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12.8.13 essi fifo control/status register (sfcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 12.8.14 transmit slot mask registers (tsma, tsmb) . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57 12.8.15 receive slot mask registers (rsma, rsmb) . . . . . . . . . . . . . . . . . . . . . . . . . . 12-58 12.9 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59 12.10 clock operation description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60 12.10.1 essi clock and frame sync generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60 12.11 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62 12.12 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63 12.13 interrupt operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63 12.13.1 receive data with exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63 12.13.2 receive data (rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64 12.13.3 receive last slot (rls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64 12.13.4 transmit data with exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64 12.13.5 transmit data (tx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64 12.13.6 transmit last slot (tls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65 12.14 user notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65 12.14.1 external frame sync setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65 12.14.2 maximum external clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65 chapter 13 quad timer (tmr) 13.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3 operatng modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13- 4 13.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3-4 13.5 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3-4 13.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.7 counting modes definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.7.1 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 -5 13.7.2 count mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13- 6 13.7.3 edge count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 5685x digital signal controller user manual, rev. 4 freescale semiconductor x 13.7.4 gated count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.7.5 quadrature count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.7.6 signed count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.7.7 triggered count mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.7.8 one-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.7.9 cascade count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.7.10 pulse output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.7.11 fixed frequency pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.7.12 variable frequency pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.7.13 compare registers use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.7.14 capture register use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.8 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.9 register descriptions (tmr_base = $1ffe80) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.9.1 timer control registers (ctl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.9.2 timer channel status and control registers (scr) . . . . . . . . . . . . . . . . . . . . . . 13-14 13.9.3 timer channel compare register 1 (cmp1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.9.4 timer channel compare register 2 (cmp2). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.9.5 timer channel capture register (cap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.9.6 timer channel load register (load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.9.7 timer channel hold register (hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.9.8 timer channel counter register (cntr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.10 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.11.1 timer compare interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.11.2 timer overflow interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.11.3 timer input edge interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 chapter 14 time-of-day (tod) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-3 14.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.3 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4-4 14.4 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5.1 scaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-6 14.5.2 time units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4-6 14.5.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14- 7 14.5.4 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.5.5 alarm interrupt flag and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.5.6 1-second interrupt flag and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 table of contents, rev. 4 xi freescale semiconductor 14.6 register description (tod_base = $1fffc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.6.1 tod register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.6.2 time-of-day control status (todcs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.6.3 time-of-day clock scaler (todcsl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 14.6.4 time-of-day seconds counter (todsec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 14.6.5 time-of-day seconds alarm register (todsal). . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.6.6 time-of-day minutes register (todmin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.6.7 time-of-day minutes alarm register (todmal) . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.6.8 time-of-day hours register (todhr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.6.9 time-of-day hours alarm register (todhal) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.6.10 time-of-day days register (todday) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 14.6.11 time-of-day days alarm register (toddal) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 chapter 15 general purpose input/output (gpio) 15.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3 block diagram 15-3 15.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.5.1 normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.5.2 gpio mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.6 gpio configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.7 module memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.8 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.8.1 port a peripheral enable register (gpioa_per) . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.8.2 port b peripheral enable register (gpiob_per) . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.8.3 port c peripheral enable register (gpioc_per) . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.8.4 port d peripheral enable register (gpiod_per) . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.8.5 port e peripheral enable register (gpioe_per) . . . . . . . . . . . . . . . . . . . . . . . 15-12 15.8.6 port f peripheral enables register (gpiof_per). . . . . . . . . . . . . . . . . . . . . . . 15-12 15.8.7 port g peripheral enables register (gpiog_per) . . . . . . . . . . . . . . . . . . . . . . 15-13 15.8.8 port h peripheral enables register (gpioh_per) . . . . . . . . . . . . . . . . . . . . . . 15-13 15.8.9 port a data direction register (gpioa_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.8.10 port b data direction register (gpiob_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 15.8.11 port c data direction register (gpioc_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.8.12 port d data direction register (gpiod_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.8.13 port e data direction register (gpioe_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.8.14 port f data direction register (gpiof_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 5685x digital signal controller user manual, rev. 4 freescale semiconductor xii 15.8.15 port g data direction register (gpiog_ddr). . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.8.16 port h data direction register (gpioh_ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.8.17 port a data register (gpioa_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.8.18 port b data register (gpiob_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.8.19 port c data register (gpioc_dr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.8.20 port d data register (gpiod_dr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.8.21 port e data register (gpioe_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.8.22 port f data register (gpiof_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.8.23 port g data register (gpiog_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.8.24 port h data register (gpioh_dr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.8.25 port a pull-up enable register (gpioa_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.8.26 port b pull-up enable register (gpiob_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.8.27 port c pull-up enable register (gpioc_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.8.28 port d pull-up enable register (gpiod_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.8.29 port e pull-up enable register (gpioe_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.8.30 port f pull-up enable register (gpiof_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.8.31 port g pull-up enable register (gpiog_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.8.32 port h pull-up enable register (gpioh_puer) . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.9 data register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.10 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 15.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 chapter 16 host interface eight (hi8) 16.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2.1 dgital signal controller (dsc) side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2.2 host side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.3 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 -5 16.4 hi8 host port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.5 hi8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16- 7 16.6 dsc side register descriptions (hi8_base = $1fffd8). . . . . . . . . . . . . . . . . . . . . 16-8 16.7 host side register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16.8 dsc side registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.8.1 hi8 control register (hcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.8.2 hi8 status register (hsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.8.3 hi8 transmit data register (htx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.8.4 hi8 receive data register (hrx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.8.5 dsc side registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.8.6 hi8 dsc core interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 table of contents, rev. 4 xiii freescale semiconductor 16.9 host side registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.9.1 interface control register (icr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 16.9.2 command vector register (cvr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 16.10 servicing the host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 16.10.1 interface status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 16.10.2 interrupt vector register (ivr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26 16.10.3 receive byte registers (rxh, rxl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27 16.10.4 transmit byte registers (txh, txl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.10.5 host side registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29 16.10.6 hi8 host processor data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.10.7 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.10.8 servicing interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31 16.10.9 host side dma mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 16.10.10 host port use considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35 chapter 17 jtag port 17.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3 master test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.1 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.4 tap block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.5 jtag port architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.5.1 jtag instruction register (jtagir) and decoder . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.5.2 sample and preload instructions (sample/preload) . . . . . . . . . . . . . . . . . . . 17-8 17.5.3 jtag chip identification (cid ) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.6 bypass register (bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.7 jtag boundary scan register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.8 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -19 17.8.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17- 21 17.9 5685x restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 4 5685x digital signal controller user manual, rev. 4 freescale semiconductor xiv appendix a glossary a.1 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 appendix b programmer?s sheets b.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 programmers? sheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 list of figures list of figures, rev. 4 freescale semiconductor xv 1-1 56853 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1-2 56854 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1-3 56855 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1-4 56857 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1-5 56858 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1-6 56800e chip architecture with external bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1-7 56800e core block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1-8 ipbus bridge interface with other main components system side operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1-9 register programming model for the 5685x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 2-1 56853 signals identified by functional group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-2 56854 signals identified by functional group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-3 56855 signals identified by functional group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-4 56857 signals identified by functional group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2-5 56858 signals identified by functional group2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 3-1 56853 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-2 56854 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-3 56855 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-4 56857 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-5 56858 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 4-1 system integration module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-2 sim register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 5-1 emi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5-2 emi register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5-6 data bus contention timing requiring mdar field assertion . . . . . . . . . . . . . . 5-12 5-8 external read cycle with clock and rws = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5-9 external read cycle with rws = 1, rwsh = 0 and rwss = 0 . . . . . . . . . . . . . 5-15 5-10 external read cycle with rwss = rws = 1, and rwsh = 0 . . . . . . . . . . . . . . . 5-16 5-11 external read cycle rws = rwsh = 1 and rwss = 0 . . . . . . . . . . . . . . . . . . . 5-17 5-12 external write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5-13 external write cycle with wws = 1, wwsh = 0, and wwss = 0 . . . . . . . . . . . . 5-19 5-14 external write cycle with wwss = 1, wws = 0 and wwsh = 0 . . . . . . . . . . . . 5-20 5-15 external write cycle with wws = 0, wwsh = 1, wwss = 0 . . . . . . . . . . . . . . . 5-21 5-16 external write cycle with wwss = wws = 1 and wwsh = 0 . . . . . . . . . . . . . . 5-22 5-17 external write cycle with wws = wwsh = 1 (wwss = 0) . . . . . . . . . . . . . . . . . 5-23 6-1 occs integration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 5685x digital signal controller user manual, rev. 4 freescale semiconductor xvi 6-2 osc supplying clocks to pll/cgm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-3 using an external crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6-4 using an external active low frequency clock, < 4 mhz . . . . . . . . . . . . . . . . . . . 6-6 6-5 using an external active high frequency clock, > 4 mhz . . . . . . . . . . . . . . . . . . . 6-7 6-6 pll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-7 pll output frequency vs. input frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6-8 occs register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 7-1 por module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7-2 cop module block diagram and interface signals . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7-3 cop register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 8-1 itcn register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8-2 interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8-25 reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8-26 interrupt handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 9-2 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9-1 dma register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9-10 memory-to-memory dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9-11 dma circular queue operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 10-1 sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-2 sci register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10-3 sci data frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-4 sci transmitter block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10-5 sci receiver block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10-6 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-7 start bit search example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-8 start bit search example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10-9 start bit search example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-10 start bit search example 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 10-11 start bit search example 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10-12 start bit search example 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10-13 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 7 10-14 fast data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10- 18 10-15 single wire operation (loop = 1, rsrc = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10-16 loop operation (loop = 1, rsrc = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 11-1 spi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11-2 cpha/ ss timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11-3 full-duplex master/slave connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-4 spi dma request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 table of contents, rev. 4 xvii freescale semiconductor 11-5 sharing of a slave by multiple masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11-6 transmission format (cpha = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-7 cpha/ss timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-8 transmission format (cpha = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11-9 transmission start delay (master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11-10 sprf/spte interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11-11 missed read of overflow condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-12 clearing sprf when ovrf interrupt is not enabled . . . . . . . . . . . . . . . . . . . . 11-19 11-13 spi register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11-18 spi interrupt request generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 12-1 essi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12-2 normal mode transmit timing (wl=8 bit words, dc = 1) . . . . . . . . . . . . . . . . . 12-11 12-3 normal mode receive timing (wl=8 bit words, dc=1) . . . . . . . . . . . . . . . . . . . 12-13 12-4 network mode transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12-5 network mode receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12-6 synchronous mode interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12-7 network mode transmit timing with mask register. . . . . . . . . . . . . . . . . . . . . . 12-20 12-8 network mode receive timing with mask register . . . . . . . . . . . . . . . . . . . . . . 12-22 12-9 asynchronous (syn=0) essi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12-10 synchronous essi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 12-11 essi register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 12-15 transmit data path (tshfd = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12-16 transmit data path (tshfd = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 12-18 receive data path (rshfd = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12-19 receive data path (rshfd = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12-21 frame sync timing options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 12-33 essi clocking (8-bit words, 3 time slots / frame) . . . . . . . . . . . . . . . . . . . . . . 12-59 12-34 essi clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60 12-35 essi transmit clock generator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 12-61 12-36 essi transmit frame sync generator block diagram . . . . . . . . . . . . . . . . . . . . 12-61 13-1 tmr module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13-2 quadrature incremental position encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13-3 tmr register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 14-1 time-of-day counter operation block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14-2 tod register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 15-1 bit-slice view of gpio logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15-2 gpio a register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15-3 gpio b register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 5685x digital signal controller user manual, rev. 4 freescale semiconductor xviii 15-4 gpio c register map summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15-5 gpio d register map summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15-6 gpio e register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15-7 gpio f register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15-8 gpio g register map summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15-9 gpio h register map summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 16-1 hi8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16-2 dsc host side register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16-3 dsc host side register map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16-5 single and dual data strobe bus modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16-9 hsr?hcr operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16-18 hi8 host request structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-31 17-1 test access port (tap) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17-2 jtagir register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17-3 bypass register diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17-4 jtag chip identification (cid) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17-5 jtag bypass register (jtagbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17-6 boundary scan register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17-7 tap controller state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 list of tables list of tables, rev. 4 xix freescale semiconductor 0-1 pin conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxix 1-1 feature matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 2-1 functional group pin allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-2 power inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2-3 grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-4 external bus control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-5 external chip select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-6 host interface eight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-7 quad timer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2-8 interrupt and program control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2-9 serial communication interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2-10 serial communication interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2-11 enhanced synchronous serial interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2-12 enhanced synchronous serial interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2-13 serial peripheral interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2-14 clock and phase lock loop signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2-15 jtag/eonce signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 3-1 eonce memory map (eonce_base = $ffff00) . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3-2 system integration module register address map (sys_base = $1fff08) see chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-3 external memory interface registers address map (emi_base = $1ffe40) see chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-4 clock generation module registers address map (cgm_base = $1fff10) see chapter 6 . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-5 computer operating properly module registers address map (cop_base = $1fffd0) see chapter 7. . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-6 interrupt control registers address map (itcn_base = $1fff20) see chapter 8. . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-7 direct memory access 0 register address map (dma0_base = $1ffec0) see chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-8 direct memory access 1 register address map (dma1_base = $1ffec8) see chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-9 direct memory access 2 register address map (dma2_base = $1ffed0) see chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-10 direct memory access 3 register address map (dma3_base = $1ffed8) see chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-11 direct memory access 4 register address map (dma4_base = $1ffee0) see chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-13 5685x digital signal controller user manual, rev. 4 freescale semiconductor xx 3-12 direct memory access 5 register address map (dma5_base = $1ffee8) see chapter 9 . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3-13 serial communication interface 0 registers address map (sci0_base = $1fffe0) see chapter 10. . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-14 serial communication interface 1 registers address map (sci1_base = $1ffdf8) see chapter 10 . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-15 serial peripheral interface registers address map (spi_base =$1fffe8) see chapter 11 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-16 enhanced synchronous serial interface 0 registers address map (essi0_base = $1ffe20) see chapter 12. . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-17 enhanced synchronous serial interface 1 registers address map (essi1_base =$1ffe00) see chapter 12 . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-18 quad timer registers address map (tmr_base = $1ffe80) see chapter 13 . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3-19 time-of-day registers address map (tod_base = $1fffc0) see chapter 14. . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3-20 general purpose input/output a register map (gpioa_base = $1ffe60) see chapter 15 . . . . . . . . . . . . . . . . . . . . . . . 3-16 3-21 general purpose input/output b register map (gpiob_base = $1ffe64) see chapter 15 . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-22 general purpose input/output c register map (gpioc_base = $1ffe68) see chapter 15 . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-23 general purpose input/output d register map (gpiod_base = $1ffe6c) see chapter 15. . . . . . . . . . . . . . . . . . . . . . . 3-17 3-24 general purpose input/output e register map (gpioe_base = $1ffe70) see chapter 15 . . . . . . . . . . . . . . . . . . . . . . 3-17 3-25 general purpose input/output f register map (gpiof_base = $1ffe74) see chapter 15. . . . . . . . . . . . . . . . . . . . . . . 3-18 3-26 general purpose input/output g register map (gpiog_base = $1ffe78) see chapter 15 . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-27 general purpose input/output h register map (gpioh_base = $1ffe7c) see chapter 15 . . . . . . . . . . . . . . . . . . . . . . 3-18 3-28 host interface 8 registers (hi8_base =$1fffd8) see chapter 16 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 4-1 ipbus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-2 clock generator inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-3 reset generator inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-4 register inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-5 power mode control inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-6 derived clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-7 system integration module memory map (sim_base = $1fff08) . . . . . . . . . . . . 4-8 list of tables, rev. 4 xxi freescale semiconductor 4-8 sim clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 5-1 emi module memory map (emi_base = $1ffe40). . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-2 csbar encoding of the blksz field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5-3 csor encoding byte_en values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-4 csor encoding of read/write values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-5 csor encoding of ps/ds values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5-6 operation with drv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 6-1 cgm memory map $1fff10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 7-1 cop time-out ranges as a function of oscill ator frequency . . . . . . . . . . . . . . . . 7-5 7-2 cop module memory map (cop_base = $1fffd0) . . . . . . . . . . . . . . . . . . . . . . 7-7 8-1 interrupt priority level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8-2 itcn module memory map (itcn_base = $1fff20) . . . . . . . . . . . . . . . . . . . . . . 8-5 8-3 interrupt vector table contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8-4 interrupt mask bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 8-5 interrupt priority encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38 9-1 dma common signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9-2 dma ipbus signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9-3 dma x1 bus signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9-4 dma 0 register address map (dma0_base = $1ffec0) . . . . . . . . . . . . . . . . . . 9-5 9-5 dma 1 register address map (dma1_base = $1ffec8) . . . . . . . . . . . . . . . . . . 9-5 9-6 dma 2 register address map (dma2_base = $1ffed0) . . . . . . . . . . . . . . . . . . 9-5 9-7 dma 3 register address map (dma3_base = $1ffed8) . . . . . . . . . . . . . . . . . . 9-6 9-8 dma 4 register address map (dma4_base = $1ffee0) . . . . . . . . . . . . . . . . . . 9-6 9-9 dma 5 register address map (dma5_base = $1ffee8) . . . . . . . . . . . . . . . . . . 9-6 9-10 dma_req connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 10-1 external i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-2 sci0 module memory map (sci0_base = $1fffe0) . . . . . . . . . . . . . . . . . . . . . 10-5 10-3 sci1 module memory map (sci1_base = $1ffdf8) . . . . . . . . . . . . . . . . . . . . . 10-5 10-4 example 8-bit data frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10-5 example 9-bit data frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10-6 example baud rates (module clock = 60mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10-7 start bit verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 10-8 data bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-9 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10-10 receiver wake up with dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10-11 loop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10-12 sci interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 11-1 spi i/o configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 5685x digital signal controller user manual, rev. 4 freescale semiconductor xxii 11-2 external i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11-3 spi module memory map (spi_base = $1fffe8) . . . . . . . . . . . . . . . . . . . . . . 11-21 11-4 spi master baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11-5 transmission data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11-6 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 12-1 signal properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12-2 mode and signal definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12-3 essi clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-4 essi frame sync sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-5 essi operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 12-6 normal mode transmit operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12-7 normal mode receive operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12-8 notes for transmit timing in figure 12-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12-9 notes for receive timing in figure 12-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12-10 notes for transmit timing with mask register in figure 12-8 . . . . . . . . . . . . . . 12-21 12-11 notes for receive timing with mask register in figure 12-33 . . . . . . . . . . . . . . 12-22 12-12 essi module memory map (essi0_base = $1ffe20, essi1_base = $1ffe00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 12-13 essi receive data interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38 12-14 essi transmit data interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12-15 control modes where scd1 is used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49 12-16 control modes where scd0 is used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49 12-17 wl encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12-18 chip clock rates as a function of essi bit clock frequency and prescale modulus. . . . . . . . . . . . . . . . . . . . . . . 12-53 12-19 rfcnt encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 12-20 tfcnt encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55 12-21 rfwm encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55 12-22 status of receive fifo full flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56 12-23 tfwm encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56 12-24 status of transmit fifo empty flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57 12-25 clock summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60 12-26 essi control bits requiring reset before change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62 12-27 interrupt summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63 13-1 tmr module memory map (tmr_base = $1ffe80) . . . . . . . . . . . . . . . . . . . . 13-10 14-1 tod module memory map (tod_base = $1fffc0) . . . . . . . . . . . . . . . . . . . . . 14-5 14-2 tod register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 list of tables, rev. 4 xxiii freescale semiconductor 15-1 gpio registers functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15-2 gpio a memory map (gpioa_base = $1ffe60) . . . . . . . . . . . . . . . . . . . . . . . 15-5 15-3 gpio b memory map (gpiob_base = $1ffe64) . . . . . . . . . . . . . . . . . . . . . . . 15-6 15-4 gpio c memory map (gpioc_base = $1ffe68) . . . . . . . . . . . . . . . . . . . . . . . 15-6 15-5 gpio d memory map (gpiod_base = $1ffe6c) . . . . . . . . . . . . . . . . . . . . . . . 15-7 15-6 gpio e memory map (gpioe_base = $1ffe70) . . . . . . . . . . . . . . . . . . . . . . . 15-7 15-7 gpio f memory map (gpiof_base = $1ffe74). . . . . . . . . . . . . . . . . . . . . . . . 15-8 15-8 gpio g memory map (gpiog_base = $1ffe78) . . . . . . . . . . . . . . . . . . . . . . . 15-8 15-9 gpio h memory map (gpioh_base = $1ffe7c) . . . . . . . . . . . . . . . . . . . . . . . 15-9 15-10 data register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 16-1 host interface 8 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16-2 dsc side host registers (hi_base =$1fffd8). . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16-3 hi8 host side register map (hi8 host side_base = $1fffd8) . . . . . . . . . . . 16-9 16-4 hrms configuration of hreq and hack pins. . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16-5 hi8 interrupt request order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16-6 dsc side registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 16-7 init execution definition?interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 16-8 init execution definition?hdma mode (hm1 = 1). . . . . . . . . . . . . . . . . . . . . . . 16-19 16-9 mode (hm1, hm0) bit definition (hrms = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 16-10 hreq pin definition?interrupt mode (hrms = 0, hm1 = hm0 = 0). . . . . . . . . . 16-22 16-11 hreq pin definition?host mode (hrms = 0, hm1, hm0 set for dma) . . . . . . 16-23 16-12 htrq and hrrq interrupt mode (hrms = 1). . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 16-13 host side registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29 17-1 jtag pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17-2 master tap instructions opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17-3 tlm register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17-4 device id register bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17-5 bsr contents for 5685x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 5685x digital signal controller user manual, rev. 4 freescale semiconductor xxiv preface, rev. 4 freescale semiconductor xxv preface about this manual features of the 5685x 16-bit digital signal controllers (dscs) are described in this manual. details of memory, operating modes, and peripheral modules are documented here. this manual is intended to be used with the 56800e reference manual (dsp56800erm), describing the central processing unit (cpu), programming models, and instruction set details. the dsp56853/+ technical data sheet provides electrical specifications as well as timing, pinout, and packaging descriptions. audience information in this manual is intended to assist design and software engineers to integrate a 5685x device into a design and/or while developing application software. manual organization this manual is arranged in sections described below: ? chapter 1, 5685x overview ?provides a brief overview, describing the structure of this document, including lists of other documentation necessary to use these chips. ? chapter 2, pin descriptions ?describes package pins for each device and how the pins are grouped into the various interfaces. ? chapter 3, memory (mem) ?depicts the on-chip memory, structures, registers, and interfaces. ? chapter 4, system integration module (sim) ?documents the system control functions module. ? chapter 5, external memory interface (emi) ?defines specifications for the ipbus based external memory interface (emi). the emi module is used for each of the 56800e family chips contained in this manual. ? chapter 6, on-chip clock synthesis (occs) ?elaborates on the internal oscillator, phase lock loop (pll), and timer distribution chain for the 5685x. 5685x digital signal controller user manual, rev. 4 xxvi freescale semiconductor ? chapter 7, power-on reset (por) and computer operating properly (cop) ?function monitors the core power supply and analog power supply. ? chapter 8, interrupt controller (itcn) ?describes how the ipbus interrupt controller accepts interrupt requests from ipbus-based peripherals and presents them to the 56800e core. ? chapter 9, direct memory access (dma) ?transfers data between points in the memory map without intervention by the cpu. the dma controller allows movements of data to and from internal data memory, or internal peripherals to occur in the background of cpu operation. ? chapter 10, serial communications interface (sci) ?presents the serial communications interface, communicating with devices such as codecs, other dscs, microprocessors, and peripherals to provide the primary data input path. ? chapter 11, serial peripheral interface (spi) ?describes the serial peripheral interface, which communicates with external devices, such as liquid crystal displays (lcds) and microcontroller units (mcus). ? chapter 12, enhanced synchronous serial interface (essi) ?details the enhanced synchronous serial interface. it communicates with devices such as industry-standard codecs, other dscs, microprocessors, and peripherals to implementing the serial peripheral interface (spi). ? chapter 13, quad timer (tmr) ?outlines the internal quad timer devices available, including features and registers. ? chapter 14, time-of-day (tod) ?discusses instruction of the sequence of counters to track elapsed time and its ability to track time up to 179.5 years, or 65,535 days. ? chapter 15, general purpose input/output (gpio) ?describes how peripheral pins are multiplexed with gpio functions. ? chapter 16, host interface eight (hi8) ?provides host processors with dsc design accesses. ? chapter 17, jtag port ?explains the joint test action group (jtag) testing methodology and its capabilities with test access port (tap) and enhanced once (fully explained in the reference manual). ? appendix a, glossary ?provides definitions of terms, peripherals, acronyms and register names used in this manual. ? appendix b, programmer?s sheets ?provides concise, one location of registers and their reference tables intended to simplify programming of the 5685x. preface, rev. 4 freescale semiconductor xxvii suggested reading a list of related books is provided here as an aid those who may be new to digital signal controllers: advanced topics in signal processing, jae s. lim and alan v. oppenheim (prentice-hall: 1988). applications of digital signal processing, a. v. oppenheim (prentice-hall: 1978). digital processing of signals: theory and practice, maurice bellanger (john wiley and sons: 1984). digital signal processing, alan v. oppenheim and ronald w. schafer (prentice-hall: 1975). digital signal processing: a system design approach, david j. defatta, joseph g. lucas, and william s. hodgkiss (john wiley and sons: 1988). discrete-time signal processing, a. v. oppenheim and r.w. schafer (prentice-hall: 1989). foundations of digital signal processing and data analysis, j. a. cadzow (macmillan: 1987). handbook of digital signal processing , d. f. elliott (academic press: 1987). introduction to digital signal processing , john g. proakis and dimitris g. manolakis (macmillan: 1988). ip bus specifications , semiconductor reuse standard, srsipb1, v 2.0, draft 1.6. multirate digital signal processing , r. e. crochiere and l. r. rabiner (prentice-hall: 1983). signal processing algorithms , s. stearns and r. davis (prentice-hall: 1988). signal processing handbook , c. h. chen (marcel dekker: 1988). signal processing: the modern approach , james v. candy (mcgraw-hill: 1988). theory and application of digital signal processing , lawrence r. rabiner and bernard gold (prentice-hall: 1975). 5685x digital signal controller user manual, rev. 4 xxviii freescale semiconductor manual conventions conventions used in this manual: ? bits within registers are always listed from most significant bit (msb) to least significant bit (lsb). ? bits within a register are formatted aa[n:0] when more than one bit is involved in a description. for purposes of description, the bits are presented as if they are contiguous within a register. however, this is not always the case. refer to the programming model diagrams or to the programmer?s sheets to see the exact location of bits within a register. ? when a bit is described as set , its value is set to one . when a bit is described as cleared , its value is set to zero . ? pins or signals asserted low, made active when pulled to ground, have an over-bar above their name. for example, the ss0 pin is asserted low. ? hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $fffb is the x memory address for the interrupt priority register (ipr). ? code examples follow in a single spaced font. ? pins or signals listed in code examples asserted as low have a tilde in front of their names. in the previous example, line three refers to the ss0 pin, shown as ~ss0. ? the word reset is used in three different contexts in this manual. the word pin is a generic term for any pin on the chip. they are described as: ? a reset pin is always written as reset , in uppercase, using the over bar ? the processor state occurs when the reset pin is asserted. it is always written as reset, with a capitalized first letter ? the word reset refers to the reset function. it is written in lowercase, without italics, used here only for differentiation. the word may require a capital letter as style dictates, such as in headings and captions ? the word assert means a high true (active high) signal is pulled high to v dd , or a low true (active low) signal is pulled low to ground. the word deassert means a high true signal is pulled low to ground, or a low true signal is pulled high to v dd . bfset #$0007,x:pcc ; configure: line 1 ; miso0, mosi0, sck0 for spi master line 2 ; ~ss0 as pc3 for gpio line 3 preface, rev. 4 freescale semiconductor xxix ? for clarity, all signals are referenced with capital letters throughout this document ? descriptive functionality of signals is taken into account when choosing signal names. this may imply names for system bus interface signals that are different than those defined in the 56800e specification documents. ? all efforts are made to maintain compliance with semiconductor reuse standards guidelines ? the prefix ipbb_ is used for all signals initiated from the ip bus bridge ? a prefix symbolizing a specific block?s name is used to distinguish input signals (point to point signals) ? all signals initiated from a particular bus will contain a prefix signifying that bus throughout the manual, registers displaying a grayed area designate reserved bits. table 0-1. pin conventions signal/symbol logic state signal state voltage 1 1.values for vil, vol, vih, and voh are defined by individual product specifications. the following standards are recognized in choosing block i/o signal names for the bridge: pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol = reserved or not implemented bit, written as zero for future compatibility 5685x digital signal controller user manual, rev. 4 xxx freescale semiconductor 5685x overview, rev. 4 freescale semiconductor 1-1 chapter 1 5685x overview 5685x digital signal controller user manual, rev. 4 1-2 freescale semiconductor 5685x family description 5685x overview, rev. 4 freescale semiconductor 1-3 1.1 introduction differing in size of memories and choice of peripherals, these multi-functional chips offer features dsp programmers demand for executing true signal processing algorithms, flexible user-defined, multi-level interrupt priority support, supports traditional dsp mathematical functions for executing complicated computations, giving programmers more control in an interrupt-driven application . the 56853, 56854, 56855, 56857, and 56858 are members of the 56800e core-based family of digital signal controllers (dscs). combined on a single chip are the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals. the chip design creates an extremely cost-effective and compact solution for a number of uses. the 56800e family includes many peripherals especially well-suited for low-end internet appliance applications and low-end client applications, such as: ? telephony ? voice recognition ? voice-processing for multi-processor systems ? portable devices ? advanced industrial control ? internet audio ? point-of-sale systems ? noise suppression ? id tag readers ? sonic/subsonic detectors ? security access devices ? remote metering ? sonic alarms 1.2 5685x family description the 5685x device family is based on the 56800e core and combines, on a single chip, the processing power of a digital signal controller and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, each of the five devices are well-suited for many applications. with the exception of the 56852 chip (not included in this manual), the 5685x family includes from 12k to 40k words of program sram, 4k to 24k words of data ram and 1k of boot rom. 5685x family description 5685x digital signal controller user manual, rev. 4 1-4 freescale semiconductor with the exception of the 56857, the balance of the 5685x family of devices supports program execution from either internal or external memories. two data operands can be accessed from the on-chip data ram per instruction cycle. the 5685x family also provides two external dedicated interrupt lines, and up to 47-general purpose input/output (gpio) lines, depending on peripheral configuration. all devices, except the 857, support program execution from external memory. the 56800e core can access two data operands from the on-chip data ram per instruction cycle. these controllers also provides a full set of standard programmable peripherals that include an 8-bit host interface (hi8), up to two enhanced synchronous serial interfaces (essi), one serial peripheral interface (spi), two serial communications interfaces (sci), and one quad timer (tmr). when primary functions of each of the peripheries (hi8, tmr, essi, spi, sci i/o and four chip selects) are not required, they can be used as general purpose input/outputs (gpios). please see section 1.3 for details on each of the 5685x family of devices. 1.2.1 5685x key family features 1.2.1.1 the 56853 ? supports program execution from either internal or external memories ? provides two external dedicated interrupt lines ? provides up to 41-general purpose input/output (gpio) lines, depending on peripheral configuration ? includes 12k words of program ram ? includes 4k words of data ram ? includes 1k words of boot rom ? provides a full set of standard programmable peripherals including: ? eight-bit host interface (hi8) ? one enhanced synchronous serial interface (essi) ? one serial peripheral interface (spi) ? two serial communications interfaces (scis) ? one quad timer (tmr) ? one, 6-channel direct memory access (dma) the hi8, essi, spi, sci, four chip selects and tmr can be used as general purpose input/outputs (gpios) if its primary function is not required. 5685x family description 5685x overview, rev. 4 freescale semiconductor 1-5 1.2.1.2 the 56854 ? supports program execution from either internal or external memories ? provides two external dedicated interrupt lines ? provides up to 41-general purpose input/output (gpio) lines, depending on peripheral configuration ? includes 16k words of program ram ? includes 16k words of data ram ? includes 1k words of boot rom ? provides a full set of standard programmable peripherals including: ? eight-bit host interface (hi8) ? one enhanced synchronous serial interface (essi) ? one serial peripheral interface (spi) ? two serial communications interfaces (scis) ? one quad timer (tmr) ? one, 6-channel direct memory access (dma) the hi8, essi, spi, sci, four chip selects and tmr can be used as general purpose input/outputs (gpios) if its primary function is not required. 1.2.1.3 the 56855 ? supports program execution from either internal or external memories ? provides two external dedicated interrupt lines ? provides up to 18-general purpose input/output (gpio) lines, depending on peripheral configuration ? includes 24k words of program ram ? includes 24k words of data ram ? includes 1k of boot rom ? provides a full set of standard programmable peripherals including: ? one enhanced synchronous serial interface (essi) ? two serial communications interfaces (sci) ? one quad timer (tmr) ? one, 6-channel direct memory access (dma) the essi, sci i/o, four chip selects and quad timer can be used as general purpose input/outputs when its primary function is not required. 5685x family description 5685x digital signal controller user manual, rev. 4 1-6 freescale semiconductor 1.2.1.4 the 56857 ? provides two external dedicated interrupt lines ? provides up to 47-general purpose input/output (gpio) lines, depending on peripheral configuration. ? includes 40k words of program ram ? includes 24k words of data ram ? includes 1k of boot rom ? provides a full set of standard programmable peripherals including: ? eight-bit host interface (hi8) ? two enhanced synchronous serial interface (essi) ? one serial peripheral interface (spi) ? two serial communications interfaces (sci) ? one quad timer (tmr) ? one, 6-channel direct memory access (dma) the hi8, essis, spi, scis i/o and tmr can be used as general purpose input/outputs when its primary function is not required. 1.2.1.5 the 56858 ? supports program execution from either internal or external memories ? provides two external dedicated interrupt lines ? provides up to 47-general purpose input/output (gpio) lines, depending on peripheral configuration ? includes 40k words of program ram ? includes 24k words of data ram ? includes 1k of boot rom ? provides a full set of standard programmable peripherals that include: ? eight-bit host interface (hi8) ? two enhanced synchronous serial interfaces (essi) ? one serial peripheral interface (spi) ? two serial communications interfaces (sci) ? one quad timer (tmr) ? one, 6-channel direct memory access (dma) the hi8, tmr, essis, spi, sci?s i/o and four chip selects can be used as general purpose input/outputs when its primary function is not required. 5685x family architectural overview 5685x overview, rev. 4 freescale semiconductor 1-7 1.3 5685x family architectural overview the 5685x family of devices consists of the 56800e core, program and data memory, including peripherals useful for embedded control applications. block diagrams for each chip describing the differences in available peripheral sets and memory shown in the following figures: figure 1-1 , figure 1-2 , figure 1-3 , figure 1-4 , and figure 1-5 . figure 1-1. 56853 functional block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core xtal extal interrupt controller quad timer or gpiog 4 clko external address bus switch external bus interface unit 4 reset irqa irqb v dd v ssio v dda v ssa external data bus switch bus control wr enable rd enable cs0-cs3[3:0] or a0-20 [20:0] modea-c or d0-d15 [15:0] 6 program memory 12,288 x 16 sram boot rom 1024 x 16 rom data memory 4,096 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr spi or gpiof 2 sci or gpioe ipbus bridge (ipbb) 3 (gpioh0-h2) 6 10 v ddio 11 decoding peripherals 4 system bus control memory pab pab cdbw cdbr cdbw v ss 6 gpioa0-a3[3:0] 6 essi0 or gpioc host interface or gpiob 16 rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll ipbus clk cop/tod clk core clk ipab ipwdb iprdb dma requests 5685x family architectural overview 5685x digital signal controller user manual, rev. 4 1-8 freescale semiconductor figure 1-2. 56854 functional block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core xtal extal interrupt controller quad timer or gpiog 4 clko external address bus switch external bus interface unit 4 reset irqa irqb v dd v ssio v dda v ssa external data bus switch bus control wr enable rd enable cs0-cs3[3:0] or a0-20 [20:0] modea-c or d0-d15 [15:0] 6 program memory 16,384 x 16 sram boot rom 1024 x 16 rom data memory 16,384 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr spi or gpiof 2 sci or gpioe ipbus bridge (ipbb) 3 (gpioh0-h2) 6 10 v ddio 11 decoding peripherals 4 system bus control memory pab pab cdbw cdbr cdbw v ss 6 gpioa0-gpioa3[3:0] 6 essi0 or gpioc host interface or gpiob 16 rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll ipbus clk cop/tod clk core clk ipab ipwdb iprdb dma requests 5685x family architectural overview 5685x overview, rev. 4 freescale semiconductor 1-9 figure 1-3. 56855 functional block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core xtal extal interrupt controller quad timer or gpiog 4 clko external address bus switch external bus interface unit reset irqa irqb v dd v ssio v dda v ssa external data bus switch bus control wr enable rd enable cs0-cs3[3:0] or a0-20 [20:0] modea-c or d0-d15 [15:0] 6 program memory 24,576 x 16 sram boot rom 1024 x 16 rom data memory 24,576 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr 2 sci or gpioe ipbus bridge (ipbb) 3 (gpioh0-h2) 4 10 v ddio 10 decoding peripherals system bus control memory pab pab cdbw cdbr cdbw v ss 4 gpioa0-gpioa3[3:0] 6 essi0 or gpioc rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll ipbus clk cop/tod clk core clk ipab ipwdb iprdb dma requests 5685x family architectural overview 5685x digital signal controller user manual, rev. 4 1-10 freescale semiconductor figure 1-4. 56857 functional block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core xtal extal interrupt controller quad timer or gpiog 4 clko 4 reset irqa irqb v dd v ssio v dda v ssa cs0-cs3[3:0] modea-c or 6 program memory 40,960 x 16 sram boot rom 1024 x 16 rom data memory 24,576 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr spi or gpiof 2 sci or gpioe ipbus bridge (ipbb) 3 (gpioh0-h2) 8 12 v ddio 12 decoding peripherals 4 system bus control memory pab pab cdbw cdbr cdbw v ss 5 6 essi0 or gpioc 6 essi1 or gpiod host interface or gpiob 16 rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll 2 ipbus clk cop/tod clk core clk used as gpioa0-a3 ipab ipwdb iprdb dma requests gpio contol 5685x family architectural overview 5685x overview, rev. 4 freescale semiconductor 1-11 figure 1-5. 56858 functional block diagram jtag/ enhanced once program controller and hardware looping unit data alu 16 x 16 + 36 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core xtal extal interrupt controller quad timer or gpiog 4 clko external address bus switch external bus interface unit 4 reset irqa irqb v dd v ssio v dda v ssa external data bus switch bus control wr enable rd enable cs0-cs3[3:0] or a0-20 [20:0] mode a-c or d0-d15 [15:0] 6 program memory 40,960 x 16 sram boot rom 1024 x 16 rom data memory 24,576 x 16 sram pdb pdb xab1 xab2 xdb2 cdbr spi or gpiof 2 sci or gpioe ipbus bridge (ipbb) 3 gpioh0-h2 8 14 v ddio 12 decoding peripherals ipab ipwdb iprdb 4 system bus control memory pab pab cdbw cdbr cdbw v ss 8 gpioa0-a3 6 essi0 or gpioc 6 essi1 or gpiod host interface or gpiob 16 rsto dma 6 channel por integration module system cop/ watch- dog time of day clock generator osc pll 2 ipbus clk cop/tod clk core clk dma requests 5685x family architectural overview 5685x digital signal controller user manual, rev. 4 1-12 freescale semiconductor table 1-1. feature matrix feature 56853 56854 56855 56857 56858 speed (mips) 120 120 120 120 120 program sram 12k x 16 16k x 16 24k x 16 40k x 16 40k x 16 data sram 4k x 16 16k x 16 24k x 16 24k x 16 24k x 16 boot rom 1k x 16 1k x 16 1k x 16 1k x 16 1k x 16 program memory up to 2m words up to 2m words u p to 2m words ? up to 2m words data memory up to 8m words up to 8m words up to 8m words ?- up to 8m words oscillator yes yes yes yes yes pll yes yes yes yes yes sci 2 2 2 2 2 spi 1 1 0 1 1 essi 1 1 1 2 2 hi8 1 1 0 1 1 watchdog 1 1 1 1 1 general purpose timers 44 4 44 dedicated gpio ? ? ? 4? gpio (max) 41 41 18 47 47 jtag/eonce 1 1 1 1 1 interrupt controller yes yes yes yes yes dma (6- channel) yes yes yes yes yes external bus 1 1 1 ? 1 package 128 lqfp 128 lqfp 100 lqfp 100 lqfp 144 lqfp 144mapbga 56800e core description 5685x overview, rev. 4 freescale semiconductor 1-13 1.4 56800e core description this section provides a brief overview of the 56800e core. for a more thorough description, please refer to the 56800e core reference manual (dsp56800erm). 1.4.1 key features the 56800e architecture provides a variety of features to enhance performance, reduce application cost, and ease product development. the architectural features making these benefits possible include: ? efficient 16-bit engine with dual harvard architecture ? 120 million instructions per second (mips) at 120mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four, 36-bit accumulators including extension bits ? 16-bit bidirectional shifter ? parallel instruction set with unique addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both digital signal controller and controller functions ? four hardware interrupt levels ? five software interrupt levels ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/enhanced once debug programming interface 1.4.2 56800e core enhancements the 56800e core architecture extends the 56800 family architecture. it is source-code compatible with 56800 devices and adds the following new features: ? byte and long data types, supplementing the 56800?s word data type ? 24-bit data memory address space ? 21-bit program memory address space ? two additional 24-bit pointer registers ? two additional 36-bit accumulator registers 56800e core description 5685x digital signal controller user manual, rev. 4 1-14 freescale semiconductor ? full-precision integer multiplication ? 32-bit logical and shifting operations ? second read in dual read instruction can access off-chip memory ? loop count (lc) register extended to 16 bits ? support for nested do looping through additional loop address and count registers ? loop address and hardware stack extended to 24 bits ? three additional interrupt levels with a software interrupt for each level ? enhanced on-chip emulation (eonce) with three debugging modes: ? non-intrusive real-time debugging ? minimally intrusive real-time debugging ? break point and step modes (core is halted) 1.4.3 system architecture and peripheral interface the 56800e system architecture encompasses all the on-chip components, including the core, on-chip memory, peripherals, and buses necessary to connect them. figure 1-6 shows the overall system architecture for a device with an external bus. figure 1-6. 56800e chip architecture with external bus external data external address ipbus pdb pab xab1 cdbr cdbw xab2 xdb2 peripheral peripheral peripheral 56800e core ipbus interface external bus interface data memory program memory 56800e core description 5685x overview, rev. 4 freescale semiconductor 1-15 complete architecture includes these components: ? 56800e core ? on-chip program memory ? on-chip data memory ? on-chip peripherals ? ipbus peripheral interface ? external bus interface some 56800e devices might not implement an external bus interface. regardless of the implementation, all peripherals communicate with the 56800e core via the ipbus interface. the ipbus interface standard connects the main data address bus xab1, cdbr, and cdbw unidirectional data buses to the corresponding bus interfaces on the peripheral devices. the program memory buses are not connected to peripherals. 1.4.4 56800e core block diagram the 56800e core is composed of several independent functional units. the program controller, address generation unit (agu), and data arithmetic logic unit (alu) contain their own register sets and control logic, allowing them to operate independently and in parallel, which increases throughput. there is also an independent bit-manipulation unit enabling efficient bit-manipulation operations. each functional unit interfaces with the other units, memory, and the memory-mapped peripherals over the core?s internal address and data buses. a block diagram of the 56800e core architecture is shown in figure 1-7 . 56800e core description 5685x digital signal controller user manual, rev. 4 1-16 freescale semiconductor figure 1-7. 56800e core block diagram instruction execution is pipelined to take advantage of the parallel units, significantly decreasing the execution time for each instruction. for example, all within a single execution cycle, it is possible for the data alu to perform a multiplication operation, for the agu to generate up to two addresses, and for the program controller to prefetch the next instruction. the major components of the 56800e core include the following: ? address buses ? data buses ? data arithmetic logic unit (alu) data 56800e core arithmetic logic unit (alu) xab2 pab pdb cdbw cdbr xdb2 program memory data memory ipbus interface external bus interface bit- manipulation unit n3 m01 address xab1 generation unit (agu) pc la la2 hws0 hws1 fira omr sr fisr lc lc2 instruction decoder interrupt unit looping unit program control unit alu1 alu2 mac and alu a1 a2 a0 b1 b2 b0 c1 c2 c0 d1 d2 d0 y1 y0 x0 eonce? jtag? r2 r3 r4 r5 sp r0 r1 n y 56800e core description 5685x overview, rev. 4 freescale semiconductor 1-17 ? address generation unit (agu) ? program controller and hardware looping unit ? bit-manipulation unit ? enhanced once debugging module ? clock generation ? reset circuitry 1.4.5 address buses the core contains three address buses: 1. program memory address bus (pab) 2. primary data address bus (xab1) 3. secondary data address bus (xab2) the pab is 21 bits wide. it is used to address (16-bit) words in program memory. the two 24-bit data address buses permit two simultaneous accesses to data (x) memory. the xab1 bus can address byte, word, and long data types. the xab2 bus is limited to (16-bit) word accesses. all three buses address on- and off-chip memory on devices containing an external bus interface unit. the 56857 device does not provide external addressing. the xab2 can not go off-chip. 1.4.6 data buses data transfers inside the chip occur over the following buses: ? two unidirectional 32-bit buses: ? core data bus for reads (cdbr) ? core data bus for writes (cdbw) ? two unidirectional 16-bit buses: ? secondary x data bus (xdb2) ? program data bus (pdb) ? ipbus interface data transfers between the data alu and data memory use the cdbr and cdbw when a single memory read or write is performed. when two simultaneous memory reads are performed, the transfers use the cdbr and xdb2 buses. all other data transfers to core blocks occur using the cdbr and cdbw buses. peripheral transfers occur through the ipbus interface. instruction word fetches occur over the pdb. 56800e core description 5685x digital signal controller user manual, rev. 4 1-18 freescale semiconductor this bus structure supports up to three simultaneous 16-bit transfers. any one of the following can occur in a single clock cycle: ? one instruction fetch ? one read from data memory ? one write to data memory ? two reads from data memory ? one instruction fetch and one read from data memory ? one instruction fetch and one write to data memory ? one instruction fetch and two reads from data memory an instruction fetch will take place on every clock cycle, although it is possible for data memory accesses to be performed without an instruction fetch. such accesses typically occur when a hardware loop is executed and the repeated instruction is only fetched on the first loop iteration. 1.4.7 data arithmetic logic unit (data alu) the data arithmetic logic unit (alu) performs all of the arithmetic, logical, and shifting operations on data operands. the data alu contains the following components: ? three, 16-bit data registers (x0, y0, and y1) ? four, 36-bit accumulator registers (a, b, c, and d) ? one multiply-accumulator (mac) unit ? a single-bit accumulator shifter ? one arithmetic and logical multi-bit shifter ? one mac output limiter ? one data limiter all in a single instruction cycle, the data alu can perform multiplication, multiply-accumulation, with positive or negative accumulation, addition, subtraction, shifting, and logical operations. division and normalization operations are provided by iteration instructions. signed and unsigned multi-precision arithmetic is also supported. all operations are performed using two?s-complement fractional or integer arithmetic. data alu source operands can be 8, 16, 32, or 36 bits in size and can be located in memory, in immediate instruction data, or in the data alu registers. arithmetic operations and shifts can have 16-, 32-, or 36-bit results. logical operations are performed on 16- or 32-bit operands and yield results of the same size. the results of data alu operations are stored either in one of the data alu registers or directly in memory. 56800e core description 5685x overview, rev. 4 freescale semiconductor 1-19 1.4.8 address generation unit (agu) the address generation unit (agu) performs all of the calculations of effective addresses for data operands in memory. it contains two address alus, allowing up to two 24-bit addresses to be generated every instruction cycle: 1. one for either the primary data address bus (xab1), or the program address bus (pab) 2. one for the secondary data address bus (xab2) the address alu can perform both linear and modulo address arithmetic. the agu operates independently of the other core units, minimizing address-calculation overhead. the agu can directly address 2 24 (16m) words on the xab1 and xab2 buses. it can access 2 21 (2m) words on the pab. the xab1 bus can address byte, word, and long data operands. the pab and xab2 buses can only address words in memory. the agu consists of the following registers and functional units: ? seven, 24-bit address registers (r0?r5 and n) ? four, 24-bit shadow registers for address registers (for r0, r1, m, and m01 ? a 24-bit dedicated stack pointer (sp) register ? two offset registers (n and n3) ? a 16-bit modifier register (m01) ? a 24-bit adder unit ? a 24-bit modulo arithmetic unit each of the address registers (r0?r5) can contain either data or an address. all of these registers can provide an address for the xab1 and pab address buses; addresses on the xab2 bus are provided by the r3 register. the n offset register can be used either as a general-purpose address register or as an offset or update value for the addressing modes supporting those values. the second 16-bit offset register (n3) is used only for offset or update values. the modifier register (m01) selects between linear and modulo address arithmetic. 1.4.9 program controller and hardware looping unit the program controller is responsible for instruction fetching and decoding, interrupt processing, hardware interlocking, and hardware looping. actual instruction execution takes place in the other core units, such as in the data alu, agu, or bit-manipulation unit. the program controller contains the following: ? an instruction latch and decoder ? the hardware looping control unit 56800e core description 5685x digital signal controller user manual, rev. 4 1-20 freescale semiconductor ? interrupt control logic ? a program counter (pc) ? two special registers for fast interrupts: ? fast interrupt return address register (fira) ? fast interrupt status register (fisr) ? seven user-accessible status and control registers: ? two-level deep hardware stack (hws) ? loop address (la) register ? loop address (la2) register 2 ? loop count (lc) register ? loop count (lc2) register 2 ? status register (sr) ? operating mode register (omr) the operating mode register (omr) is a programmable register to control the operation of the 56800e core, including the memory-map configuration. the initial operating mode is typically latched on reset from an external source; it can subsequently be altered under program control. the loop address (la) and loop count (lc) registers work in conjunction with the hardware stack to support no-overhead hardware looping. the hardware stack is an internal last-in-first-out (lifo) buffer consisting of two, 24-bit words and stores the address of the first instruction of a hardware do loop. when executing the do instruction begins a new hardware loop, the address of the first instruction in the loop is pushed onto the hardware stack. when a loop finishes normally or an enddo instruction is encountered, the value is popped from the hardware stack. this process allows one hardware do loop to be nested inside another. 1.4.10 bit manipulation unit the bit-manipulation unit performs bit field operations on data memory words, peripheral registers, and registers within the 56800e core. it is capable of testing, setting, clearing, or inverting individual or multiple bits within a 16-bit word. the bit-manipulation unit can also test bytes for branch-on-bit field instructions. 56800e core description 5685x overview, rev. 4 freescale semiconductor 1-21 1.4.11 enhanced on-chip emulation (eonce) module the enhanced on-chip emulation (eonce) module allows user interaction in a debug environment with the 56800e core and its peripherals. its capabilities include: ? examining registers ? memory, or on-chip peripherals ? setting breakpoints in memory ? stepping or tracing instructions it provides simple, inexpensive, and speed independent access to the 56800e core for sophisticated debugging and economical system development. the jtag port allows access to the enhanced once module and through the 5685x device to its target system, retaining debug control without sacrificing other user accessible on-chip resources. this technique eliminates the costly cabling and the access to processor pins required by traditional emulator systems. the enhanced once interface is fully described in the dsp56800e reference manual (dsp56800erm). 1.4.12 clocks 1.4.12.1 on-chip clock synthesis block the clock synthesis module generates the clocking for the 5685x family of devices. it generates the master clock used by the system integration module (sim) to derive the system and peripheral clocks. it also generates the time of day clock used by time-based modules like tod and cop. it contains an oscillator module to apply the clock. it also contains a pll with the ability to multiply-up the frequency. the pll can also be bypassed and scaled to lower power consumption on the 5685x device. the cgm module selects which clock is routed to the master clock output. it also selects and configures the time of day clock prescaler and pll. 1.4.12.2 oscillator the 5685x device is clocked either from an external crystal or external clock input: ? crystal oscillator uses a 2 - 4mhz crystal ? ceramic resonator can be used in place of the crystal ? there are separate power and ground for the oscillator and pll ? oscillator input can be directly clocked at up to 240mhz 56800e core description 5685x digital signal controller user manual, rev. 4 1-22 freescale semiconductor 1.4.12.3 pll the pll in the 56800e core provides the following features: ? the pll generates output frequencies up to 240mhz from a 2 - 4mhz input ? the pll can be bypassed to use oscillator or prescalar outputs directly 1.4.12.4 clock generation module this contains registers used to control clock generation and select clock sources: ? there is a choice of time of day clock prescalers ? the pll frequency postscaler and enable control ? selection of master clock source to be pll ,or osc and glitch-free clock switching ? pll postscaler supports pll output division by 1, 2, 4, 8, 16, 64,or 128 1.4.12.5 time of day clock options these options provide: ? a choice of two tod clock prescalers ? low power/128 prescaler in osc module for input clock frequencies to 4mhz ? high frequency two stage/1-4096 and /2 prescaler in cgm module for input clock frequencies to 240mhz osc tod prescaler 1.4.13 resets the 5685x device reset circuitry provides these features: ? integrated por release occurs when v dd exceeds 1.35v and v dda exceeds 2.45v ? reset pin ? software reset ?cop reset 1.4.14 ipbus bridge the ipbus architecture supports a variety of on-chip peripherals, including: ? external memory interface (emi) module ? serial communication interface (sci) module ? 16-bit timer (tmr) module ? computer operating properly (cop) module ? time of day (tod) module system bus controller 5685x overview, rev. 4 freescale semiconductor 1-23 ? enhanced synchronous serial interface (essi) module ? serial peripheral interface (spi) module ? programmable general-purpose i/o (gpio) module ? eight-bit parallel host interface (hi8) 1.5 system bus controller the system bus controller (sbc) controls a number of functions essential to the transfer of data between the core, dma controllers and memory within the 56853/854/855/857/858 systems. 1.5.1 operation the sbc performs a number of central roles in the transfer of data between either the core or dma controller and memory space. in every clock cycle, the sbc determines whether the core or dma is bus master, which memory device in any space is active, and if the core clock is active. through these actions, all data transfers are completed at maximum bus efficiency. the sbc is capable of supporting one core and one dma controller of up to six channels (operating in x1 data space only): ? up to three program memory address spaces ? up to two x1 memory address spaces ? single x2 memory address space either the core or dma controller are capable of initiating memory transfers. bus mastership is arbitrated by the sbc, and the device which is permitted to access the bus on any given cycle is referred to as the active bus master. 1.5.2 ipbus bridge (ipbb) the ipbus bridge (ippb) provides a means for communication between the high speed core and the low-bandwidth devices on the ip peripheral bus. among other functions, the bridge is responsible for maintaining an orderly and synchronized communication between devices on both sides running at two different clock frequencies. figure 1-8 denotes the position and interface of the ipbus bridge with other main blocks within the chip. other connections in the figure not pertaining to the primary function of the bridge are omitted for clarity; nevertheless, they will be discussed as appropriate. a brief description of bridge?s interface with various main components on both sides is also provided. system bus controller 5685x digital signal controller user manual, rev. 4 1-24 freescale semiconductor 1.5.2.1 system side operation on the system side, the ipbus bridge operates at core frequency and fully supports pipelined communication with the core. the bridge acts as a slave device on this bus. the bridge is responsible for initiating ipbus transactions only per requests initiated by the core, or other system bus masters. figure 1-8. ipbus bridge interface with other main components system side operation 1.5.2.2 peripheral side operation on the peripheral side, the ipbus bridge accesses various devices through a standard non-pipelined ipbus interface. separate bus lines are used for read and write transactions. the ipbus bridge also interfaces with an external memory interface (emi) block. the ipbus operates at half of the core frequency. ip ip x1 data 56800e core 416 21 xab1 cdbr cdbw x2 data ram 1-1/2 port xab2 xdb2 program ram pab pdb 16 21 24 32 ipb_rdata ipb_wdata ipb_addr ram ip ipb_r/w ip 16 32 24 emi interface cs ad ipbus bridge rd wr 5685x memory 5685x overview, rev. 4 freescale semiconductor 1-25 1.6 5685x memory these lists provide features of the 56853/854/55/857/858?s memory modules: ? 56853 ? 12k 16-bit program sram ?4k 16-bit data sram ?1k 16-bit boot rom ? 56854 ? 16k 16-bit program sram ? 16k 16-bit data sram ?1k 16-bit boot rom ? 56855 ? 24k 16-bit program sram ? 24k 16-bit words of data sram ?1k 16-bit boot rom ? 56857 ? 40k 16-bit program sram ? 24k 16-bit data sram ?1k 16-bit boot rom ? 56858 ? 40k x 16-bit program sram ? 24k x 16-bit data sram ? 1k x 16-bit boot rom 1.6.1 program sram ? single port ram is compatible with the pipelined program bus structure ? single cycle reads at 120mhz 1.6.2 data sram ? single read, dual read or single write memory compatible with the pipelined data bus structure ? single cycle reads/writes at 120mhz 56853 peripheral blocks 5685x digital signal controller user manual, rev. 4 1-26 freescale semiconductor 1.6.3 boot rom ? single port rom is compatible with the pipelined program bus structure ? single cycle reads at 120mhz 1.7 56853 peripheral blocks the 56853 provides these peripheral blocks: ? two serial communication interfaces (sci0 and sci2), each with two pins, or four additional gpio lines ? enhanced synchronous serial interface (essi0), with six pins or additional gpio lines ? general purpose 16-bit quad timer (tmr), with four pins or additional gpio lines ? one serial peripheral interface (spi), with four pins or additional gpio lines ? eight-bit host interface (hi8) with 16 pins, or 16 additional gpio lines ? interrupt controller ? computer operating properly (cop)/watchdog timer ? time of day (tod) ? clock generator ? system integration module (sim) ? external memory interface (emi) ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging 1.8 56854 peripheral blocks the 56854 provides these peripheral blocks: ? two serial communication interfaces (sci), each with two pins, or four additional gpio lines ? enhanced synchronous serial interface (essi0), with six pins or additional gpio lines ? general purpose 16-bit quad timer (tmr) with four pins or additional gpio lines ? serial port interface (spi) with four pins or additional gpio lines ? eight-bit parallel host interface (hi8) with 16 pins, or 16 additional gpio lines ? interrupt controller ? computer operating properly (cop)/watchdog timer ? time of day (tod) ? clock generator ? system integration module (sim) 56857 peripheral blocks 5685x overview, rev. 4 freescale semiconductor 1-27 ? external memory interface (emi) ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging 1.9 56855 peripheral blocks the 56855 provides these peripheral blocks: ? two serial communication interfaces (sci0 and sci2), each with two pins, or four additional gpio lines ? enhanced synchronous serial interface (essi0), with six pins or additional gpio lines ? general purpose 16-bit quad timer with one pin or additional gpio line ? interrupt controller ? computer operating properly (cop)/watchdog timer ? time of day (tod) ? clock generator ? system integration module (sim) ? external memory interface (emi) ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging 1.10 56857 peripheral blocks the 56857 provides these peripheral blocks: ? two serial communication interfaces (sci), each with two pins, or four additional gpio lines ? two enhanced synchronous serial interfaces (essi0 and essi1), each with six pins, or 12 additional gpio lines ? general purpose 16-bit quad timer (tmr) with four pins or additional gpio lines ? serial port interface (spi) with four pins or additional gpio lines ? eight-bit parallel host interface (hi8) with 16 pins, or 16 additional gpio lines ? interrupt controller ? computer operating properly (cop)/watchdog timer ? time of day (tod) ? clock generator ? system integration module (sim) ? external memory interface (emi) ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging 56858 peripheral blocks 5685x digital signal controller user manual, rev. 4 1-28 freescale semiconductor 1.11 56858 peripheral blocks the 56858 provides these peripheral blocks: ? two serial communication interfaces (sci), each with two pins, or four additional gpio lines ? two enhanced synchronous serial interfaces (essi0 and essi1), each with six pins, or 12 additional gpio lines ? general purpose 16-bit quad timer (tmr) with four pins or additional gpio lines ? serial port interface (spi) with four pins or additional gpio lines ? eight-bit parallel host interface (hi8) with 16 pins, or 16 additional gpio lines ? interrupt controller ? computer operating properly (cop)/watchdog timer ? time of day (tod) ? clock generator ? system integration module (sim) ? external memory interface (emi) ? jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging 1.12 peripheral descriptions the ipbus bridge converts program and data memory accesses to the ipbus-compliant interface for peripherals and external emi. this ipbus bridge allows for communication between the core and peripherals utilizing the cdbr for data and xab for addresses. to access program space through the emi, use pab and pdb buses. peripherals run off the ipbus clock at up to 60mhz. the ipbus clock frequency is half of the system clock frequency. 1.12.1 external memory interface the emi design includes these distinctive features: ? programmable wait states for slower memories (up to 16 ip_clk access time) ? contains four programmable chip selects ? no external glue logic required for typical systems, if the chip selects are used ? chip selects may be independently programmed with various features ? program or data space selection ? programmable byte enables, to support 8-bit wide external memories peripheral descriptions 5685x overview, rev. 4 freescale semiconductor 1-29 1.12.2 general purpose input/output port (gpio) ? 56853 ? 41 shared gpio, multiplexed with other peripherals ? each bit may be individually configured as an input or output ? selectable enable for pull-up resistors ? 56854 ? 41 shared gpio, multiplexed with other peripherals ? each bit may be individually configured as an input or output ? selectable enable for pull-up resistors ? 56855 ? 18 shared gpio, multiplexed with other peripherals ? each bit may be individually configured as an input or output ? selectable enable for pull-up resistors ? 56857 ? 47 gpio, multiplexed with other peripherals (43 multiplexed and 4 dedicated) ? each bit may be individually configured as an input or output ? selectable enable for pull-up resistors ? 56858 ? 47 gpio, multiplexed with other peripherals ? each bit may be individually configured as an input or output ? selectable enable for pull-up resistors 1.12.3 serial communications interface (sci) each of the chips in the 56800e family has two serial communication interfaces (sci0 and sci1). sci features include: ? asynchronous operation ? baud rate generation ? ir interface support peripheral descriptions 5685x digital signal controller user manual, rev. 4 1-30 freescale semiconductor 1.12.4 enhanced synchro nous serial interface (essi) the essi is a full-duplex, serial port designed to allow digital signal controllers (dscs) to communicate with a variety of serial devices, including industry-standard codecs, other dscs, and microprocessors. it is typically used to transfer samples in a periodic manner. the essi consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. essi features include: ? independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs ? normal mode operation using frame sync ? network mode operation allowing multiple devices to share the port with as many as 32-time slots ? network mode enhancements ? time slot mask registers (receive and transmit) ? end of frame interrupt ? programmable internal clock divider ? programmable word length (8, 10, 12, or 16 bits) ? program options for frame sync and clock generation ? essi power-down feature ? audio enhancements ? three transmitters per essi (for six-channel surround sound) 1.12.5 quad timer (tmr) module each chip in the 56800e family contains a general purpose 16-bit tmr module. the quad timer (tmr) module has four external signals capable of being used as either inputs or outputs. they may also be used to interface to the peripheral bus. the 855 has only one external signal. tmr features include: ? four, 16-bit counters/timers ? count up/down ? counters are cascadable ? programmable count modulo ? max count rate equals peripheral clock/2 for external clocks ? max count rate equals peripheral clock for internal clocks ? count once or repeatedly peripheral descriptions 5685x overview, rev. 4 freescale semiconductor 1-31 ? counters are preloadable ? counters can share available input pins ? separate prescaler for each counter ? each counter has capture and compare capability 1.12.6 serial peripheral interface (spi) the serial peripheral interface (spi) is an independent serial communications subsystem allowing full-duplex, synchronous, serial communication between the signal controller and peripheral devices, including other dscs. software can poll spi status flags or spi operation can be interrupt driven. this block contains four, 16-bit memory mapped registers for control parameters, status, and data transfer. spi features include: ? full-duplex operation ? master and slave modes ? double-buffered operation with separate transmit and receive registers ? programmable length transmissions (2 to 16 bits) ? programmable transmit and receive shift order (msb first or last bit transmitted) ? eight master mode frequencies (maximum = bus frequency/2 1 ) ? maximum slave mode frequency = bus frequency ? clock ground for reduced radio frequency (rf) interference ? serial clock with programmable polarity and phase ? two separately enabled interrupts ? sprf (spi receiver full) ? spte (spi transmitter empty) ? mode fault error flag interrupt capability ? direct memory access (dma) capability for both the transmitter and receiver ? wired or mode functionality to enabling connection to multiple spis 1. this frequency may be further limited by the gpio function. peripheral descriptions 5685x digital signal controller user manual, rev. 4 1-32 freescale semiconductor 1.12.7 host interface 8 (hi8) host interface 8 (hi8) is an 8-bit, bidirectional data bus used to transfer data between the host processor and the dsc. to accomplish this, a series of registers are provided to establish the control desired, to monitor the status of the data transfer and to perform the data transfer itself. registers are divided into two groups: 1. host side 2. dsc side both groups allow the host port to operate asynchronously to core clock. generally, the mode of operation is set using the host side control. the dsc side control provides the selectivity for masking or unmasking the various dsc interrupt sources. there are various functional modes possible in the transfer of data: 8-bit vs. 16-bit data transfers, dma vs. single strobe or dual strobe transactions, and interrupt versus polling status interrogation. 1.12.8 cop/watchdog timer module the computer operating properly (cop) module monitors processor activity and provides an automatic reset signal if a failure occurs. please reference chapter 16, reset, low voltage, stop and wait operations . ? 16-bit counter to provide 65536 different time-out periods ? programmable wait and stop mode operation ? programmable time-out period from 32 s to 2.1 sec. with a resolution of 32 s 1.12.9 time of day ? sequence counters to track seconds, minutes, hours, and days ? programmable prescaler to generate 1hz clock ? generates interrupts capable of pulling the part out of wait or stop modes ? capability to track time up to 179.5 years ? configurable alarm and one second interrupts 1.12.10 system integration module the system integration module (sim) is responsible for several system control functions including: ? clock generation ? reset generation ? power mode control peripheral descriptions 5685x overview, rev. 4 freescale semiconductor 1-33 ? boot mode control ? memory map control ? external i/o configuration sim features include: ? four system bus clocks with pipeline hold off support at master clock frequency/2 ? three system clocks for non pipelined interfaces at master clock frequency/2 ? a peripheral bus (ipbus) clock, both on standard and inverted versions at master clock frequency/4 ? an external clock output with disable at master clock frequency/5 ? a core stall control used to stall the 56800e core system clock for dma mastership ? three power modes to control power utilization ? controls to enable/disable the 56800e core wait and stop instructions ? software initiated reset ? controls to redirect internal data and/or program ram accesses to the external memory interface ? software boot mode control register, initialized at any reset except cop reset from external pads via sim inputs modea, b, and c ? a hold off output to coordinate system and peripheral buses ? two 16-bit registers reset only by a power-on reset usable for general purpose software control 1.12.11 jtag/enhanced once port the jtag/enhanced once port allows insertion of the 5685x devices into a target system while retaining debug control. the jtag port provides board-level testing capability for scan-based emulation compatible with the ieee 1149.1a-1993 ieee standard test access port and boundary scan architecture specification defined by the jtag. five dedicated pins interface to a tap containing a 16-state controller. the eonce module allows the user to interact in a debug environment with the 56800e core and its peripherals nonintrusively. its capabilities include: ? examining registers, memory, or on-chip peripherals ? setting breakpoints in memory ? stepping or tracing instructions peripheral descriptions 5685x digital signal controller user manual, rev. 4 1-34 freescale semiconductor it provides simple, inexpensive, and speed-independent access to the 56800e core for sophisticated debugging and economical system development. the jtag/eonce port provides access to the eonce module. the jtag/eonce port retains debug control without sacrificing other accessible on-chip resources through the 5685x devices to its target system. 1.12.12 six-channel dma controller ? the dma operates independently of the cpu. ? the 5685x dma includes six channels. the dma can handle the contexts of six independent block transfers. ? the dma controller has access to 33 percent of the system bus traffic. this one-quarter duty cycle is governed by the 5685x system bus controllers. ? each channel has independently programmable peripheral selection. ? each channel?s source and destination address registers has configurable indices. ? for each memory fetch and put , the address may remain constant, be post incremented, or post decremented. ? each read or write transfer may be initiated by selected events: specified peripheral requests or direct cpu triggering may launch a new dma transaction. ? upon completion of a block transfer, each dma channel may send an interrupt to the cpu. ? the dma includes a circular queue operational mode providing continuous dma operation with no additional processor intervention. 1.12.13 peripheral interrupts/interrupt controller the peripherals on the 5685x use the itcn module to interface to the interrupt signal found on the 56800e core. each peripheral has its own interrupt vector, often more than one interrupt vector for each peripheral, and can selectively be enabled or disabled via the ipr registers. the interrupt controller (itcn) module design includes these distinctive features: ? programmable priority levels for each irq ? two programmable fast interrupts ? notification to sim module to restart clocks out of wait and stop modes 56800e programming model 5685x overview, rev. 4 freescale semiconductor 1-35 1.13 56800e programming model the programming model for the registers in the 56800e core is shown in figure 1-9 . figure 1-9. register programming model for the 5685x 0 15 16 31 32 35 0 23 0 15 0 12 r2 r3 r4 r5 sp r0 r1 n a1 a2 a0 b1 b2 b0 c1 c2 c0 d1 d2 d0 data arithmetic logic unit (alu) data registers address generation unit (agu) pointer registers 0 15 y1 y0 x0 d c b a y program counter 0 20 pc 0 23 la loop address la2 0 23 hws0 hardware stack hws1 0 23 fira fast interrupt return address secondary offset register program control unit n3 0 15 modifier registers m01 0 15 operating mode register omr sr and status register (omr, sr) fast interrupt status register fisr loop counter 0 15 lc lc2 56800e programming model 5685x digital signal controller user manual, rev. 4 1-36 freescale semiconductor overview, rev. 4 freescale semiconductor 2-1 chapter 2 pin descriptions 5685x digital signal controller user manual, rev. 4 2-2 freescale semiconductor introduction overview, rev. 4 freescale semiconductor 2-3 2.1 introduction this chapter details the input and output signals and functions of 568x packaging. depending on the device, their pins allow a variety of functions and capabilities. each is detailed in this chapter. in addition to the available peripherals, up to 47-general purpose pins are also available when not required for other purposes. the remaining signal pins are dedicated to one function. the input and output signals of these packages are organized into functional groups, shown in table 2-1 and illustrated in figure 2-1 through figure 2-5 . each table row describes the package pins and the signal or signals present in table 2-2 through table 2-15 . interface signals have these general characteristics: ? pins listed here are pulled high with an on-chip resistor ? tdi ? tms ? trst ? de ? this pin is pulled low with an on-chip resistor: ?tck ? these pins are pulled high by the device during hardware reset: ? rd ? wr ? these pins have the internal pull-ups permanently disabled: ? moda ? modb ? modc ? general purpose i/o pins have programmable pull-up resistors introduction 5685x digital signal controller user manual, rev. 4 2-4 freescale semiconductor table 2-1. functional group pin allocations functional group number of pins detailed description 853 854 855 857 858 power (v dd , v dda , or v dd core) 1818152121 table 2-2 ground (v ss or v ssa ) 1717151924 table 2-3 external chip select signals* 39 39 39 ? 39 table 2-4 external bus control signals 44444 table 2-5 host interface (hi)* 16 16 ? 16 16 table 2-6 quad timer module (tmr) port* 44144 table 2-7 interrupt and program control 77777 table 2-8 serial communication interface (sci0) ports* 22222 table 2-9 serial communication interface (sci1) ports* 22222 table 2-10 enhanced synchronous serial interface (essi0) port*66666 table 2-11 enhanced synchronous serial interface (essi1) port* ? ? ? 6 6 table 2-12 serial peripheral interface (spi) port* 4 4 ? 4 4 table 2-13 clock and phase lock loop (pll) 33333 table 2-14 jtag/eonce 66666 table 2-15 *alternately, general-purpose i/o pins introduction overview, rev. 4 freescale semiconductor 2-5 figure 2-1. 56853 signals identified by functional group 2 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. 56853 logic power i/o power sci 0 jtag / enhanced once timer module essi 0 spi chip select external bus analog power 1 pll/clock host interface sci 1 interrupt/ program control v dd v ss v ddio v ssio v dda v ssa a0 - a20 rd d0 - d15 wr cs0 - cs3 (gpioa0 - a3) hd0 - hd7 (gpiob0 - b7) ha0 - ha2 (gpiob8 - b10) hrw (hrd ) (gpiob11) hds (hwr ) (gpiob12) hcs (gpiob13) hreq (htrq ) (gpiob14) hack (hrrq) (gpiob15) tio0 - tio3 (gpiog0 - g3) irqa irqb moda, modb, modc (gpioh0 - h2) reset rsto host interface xtal (clkin) rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) miso (gpiof0) mosi (gpiof1) sck (gpiof2) ss (gpiof3) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 4 1 1 1 1 1 3 8 4 1 1 16 21 1 1 10 11 6 6 introduction 5685x digital signal controller user manual, rev. 4 2-6 freescale semiconductor figure 2-2. 56854 signals identified by functional group 2 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. 56854 logic power i/o power sci 0 jtag / enhance d once timer module essi 0 spi chip select external bus analog power 1 pll/cloc k host interface sci 1 interrupt/ program control v dd v ss v ddio v ssio v dda v ssa a0 - a20 rd d0 - d15 wr cs0 - cs3 (gpioa0 - a3) hd0 - hd7 (gpiob0 - b7) ha0 - ha2 (gpiob8 - b10) hrw (hrd ) (gpiob11) hds (hwr ) (gpiob12) hcs (gpiob13) hreq (htrq ) (gpiob14) hack (hrrq) (gpiob15) tio0 - tio3 (gpiog0 - g3) irqa irqb moda, modb, modc (gpioh0 - h2) reset rsto host interface xtal (clkin) rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) miso (gpiof0) mosi (gpiof1) sck (gpiof2) ss (gpiof3) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 4 1 1 1 1 1 3 8 4 1 1 16 21 1 1 10 11 6 6 introduction overview, rev. 4 freescale semiconductor 2-7 figure 2-3. 56855 signals identified by functional group 2 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. 56855 logic power i/o power sci 0 jtag / enhanced once timer module essi 0 chip select external bus analog power 1 pll/clock sci 1 interrupt/ program control v dd v ss v ddio v ssio v dda v ssa a0 - a20 rd d0 - d15 wr cs0 - cs3 (gpioa0 - a3) tio0 (gpiog0) irqa irqb moda, modb, modc (gpioh0 - h2) reset rsto xtal (clkin) rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 4 1 1 16 21 1 1 10 10 4 4 introduction 5685x digital signal controller user manual, rev. 4 2-8 freescale semiconductor figure 2-4. 56857 signals identified by functional group 2 1. specifically for pll, osc, and por. 2. alternative pin functions are shown in parentheses. 56857 logic power i/o power sci 0 jtag / enhanced once timer module essi 0 spi chip select analog power 1 pll/clock host interface sci 1 essi 1 interrupt/ program control v dd v ss v ddio v ssio v dda v ssa cs0 - cs3 (gpioa0 - a3) hd0 - hd7 (gpiob0 - b7) ha0 - ha2 (gpiob8 - b10) hrw (hrd ) (gpiob11) hds (hwr ) (gpiob12) hcs (gpiob13) hreq (htrq ) (gpiob14) hack (hrrq) (gpiob15) tio0 - tio3 (gpiog0 - g3) irqa irqb mode a, mode b, mode c (gpioh0 - h2) reset rsto host interface xtal (clkin) rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) miso (gpiof0) mosi (gpiof1) sck (gpiof2) ss (gpiof3) std1 (gpiod0) srd1 (gpiod1) sck1 (gpiod2) sc10 (gpiod3) sc11 (gpiod4) sc12 (gpiod5) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 4 1 1 1 1 1 3 8 4 2 1 12 12 5 8 introduction overview, rev. 4 freescale semiconductor 2-9 figure 2-5. 56858 signals identified by functional group 2 1. specifically for pll, osc, and por. 2. alternate pin functions are shown in parentheses. 56858 logic power i/o power sci 0 jtag / enhanced once timer module essi 0 spi chip select address bus analog power 1 pll/cloc k host interface sci 1 essi 1 interrupt/ program control v dd v ss v ddio v ssio v dda v ssa a0 - a20 rd d0 - d15 wr cs0 - cs3 (gpioa0 - a3) hd0 - hd7 (gpiob0 - b7) ha0 - ha2 (gpiob8 - b10) hrw (hrd ) (gpiob11) hds (hwr ) (gpiob12) hcs (gpiob13) hreq (htrq ) (gpiob14) hack (hrrq) (gpiob15) tio0 - tio3 (gpiog0 - g3) irqa irqb moda, modb, modc (gpioh0 - h2) reset rsto host interface rxdo (gpioe0) txdo (gpioe1) rxd1 (gpioe2) txd1 (gpioe3) std0 (gpioc0) srd0 (gpioc1) sck0 (gpioc2) sc00 (gpioc3) sc01 (gpioc4) sc02 (gpioc5) miso (gpiof0) mosi (gpiof1) sck (gpiof2) ss (gpiof3) std1 (gpiod0) srd1 (gpiod1) sck1 (gpiod2) sc10 (gpiod3) sc11 (gpiod4) sc12 (gpiod5) extal clko tck tdi tdo tms trst de 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 4 1 1 1 1 1 3 8 4 1 1 16 21 2 1 14 12 8 8 xtal (clkin) signal and package information 5685x digital signal controller user manual, rev. 4 2-10 freescale semiconductor 2.2 signal and package information all digital inputs have a weak internal pull-up circuit associated with them. these pull-up circuits are enabled by default. exceptions: 1. when a pin has gpio functionality, the pull-up may be disabled under software control 2. mode pins d13, d14, and d15 have no pull-up 3. tck has a weak pull-down circuit always active 4. bidirectional i/o pull ups automatically disabled when the output is enabled the following tables are presented consistently with the signals identified by functional group figure. 1. bold entries in the type column represents the state of the pin just out of reset. 2. output(z) means an output is in a high-z condition. 2.3 power, ground and peripheral signals the following tables illustrate power, ground, and bypass capacitor pinout data. table 2-2 through table 2-9 displays the physical layout of various grounds and voltage input signals associated with the input/output ring. signal names in parentheses on the same table row provide the gpio alternative pin function. table 2-2. power inputs signal name signal description 853 pins 854 pins 855 pins 857 pins 858 pins v dd power? these pins provide power to the internal structures of the chip. they all should be attached to v dd . 66488 v ddio power? these pins provide power for all i/o and esd structures of the chip. they all should be attached to v ddio (3.3v). 11 11 10 12 12 v dda analog power ?these pins supply analog power. 11111 power, ground and peripheral signals overview, rev. 4 freescale semiconductor 2-11 table 2-3. grounds signal name signal description 853 pins 854 pins 855 pins 857 pins 858 pins v ss ground? these pins provide grounding for the internal structures of the chip and should all be attached to v ss . 66458 v ssio ground? these pins provide grounding for all i/o and esd structures of the chip. they all should be attached to v ssio . 10 10 10 12 14 v ssa analog power ?these pins supply an analog ground. 11122 table 2-4. external bus control signals signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins a0-a20 output(z) address bus? these signals specify a word address for external program or data memory access. 21 21 21 ? 21 d0-d15 input / output(z) data bus? these pins provide the bidirectional data for external program or data memory accesses. 16 16 16 ? 16 rd output read enable? is asserted during external memory read cycles. this signal is pulled high during reset. 111?1 wr output write enable? is asserted during external memory write cycles. this signal is pulled high during reset. 111?1 table 2-5. external chip select signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins cso - cs3 (gpioa0-a3) output input / output external chip select? these pins are used as chip selects during external memory cycles. port a gpio0-3? these are general purpose i/o pins when not configured for emi use. 44444 power, ground and peripheral signals 5685x digital signal controller user manual, rev. 4 2-12 freescale semiconductor table 2-6. host interface eight signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins hd0-hd7 (gpiob0-b7) input input / output host data? these inputs provide data for the hi registers. these pins are disconnected internally during reset. port b gpio 0-7? these are a general purpose i/o pins when not configured for host port use. 88?88 ha0-ha2 (gpiob8-b10) input input / output host address? these inputs provide address selection for hi registers. these pins are disconnected internally during reset. port b gpio 10? these are general purpose i/o pins when not configured for host port use. 33?33 hrw (hrd ) (gpiob11) input input input / output host read/write? when the hi is programmed to interface to a single-data-strobe host bus and the hi function is selected, this signal is the read/write input. these pins are disconnected internally during reset. host read enable? this signal is the read data input when the hi is programmed to interface to a double-data-strobe host bus and the hi function is selected. port b gpio 11? this is a general purpose i/o pin when not configured for host port use. 11?11 hds (hwr ) (gpiob12) input input input / output host data strobe? when the hi is programmed to interface to a single-data-strobe host bus and the hi function is selected, this input enables a data transfer on the hi when hcs is asserted. host write enable? this signal is the write data input when the hi is programmed to interface to a double-data-strobe host bus and the hi function is selected. port b gpio 12? this is a general purpose i/o pin when not configured for host port use. 11?11 hcs (gpiob13) input input / output host chip select? this input is the chip select input for the host interface.this pin is disconnected internally when reset. port b gpio 13? this is a general purpose i/o pin when not configured for host port use. 11?11 power, ground and peripheral signals overview, rev. 4 freescale semiconductor 2-13 hreq (htrq ) (gpiob14) open drain output open drain output input / output host request? when the hi is programmed for hrms = 0 functionality, typically used on a single-data-strobe bus, this open drain output is used by hi to request service from the host processor. the hreq may be connected to an interrupt request pin of a host processor, a transfer request of a dma controller, or a control input of external circuitry. this pin is disconnected internally when reset. transmit host request? this signal is the output when the hi is programmed for hrms = 1 functionality and is typically used on a double-data-strobe bus. port b gpio 14? this is a general purpose i/o pin when not configured for host port use. 11?11 hack (hrrq) (gpiob15) input open drain output input / output host acknowledge? when the hi is programmed for the hrms = 0 functionality, typically used on a single-data-strobe bus, this input has two functions: (1) provide a host acknowledge signal for dma transfers, or (2) to control handshaking and provide a host interrupt acknowledge compatible with the mc68000 family processors. this pin is disconnected internally when reset. receive host request? this signal is the output when the hi is programmed for hrms = 1 functionality, and it is typically used on a double-data-strobe bus. port b gpio 15? this is a general purpose i/o pin when not configured for host port use. 11?11 table 2-6. host interface eight (continued) signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins power, ground and peripheral signals 5685x digital signal controller user manual, rev. 4 2-14 freescale semiconductor table 2-7. quad timer module signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins tio0 (gpiog0) input / output input / output timer input/output? this pin can be independently configured to be either a timer input source or an output. port g gpio 0? this is a general purpose i/o pin when not configured for timer use. 11111 tio1-tio3 (gpiog0-g3) input / output input / output timer input/output? these pins can be independently configured to be either a timer input source or an output. port g gpio 1-3? these are general purpose i/o pins when not configured for timer use. 33?33 table 2-8. interrupt and program control signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins irqa input external interrupt request a and b? these inputs are asynchronous external interrupt requests, indicating an external device is requesting service. a schmitt trigger input is used for noise immunity. they can be programmed to be level-sensitive or negative-edge-triggered. if level-sensitive triggering is selected, an external pull-up resistor is required or wired-or operation. 11111 irqb input 11111 moda, modb, modc (gpioh0-h2) input input / output mode select? during the bootstrap process, moda, modb, and modc selects one of the eight bootstrap modes. mode select? during the bootstrap process, the mode a, b, and c pins select one of the eight bootstrap modes. these pins are sampled at the end of reset. port h gpio 0-2? these are general purpose i/o pins after the bootstrap process has completed. note: any time por and external resets are active the state of mode a, b and c pins get asynchronous transferred to the sim control register [14:12] ($1fff08) respectively. these bits determine the mode in which the part will boot up. note: software and cop resets do not update the sim control register. 33333 power, ground and peripheral signals overview, rev. 4 freescale semiconductor 2-15 reset input reset? this input is a direct hardware reset on the processor. when reset is asserted low, the device is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the moda, modb, and modc pins. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the jtag/eonce module. in this case, assert reset . do not assert trst . 11111 rsto output reset output? this output is asserted on any reset condition (external reset, low voltage, software, or cop). 11111 table 2-9. serial communication interface 0 signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins rxdo (gpioe0) input input / output serial receive data 0? this input receives byte-oriented serial data and transfers it to the sci0 receive shift receiver. port e gpio 0? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11111 txdo (gpioe1) output(z) input / output serial transmit data 0? this signal transmits data from the sci0 transmit data register. port e gpio 1? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11111 table 2-8. interrupt and program control (continued) signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins power, ground and peripheral signals 5685x digital signal controller user manual, rev. 4 2-16 freescale semiconductor table 2-10. serial communication interface 1 signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins rxd1 (gpioe2) input input / output serial receive data 1? this input receives byte-oriented serial data and transfers it to the sci1 receive shift receiver. port e gpio 2? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11111 txd1 (gpioe3) output(z) input / output serial transmit data 1? this signal transmits data from the sci1 transmit data register. port e gpio 3? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11111 table 2-11. enhanced synchronous serial interface 0 signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins std0 (gpioc0) output(z) input / output essi transmit data 0? this output pin transmits serial data from the essi transmitter shift register. port c gpio 0? this is a general purpose i/o pin when the essi is not in use. 11111 srd0 (gpioc1) input input / output essi receive data 0? this input pin receives serial data and transfers the data to the essi transmitter shift register. port c gpio 1? this is a general purpose i/o pin when the essi is not is use. 11111 sck0 (gpioc2) input / output input / output essi serial clock 0? this bidirectional pin provides the serial bit rate clock for the transmit section of the essi. the clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. port c gpio 2? this is a general purpose i/o pin when the essi is not is use. 11111 power, ground and peripheral signals overview, rev. 4 freescale semiconductor 2-17 sc00 (gpioc3) input / output input / output essi serial control pin 0? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used either for transmitter 1 output or for serial i/o flag 0. port c gpio 3? this is a general purpose i/o pin when the essi is not in use. 11111 sc01 (gpioc4) input / output input / output essi serial control pin 1? the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin is the receiver frame sync i/o. for synchronous mode, this pin is used either for transmitter 2 output or for serial i/o flag 1. port c gpio 4? this is a general purpose i/o pin when the essi is not in use. 11111 sc02 (gpioc5) input / output input / output essi serial control pin 2? this pin is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous more. when configured as an output, this pin is the internally generated frame sync signal. when configured as an input, this pin receives an external sync signal for the transmitter, and the receiver in the synchronous operation. port c gpio 5? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11111 table 2-12. enhanced synchronous serial interface 1 signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins std1 (gpiod0) output(z) input / output essi transmit data (std1) ?this output pin transmits serial data from the essi transmitter shift register. port d gpio 0 ?this is a general purpose i/o pin available when the essi is not in use. ??? 1 1 srd1 (gpiod1) input input / output essi receive data (srd1) ?this input pin receives serial data and transfers the data to the essi receive shift register. port d gpio 1 ?this is a general purpose i/o pin available when the essi is not in use. ??? 1 1 table 2-11. enhanced synchronous serial interface 0 (continued) signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins power, ground and peripheral signals 5685x digital signal controller user manual, rev. 4 2-18 freescale semiconductor sck1 (gpiod2) input / output input / output essi serial clock (sck1) ?this bidirectional pin provides the serial bit rate clock for the transmit section of the essi. the clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. port d gpio 2 ?this is a general purpose i/o pin available when the essi is not in use. ??? 1 1 sc10 (gpiod3) input / output input / output essi serial control pin 0 (sc10) ?the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used either for transmitter1 output or for serial i/o flag 0. port d gpio 3 ?this is a general purpose i/o pin available when the essi is not in use. ??? 1 1 sc11 (gpiod4) input / output input / output essi serial control pin 1 (sc11) ?the function of this pin is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this pin is the receiver frame sync i/o. for synchronous mode, this pin is used either for transmitter2 output or for serial i/o flag 1. port d gpio (4) ?this is a general purpose i/o pin available when the essi is not in use. ??? 1 1 sc12 (gpiod5) input / output input / output essi serial control pin 2 (sc12) ?this pin is used for frame sync i/o. sc02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this pin is the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port d gpio 5 ?this is a general purpose i/o pin available when the essi is not in use. ??? 1 1 table 2-12. enhanced synchronous serial interface 1 (continued) signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins power, ground and peripheral signals overview, rev. 4 freescale semiconductor 2-19 table 2-13. serial peripheral interface signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins miso (gpiof0) input / output input / output spi master in / slave out? this serial data pin is an input to a master device and an output from a slave device. the slave device places data on the miso line a half-cycle before the clock edge the master device uses to latch the data. the driver on this pin can be configured as an open-drain by the spi?s wired-or mode (wom) bit when this pin is configured for spi operation. port f gpio 0? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11?11 mosi (gpiof1) input / output(z) input / output spi master out / slave in? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge the slave device uses to latch the data. the driver on this pin can be configured as an open-drain by the spi?s wired-or mode (wom) bit when this pin is configured for spi operation. port f gpio 1? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11?11 sck (gpiof3) input / output input / output spi serial clock? this bidirectional pin provides a serial bit rate clock for the spi. this gated clock signal is an input to a slave device and is generated as an output by a master device. slave devices ignore the sck signal unless the ss pin is active low. in both master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge, where data is stable. the driver on this pin can be configured as an open-drain driver by the spi?s wom bit when this pin is configured for spi operation. when using wired-or mode, the user must provide an external pull-up device. port f gpio 2? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11?11 ss (gpiof3) input input / output spi slave select? this input pin selects a slave device before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration of the transaction. the ss line of the master must be held high. port f gpio 3? this is a general purpose i/o pin capable of being independently programmed as an input or output pin. 11?11 power, ground and peripheral signals 5685x digital signal controller user manual, rev. 4 2-20 freescale semiconductor table 2-14. clock and phase lock loop signals signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins extal input external crystal oscillator input? this input should be connected to an external crystal. if an external clock source other than a crystal oscillator is used, extal must be tied off. 11111 clko output clock output ?this pin outputs a buffered clock signal. when enabled, this signal is the system clock divided by four. 11111 xtal input / output crystal oscillator output? this output connects the internal crystal oscillator output to an external crystal. if an external clock source other than a crystal oscillator is used, xtal must be used as the input and the extal connected to v dda /2. 11111 table 2-15. jtag/eonce signals signal name signal type signal description 853 pins 854 pins 855 pins 857 pins 858 pins tck input test clock input? this input pin provides a gated clock to synchronize the test logic and to shift serial data to the jtag/eonce port. the pin is connected internally to a pull-down resistor. 11111 tdi input test data input? this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 11111 tdo output(z) test data output? this tri-statable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. 11111 tms input test mode select input? this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. 11111 trst input test reset? as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment when a hardware reset is required and it is necessary not to rest the jtag/eonce module. in this case, assert reset . do not assert trst . 11111 de input / output debug enable? this is an open-drain, bidirectional, active low signal. as an input, it is a means of entering debug mode of operation from an external command controller. as an output, it is a means of acknowledging the chip has entered debug mode. 11111 overview, rev. 4 freescale semiconductor 3-1 chapter 3 memory (mem) 5685x digital signal controller user manual, rev. 4 3-2 freescale semiconductor program boot rom overview, rev. 4 freescale semiconductor 3-3 3.1 introduction the 56800e provides separate program and data memory areas. the program area has a 21-bit address range, while the data area has a 24-bit address range. each area has a data width of 16 bits. in the 5685x, the active areas in memory include: ? up to 40k 16 bit program ram ? up to 24k 16 bit data ram ?1k 16 bit boot rom off-chip memory expansion capability up to 4mb program and 16mb data with four programmable chip select signals. 3.2 program boot rom the 5685x has 1k-word 16-bit on-chip program rom. the program rom contains the bootstrap firmware program able to perform initial loading of the internal program ram. it is located in program memory space at locations $1f0000-$1f03ff. the bootstrap program can load any program ram segment from an external memory or serial eeprom. on exiting the reset state the first instruction is fetched from the program rom ($1f0000) to start execution of the bootstrap program. the value on the input pins, moda, modb, and modc, when the last active reset source?reset pin, power-on reset, or software reset?deasserts, it will determine which bootstrap mode is entered. note: a cop reset via rst does not alter mod pins of the sim register since a cop reset by definition occurs unexpectedly during system operation, therefore possibly no longer providing the required mode inputs. note: a software reset via rst_sw does not alter mod pins of the sim register, thereby allowing users to reboot in a different mode without altering the hardware. some boot modes, specifically those transferring code to internal pram for execution, require header data to synchronize the peripheral, define the transfer start address in pram, and define the number of words to load. the following four points describe the required format for available boot modes: 1. the four byte ascii sequence boot (mode 1 only) 2. two words (4 bytes) defining the number of program words to be loaded (modes 0, 1, 4, 5, and 6 only) program boot rom 5685x digital signal controller user manual, rev. 4 3-4 freescale semiconductor 3. two words (4 bytes) starting address where loaded in the program memory (modes 0, 1, 4, 5, and 6 only) 4. the user program (two bytes for each 16-bit program word) on all boot modes the four-byte string boot loads b first in boot mode one. the bytes/words for the remaining data are loaded least significant byte/word first. the boot code is general-purpose and assumes the number of program words and starting address are valid for the user?s system. if the values are invalid, unpredictable results will occur. if a reserved mode is specified, the debughlt instruction will be executed causing the software to enter an infinite loop. once the bootstrap program completes loading the specified number of words, if applicable to that boot mode, the bootstrap program jumps to the starting address and executes the loaded program. some of the bootstrap routines reconfigure the memory map by setting the pram disable field in the sim control register. some bootstrap routines also make specific assumptions about the external clock frequency being applied to the part. 3.2.1 boot mode 0: bootstrap from byte-wide external memory the pram disable remains zero, leaving both internal program and data ram enabled. the bootstrap program loads program memory from a byte-wide memory located at $040000 using cs0 as the chip select, before jumping to the start of the user code. 3.2.2 boot mode 1: bootstrap from spi the pram disable remains zero, leaving both internal program and data ram enabled. the bootstrap program loads program memory from a serial eeprom via the spi. gpiof3 is an alternative function of the slave select _b (ss ). when configured and programmed, the alternative function can be used as the ss output. this mode is compatible with atmel at25xxx and at45xxx series serial eeproms. in order to determine the correct spi configuration, the first four bytes in the serial memory must be the string boot in ascii. they are: $42, $4f, $4f and $54. if, after trying all three configurations, boot is not read, the part will move to the debug halt state. after the string boot, the data should continue as described in the data sequence above. after loading the user program, gpiof3 is returned to its power-on reset state?input under peripheral control?and the bootstrap program jumps to the start of the user code. this boot loader assumes the external clock is being applied at a frequency between 2mhz and 4mhz. for some external devices, it enables the pll during boot loading but always leaves the pll off when complete. program boot rom overview, rev. 4 freescale semiconductor 3-5 3.2.3 boot mode 2: normal expanded mode the pram disable remains at zero, leaving both internal program and data ram enabled. no code is loaded. the bootstrap program simply vectors to external program memory location p:$040000 using cs0 as the chip select. 3.2.4 boot mode 3: development expanded mode the pram disable remains at one, leaving internal data ram enabled, but the internal program ram is disabled. all references to internal program memory space are subsequently directed to external program memory. no code is loaded. the bootstrap program simply vectors to program memory location p:$000000 using cs0 as the chip select. 3.2.5 boot mode 4: bootstrap from host port?single strobe clocking the pram disable remains at zero, leaving both internal program and data ram enabled. the bootstrap program configures the host port for single strobe access, loading program memory from the host port before jumping to the start of the user code. 3.2.6 boot mode 5: bootstrap from host port?dual strobe clocking the pram disable remains at zero, leaving both internal program and data ram enabled. the bootstrap program configures the host port for dual strobe access, loading program memory from the host port before jumping tot he start of the user code. 3.2.7 boot mode 6: bootstrap from sci the pram disable remains at zero, leaving both internal program and data ram enabled. it configures the sci for 38400 baud transfers with a 4mhz or 19200 with 2mhz crystals. it also enables the pll to operate during the boot process. the bootstrap program then loads program memory from the sci port and jumps to the start of the user code. external clocking must be between 2mhz and 4mhz. it uses the pll but leaves it off when complete. the data format is: ? one start bit ? eight-data bits ? no parity bit ? one stop bit ? flow control off 3.2.8 boot mode 7: reserved for future use memory maps 5685x digital signal controller user manual, rev. 4 3-6 freescale semiconductor 3.3 memory maps memory maps for each of the five devices are illustrated in figure 3-1 through figure 3-5 . figure 3-1. 56853 memory map program space $000000 $00a000 prog ram 1 $1fffff prog rom $1f0400 $1f0000 external memor y 2 data space $000000 data ram 1 $1ffc00 on-chip external memory 3 $1fffff peripherals 4 $ffffff external memory $ffff00 eonce $003000 $001000 1. can be disabled resulting in this space being external memory. 2. in operating mode 2, chip select 0 is initially set to $040000 - $07ffff. 3. in operating mode 0, chip select 0 is initially set to $040000 - $07ffff. 4. the range of short i/o space is: $1fffc0 - $1fffff. reserved memory maps overview, rev. 4 freescale semiconductor 3-7 figure 3-2. 56854 memory map figure 3-3. 56855 memory map program space $000000 prog ram 1 $1fffff prog rom $1f0400 $1f0000 external memory 2 data space $000000 data ram 1 $1ffc00 on-chip external memory 3 $1fffff peripherals 4 $ffffff external memory $ffff00 eonce $004000 $004000 1. can be disabled resulting in this space being external memory. 2. in operating mode 2, chip select 0 is initially set to $040000 - $07ffff. 3. in operating mode 0, chip select 0 is initially set to $040000 - $07ffff. 4. the range of short i/o space is: $1fffc0 - $1fffff. reserved program space $000000 prog ram 1 1. can be disabled, in which case this space is external memory. $1fffff prog rom $1f0400 $1f0000 external memory 2 2. in operating mode 2, chip select 0 is initially set to $040000 - $07ffff. data space $000000 $006000 data ram 1 $1ffc00 on-chip external memory 3 3. in operating mode 0, chip select 0 is initially set to $040000 - $07ffff. $1fffff peripherals 4 4. the range of short i/o space is: $1fffc0 - $1fffff. $ffffff external memory $ffff00 eonce $006000 reserved memory maps 5685x digital signal controller user manual, rev. 4 3-8 freescale semiconductor figure 3-4. 56857 memory map figure 3-5. 56858 memory map program space $000000 $00a000 prog ram $1fffff prog rom $1f0400 $1f0000 data space $000000 $006000 data ram $1ffc00 on-chip $1fffff peripherals 1 1. the range of short i/o space is: $1fffc0 - $1fffff. $ffffff $ffff00 eonce reserved program space $000000 $00a000 prog ram 1 $1fffff prog rom $1f0400 $1f0000 data space $000000 $006000 data ram 1 $1ffc00 on-chip $1fffff peripherals 4 $ffffff $ffff00 eonce external memory 3 external memory 2 external memory 1. can be disabled resulting in this space being external memory. 2. in operating mode 2, chip select 0 is initially set to $040000. 3. in operating mode 0, chip select 0 is initially set to $040000 - $07ffff. 4. the range of short i/o space is: $1fffc0 - $1fffff. reserved memory maps overview, rev. 4 freescale semiconductor 3-9 note: the x (data) address space for all parts is actually 24 bits ($000000 - $ffffff) but only 21 bits are brought out externally. the chip selects can be programmed to allow data accesses above $1fffff. in this case the data space can be thought of as multiple 2m word pages. 3.3.1 memory register summary this summary lists all accessible eonce memory mapped registers in the 5685x devices, in table 3-1 . the peripheral system configurations are listed in table 3-15 . 3.3.1.1 memory mapped registers table 3-1 lists all of the eonce memory mapped registers in the 5685x devices. please consult the dsp56800e reference manual (dsp56800erm) for complete details of the following table. table 3-1. eonce memory map (eonce_base = $ffff00) address offset register acronym register name base + $ff otx1/orx1 transmit register upper word receive register upper word base + $fe otx/orx transmit register receive register base + $fd otxrxsr transmit /receive status/ control reg. base + $fc oclsr core lock/unlock status register reserved base + $a0 ocr control register base + $9f ? instruction step counter base + $9e oscntr instruction step counter base + $9d osr status register base + $9c obase peripheral base address register base + $9b otbcr trace buffer control register base + $9a otbpr trace buffer pointer register base + $99 ? trace buffer register stages base + $98 otb trace buffer register stages base + $97 ? breakpoint unit [0] control register base + $96 obcr breakpoint unit [0] control register base + $95 ? breakpoint 1 unit [0] address register base + $94 obar1 breakpoint 1 unit [0] address register base + $93 ? breakpoint 2 unit [0] address register base + $92 obar2 breakpoint 2 unit [0] address register base + $91 ? breakpoint 1 unit [0] mask register base + $90 obmsk breakpoint 1 unit [0] mask register memory maps 5685x digital signal controller user manual, rev. 4 3-10 freescale semiconductor 3.3.1.2 peripheral mapped registers the following tables provide lists of all of the peripheral memory mapped registers in the 5685x devices. each is discussed in this manual. reserved $8e obcntr eonce breakpoint unit [0] counter reserved reserved reserved $8a oescr external signal control register reserved table 3-2. system integration module register address map (sys_base = $1fff08) see chapter 4 address offset register acronym register name access type chapter location base + $0 scr sim control register read/write section 4.6.1 base + $1 scd1 software control data 1 register read/write section 4.6.2 base + $2 scd2 software control data 2 register read/write section 4.6.3 table 3-3. external memory interface registers address map (emi_base = $1ffe40) see chapter 5 address offset register acronym register name access type chapter location base + $0 cs0 chip select address & block size read/write section 5.6.1 base + $1 cs1 chip select address & block size read/ write base + $2 cs2 chip select address & block size read/write base + $3 cs3 chip select address & block size read/write base + $8 csor_0 chip select options register 0 read/write section 5.6.2 base + $9 csor_1 chip select options register 1 read/ write base + $a csor_2 chip select options register 2 read/write base + $b csor_3 chip select options register 3 read/write base + $10 bcr bus control register read/write section 5.6.3 table 3-1. eonce memory map (e once_base = $ffff00) (continued) address offset register acronym register name memory maps overview, rev. 4 freescale semiconductor 3-11 table 3-4. clock generation module registers address map (cgm_base = $1fff10) see chapter 6 address offset register acronym register name access type chapter location base + $0 cgmcr control register read/write section 6.6.1 base + $1 cgmdb divide-by register read/write section 6.6.2 base + $2 cgmtod time-of-day register read/write section 6.6.3 table 3-5. computer operating properly module registers address map (cop_base = $1fffd0) see chapter 7 address offset register acronym register name access type chapter location base + $0 copctl control register read/write section 7.9.1 base + $1 copto time-out register read/write section 7.9.2 base + $2 copctr counter register read/write section 7.9.3 table 3-6. interrupt control registers address map (itcn_base = $1fff20) see chapter 8 address offset register acronym register name access type chapter location base + $0 ipr0 interrupt priority register 0 read/write section 8.7.1 base + $1 ipr1 interrupt priority register 1 read/write section 8.7.2 base + $2 ipr2 interrupt priority register 2 read/write section 8.7.3 base + $3 ipr3 interrupt priority register 3 read/write section 8.7.4 base + $4 ipr4 interrupt priority register 4 read/write section 8.7.5 base + $5 ipr5 interrupt priority register 5 read/write section 8.7.6 base + $6 ipr6 interrupt priority register 6 read/write section 8.7.7 base + $7 ipr7 interrupt priority register 7 read/write section 8.7.8 base + $8 ipr8 interrupt priority register 8 read/write section 8.7.9 base + $9 vba vector base address register read/write section 8.7.10 base + $a fim0 fast interrupt match register 0 read/write section 8.7.11 base + $b fival0 fast interrupt vector address low 0 read/write section 8.7.12 base + $c fivah0 fast interrupt vector address high 0 read/write base + $d fim1 fast interrupt match register 1 read/write section 8.7.13 base + $e fival1 fast interrupt vector low register 1 read/write section 8.7.14 base + $f fivah1 fast interrupt vector high register 1 read/write base + $10 irqp0 irq pending register 0 read only section 8.7.15 base + $11 irqp1 irq pending register 1 read only base + $12 irqp2 irq pending register 2 read only base + $13 irqp3 irq pending register 3 read only base + $14 irqp4 irq pending register 4 read only base + $1a ictl interrupt control register read/write section 8.7.16 memory maps 5685x digital signal controller user manual, rev. 4 3-12 freescale semiconductor table 3-7. direct memory access 0 register address map (dma0_base = $1ffec0) see chapter 9 address offset register acronym register name access type chapter location base + $0 dma_0_tc transfer control register read/write section 9.6.1 base + $1 dma_0_cqs circular queue size register read/write section 9.6.2 base + $2 dma_0_tc transfer count register read/write section 9.6.3 base + $3 dma_0_dal destination address-low register read/write section 9.6.4 base + $4 dma_0_dah destination address-high register read/write section 9.6.5 base + $5 dma_0_sal source address-low register read/write section 9.6.6 base + $6 dma_0_sah source address-high register read/write section 9.6.7 table 3-8. direct memory access 1 register address map (dma1_base = $1ffec8) see chapter 9 address offset register acronym register name access type chapter location base + $0 dma_1_tc transfer control register read/write section 9.6.1 base + $1 dma_1_cqs circular queue size register read/write section 9.6.2 base + $2 dma_1_tc transfer count register read/write section 9.6.3 base + $3 dma_1_dal destination address-low register read/write section 9.6.4 base + $4 dma_1_dah destination address-high register read/write section 9.6.5 base + $5 dma_1_sal source address-low register read/write section 9.6.6 base + $6 dma_1_sah source address-high register read/write section 9.6.7 table 3-9. direct memory access 2 register address map (dma2_base = $1ffed0) see chapter 9 address offset register acronym register name access type chapter location base + $0 dma_2_tc transfer control register read/write section 9.6.1 base + $1 dma_2_cqs circular queue size register read/write section 9.6.2 base + $2 dma_2_tc transfer count register read/write section 9.6.3 base + $3 dma_2_dal destination address-low register read/write section 9.6.4 base + $4 dma_2_dah destination address-high register read/write section 9.6.5 base + $5 dma_2_sal source address-low register read/write section 9.6.6 base + $6 dma_2_sah source address-high register read/write section 9.6.7 memory maps overview, rev. 4 freescale semiconductor 3-13 table 3-10. direct memory access 3 register address map (dma3_base = $1ffed8) see chapter 9 address offset register acronym register name access type chapter location base + $0 dma_3_tc transfer control register read/write section 9.6.1 base + $1 dma_3_cqs circular queue size register read/write section 9.6.2 base + $2 dma_3_tc transfer count register read/write section 9.6.3 base + $3 dma_3_dal destination address-low register read/write section 9.6.4 base + $4 dma_3_dah destination address-high register read/write section 9.6.5 base + $5 dma_3_sal source address-low register read/write section 9.6.6 base + $6 dma_3_sah source address-high register read/write section 9.6.7 table 3-11. direct memory access 4 register address map (dma4_base = $1ffee0) see chapter 9 address offset register acronym register name access type chapter location base + $0 dma_4_tc transfer control register read/write section 9.6.1 base + $1 dma_4_cqs circular queue size register read/write section 9.6.2 base + $2 dma_4_tc transfer count register read/write section 9.6.3 base + $3 dma_4_dal destination address-low register read/write section 9.6.4 base + $4 dma_4_dah destination address-high register read/write section 9.6.5 base + $5 dma_4_sal source address-low register read/write section 9.6.6 base + $6 dma_4_sah source address-high register read/write section 9.6.7 table 3-12. direct memory access 5 register address map (dma5_base = $1ffee8) see chapter 9 address offset register acronym register name access type chapter location base + $0 dma_5_tc transfer control register read/write section 9.6.1 base + $1 dma_5_cqs circular queue size register read/write section 9.6.2 base + $2 dma_5_tc transfer count register read/write section 9.6.3 base + $3 dma_5_dal destination address-low register read/write section 9.6.4 base + $4 dma_5_dah destination address-high register read/write section 9.6.5 base + $5 dma_5_sal source address-low register read/write section 9.6.6 base + $6 dma_5_sah source address-high register read/write section 9.6.7 memory maps 5685x digital signal controller user manual, rev. 4 3-14 freescale semiconductor table 3-13. serial communication interface 0 registers address map (sci0_base = $1fffe0) see chapter 10 address offset register acronym register name access type chapter location base + $0 sci_0_br baud rate register read/write section 10.9.1 base + $1 sci_0_cr control register read/write section 10.9.2 base + $2 sci_0_cr2 control register 2 read/write section 10.9.3 base + $3 sci_0_sr status register read only section 10.9.4 base + $4 sci_0_dr data register read/write section 10.9.5 table 3-14. serial communication interface 1 registers address map (sci1_base = $1ffdf8) see chapter 10 address offset register acronym register name access type chapter location base + $0 sci_1_br baud rate register read/write section 10.9.1 base + $1 sci_1_cr control register read/write section 10.9.2 base + $2 sci_1_cr2 control register 2 read/write section 10.9.3 base + $3 sci_1_sr status register read only section 10.9.4 base + $4 sci_1_dr data register read/write section 10.9.5 table 3-15. serial peripheral interface registers address map (spi_base =$1fffe8) see chapter 11 address offset register acronym register name access type chapter location base + $0 spscr status and control register read/write section 11.11.1 base + $1 spdscr data size and control register read/write section 11.11.2 base + $2 spdrr data receive register read-only section 11.11.3 base + $3 spdtr data transmit register write-only section 11.11.4 note: spi registers are not available on the 56855 memory maps overview, rev. 4 freescale semiconductor 3-15 table 3-16. enhanced synchronous serial interface 0 registers address map (essi0_base = $1ffe20) see chapter 12 address offset register acronym register name access type chapter location base + $0 essi_0_stx0 transmit register 0 write-only section 12.8.1 base + $1 essi_0_stx1 transmit register 1 write-only section 12.8.2 base + $2 essi_0_stx2 transmit regsiter 2 write-only section 12.8.3 base + $3 essi_0_srx receive register read-only section 12.8.4 base + $4 essi_0_ssr status register read-only section 12.8.7 base + $5 essi_0_scr2 control register 2 read/write section 12.8.8 base + $6 essi_0_scr3 control register 3 read/write section 12.8.9 base + $7 essi_0_scr4 control register 4 read/write section 12.8.10 base + $8 essi_0_stxcr transmit control register read/write section 12.8.11 base + $9 essi_0_srxcr receive control register read/write base + $a essi_0_stsr time slot register write-only section 12.8.12 base + $b essi_0_sfcsr fifo control / status register read-only section 12.8.13 base + $c essi_0_tsma transmit slot mask register read/write section 12.8.14 base + $d essi_0_tsmb transmit slot mask register read/write base + $e essi_0_rsma receive slot mask register read/write section 12.8.15 base + $f essi_0_rsmb receive slot mask register read/write table 3-17. enhanced synchronous seri al interface 1 registers address map (essi1_base =$1ffe00) see chapter 12 address offset register acronym register name access type chapter location base + $0 essi_1_stx0 transmit register 0 write-only section 12.8.1 base + $1 essi_1_stx1 transmit register 1 write-only section 12.8.2 base + $2 essi_1_stx2 transmit regsiter 2 write-only section 12.8.3 base + $3 essi_1_srx receive register read-only section 12.8.4 base + $4 essi_1_ssr status register read-only section 12.8.7 base + $5 essi_1_scr2 control register 2 read/write section 12.8.8 base + $6 essi_1_scr3 control register 3 read/write section 12.8.9 base + $7 essi_1_scr4 control register 4 read/write section 12.8.10 base + $8 essi_1_stxcr transmit control register read/write section 12.8.11 base + $9 essi_1_srxcr receive control register read/write base + $a essi_1_stsr time slot register write-only section 12.8.12 base + $b essi_1_sfcsr fifo control / status register read-only section 12.8.13 base + $c essi_1_tsma transmit slot mask register read/write section 12.8.14 base + $d essi_1_tsmb transmit slot mask register read/write base + $e essi_1_rsma receive slot mask register read/write section 12.8.15 base + $f essi_1_rsmb receive slot mask register read/write memory maps 5685x digital signal controller user manual, rev. 4 3-16 freescale semiconductor table 3-18. quad timer registers address map (tmr_base = $1ffe80) see chapter 13 address offset register acronym register name access type chapter location base + $6, $e, $16, $1e ctrl timer channel control register read/write section 13.9.1 base + $7, $f, $17, $f scr timer channel status/control reg. read/write section 13.9.2 base + $0, $8, $10, $18 cmp1 timer channel compare register 1 read/write section 13.9.3 base + $1, $9, $11, $19 cmp2 timer channel compare register 2 read/write section 13.9.4 base + $2, $a, $12, $1a cap timer channel capture register read/write section 13.9.5 base + $3, $b, $13, $1b load timer channel load register read/write section 13.9.6 base + $4, $c, $14, $1c hold timer channel hold register read/write section 13.9.7 base + $5, $d, $15, $1d cntr timer channel counter register read/write section 13.9.8 table 3-19. time-of-day registers address map (tod_base = $1fffc0) see chapter 14 address offset register acronym register name access type chapter location base + $0 todcs control/status register read/write section 14.6.2 base + $1 todcsl clock scaler load register read-only section 14.6.3 base + $2 todsec seconds register read-only section 14.6.4 base + $3 todsal seconds alarm register read-only section 14.6.5 base + $4 todmin minutes register read-only section 14.6.6 base + $5 todmal minutes alarm register read-only section 14.6.7 base + $6 todhr hour register read-only section 14.6.8 base + $7 todhal hour alarm register read-only section 14.6.9 base + $8 todday days register read-only section 14.6.10 base + $9 toddal days alarm register read-only section 14.6.11 table 3-20. general purpose input/output a register map (gpioa_base = $1ffe60) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_a_per peripheral enable register read/write section 15.8.1 base + $1 gpio_a_ddr data direction register read/write section 15.8.9 base + $2 gpio_a_dr data register read/write section 15.8.17 base + $3 gpio_a_pur peripheral enable register read/write section 15.8.25 memory maps overview, rev. 4 freescale semiconductor 3-17 table 3-21. general purpose input/output b register map (gpiob_base = $1ffe64) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_b_per peripheral enable register read/write section 15.8.2 base + $1 gpio_b_ddr data directionregister read/write section 15.8.10 base + $2 gpio_b_dr data register read/write section 15.8.18 base + $3 gpio_b_pur peripheral enable register read/write section 15.8.26 table 3-22. general purpose input/output c register map (gpioc_base = $1ffe68) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_c_per peripheral enable register read/write section 15.8.3 base + $1 gpio_c_ddr data directionregister read/write section 15.8.11 base + $2 gpio_c_dr data register read/write section 15.8.19 base + $3 gpio_c_pur peripheral enable register read/write section 15.8.27 table 3-23. general purpose input/output d register map (gpiod_base = $1ffe6c) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_d_per peripheral enable register read/write section 15.8.4 base + $1 gpio_d_ddr data directionregister read/write section 15.8.12 base + $2 gpio_d_dr data register read/write section 15.8.20 base + $3 gpio_d_pur peripheral enable register read/write section 15.8.28 table 3-24. general purpos e input/output e register map (gpioe_base = $1ffe70) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_e_per peripheral enable register read/write section 15.8.5 base + $1 gpio_e_ddr data directionregister read/write section 15.8.13 base + $2 gpio_e_dr data register read/write section 15.8.21 base + $3 gpio_e_pur peripheral enable register read/write section 15.8.29 memory maps 5685x digital signal controller user manual, rev. 4 3-18 freescale semiconductor table 3-25. general purpose input/output f register map (gpiof_base = $1ffe74) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_f_per peripheral enable register read/write section 15.8.6 base + $1 gpio_f_ddr data directionregister read/write section 15.8.14 base + $2 gpio_f_dr data register read/write section 15.8.22 base + $3 gpio_f_pur peripheral enable register read/write section 15.8.30 table 3-26. general purpose input/output g register map (gpiog_base = $1ffe78) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_g_per peripheral enable register read/write section 15.8.7 base + $1 gpio_g_ddr data directionregister read/write section 15.8.15 base + $2 gpio_g_dr data register read/write section 15.8.23 base + $3 gpio_g_pur peripheral enable register read/write section 15.8.31 table 3-27. general purpose input/output h register map (gpioh_base = $1ffe7c) see chapter 15 address offset register acronym register name access type chapter location base + $0 gpio_h_per peripheral enable register read/write section 15.8.8 base + $1 gpio_h_ddr data directionregister read/write section 15.8.16 base + $2 gpio_h_dr data register read/write section 15.8.24 base + $3 gpio_h_pur peripheral enable register read/write section 15.8.32 table 3-28. host interface 8 registers (hi8_base =$1fffd8) see chapter 16 address offset register acronym register name access type chapter location base + $0 hcr control register read/write section 16.8.1 base + $1 hsr status register read/write section 16.8.2 base + $2 hrx receive data register write-only section 16.8.3 htx transmit data register read-only section 16.8.4 note: hi8 registers are not available on the 56855 memory maps overview, rev. 4 freescale semiconductor 3-19 3.3.2 interrupt vectors the interrupt vectors for the 5685x devices reside in the program memory area. default addresses of each vector is listed in the interrupt controller (itcn) chapter, and outlined in table 8-3 . reset is considered to be the highest priority interrupt and takes precedence over all other interrupts. if the reset pin is pulled low, the interrupt controller generates a reset vector address for the core. note: the reset vector for the 5685x series devices is $1f0000, the start address of the internal boot rom. memory maps 5685x digital signal controller user manual, rev. 4 3-20 freescale semiconductor system integration module (sim), rev. 4 freescale semiconductor 4-1 chapter 4 system integrat ion module (sim) 5685x digital signal controller user manual, rev. 4 4-2 freescale semiconductor features system integration module (sim), rev. 4 freescale semiconductor 4-3 4.1 introduction the system integration module (sim) is responsible for several system control functions including: ? clock generation ? reset generation ? power mode control ? boot mode control ? memory map control ? external i/o configuration ? software control 4.2 features the following list contains distinctions of sim: ? five system bus clocks with pipeline hold-off support ? data ram clock with hold-off control ? ipbus interface clock with hold-off control ? system external memory interface four-phase clock with hold-off control ? 56800e core system clock ? general purpose clock (both standard and inverted versions) ? three system clocks for non pipelined interfaces ? pclk clock for 56800e core ? nclk clock for 56800e core ? a continuously running system clock ? a peripheral bus (ipbus) clock, both on standard and inverted versions ? an external clock output with disable ? a core stall control used to stall the 56800e core system clock for dma mastership ? a peripheral bus clock phase indicator ? three power modes to control power utilization: ? stop mode shuts down the 56800e core, system clocks, and the peripheral clock. stop mode entry can optionally disable pll and oscillator providing a choice of lower power vs. a faster restart. block diagram 5685x digital signal controller user manual, rev. 4 4-4 freescale semiconductor ? wait mode shuts down the 56800e core, and unnecessary system clock operation. ? run mode supports full part operation. ? controls to enable/disable the 56800e core wait and stop instructions ? 32-cycle extended chip internal reset ? 32-cycle extended time-of-day reset (responds only to por reset) ? 32-cycle extended reset for the clock generated module (cgm) ? software initiated reset ? controls to redirect internal data and/or program ram accesses to the external memory interface ? software boot mode control register, initialized at any reset (except cop reset) from external pins ? a hold off output to coordinate peripheral bus transactions with the system bus pipeline ? two 16-bit registers reset only by a power-on reset usable for general purpose software control 4.3 block diagram the system integration module (sim) is depicted in figure 4-1 . block diagram system integration module (sim), rev. 4 freescale semiconductor 4-5 figure 4-1. system integration module power modes: run, wait, pre-stop, stop * cont sys_clk_in is a synthesized clock tree fed by the clk_sys cont output of sim power mode control p/d ram disable software control reg 1 software control reg 2 sim control register bus interface ipbus modes a, b, c stop/wait disable ipbus slow write clock generator master clk scan clk ipbb hold off dram hold off core stall clkout disable nclk enable pipelined sys clks other sys clks 56800e clks periph bus clk periph bus phase hold off cont sys clk* internal clk por disable reset sw reset pin reset por reset cop bscan enable reset generator reset por reset reset core reset reset tod cont sys clk in cont sys clk in osc_lopwr pll shutdown p5stop p5wait int pending jtdebreq /de omr6_sd signal description 5685x digital signal controller user manual, rev. 4 4-6 freescale semiconductor 4.4 signal description a description of the system integration module (sim) signals are shown in tables 4-1 through tables 4-6 . 4.4.1 sim interface signals table 4-1. ipbus signals name type clock domain function clk_ipb input ? peripheral bus clock rd_data_z output clk_ipb read data (tri-stateable) wr_data input clk_ipb write data addr input clk_ipb r/w address (two lsbs of ipbus address) rwb input clk_ipb write enable (active low) module_en input clk_ipb module enable (active low) table 4-2. clock generator inputs/outputs name type clock domain function clk_sys_dram output clk_mstr system clock to data ram with hold off support clk_sys_ipbb output clk_mstr system clock to ipbus bridge with hold off support clk_sys_cpuclk output clk_mstr system clock to 56800e core with hold off support clk_cpu_pclk output clk_mstr feeds pclk input on 56800e core clk_cpu_nclk output clk_mstr feeds nclk input on 56800e core clk_cpu_wclk output clk_mstr feeds wrap_clk input on 56800e core clk_sys_genri output clk_mstr general purpose system clock with hold off support clk_sys_genri_inv output clk_mstr general purpose system clock with hold off support-inverted clk_sys_cont output clk_mstr continuous system clock (feeds back into sim) clk_per_cont output clk_mstr peripheral bus clock clk_per_cont_inv output clk_mstr inverted peripheral bus clock clk_clkout output clk_mstr output to clkout output pad pclk_phase output clk_mstr indicates peripheral clock phase (1=address 0=data) hold off output clk_mstr indicates at least one hold off control is asserted, used to abort peripheral bus transactions c7waitst output clk_mstr indicates to core if it?s system clock is to be stalled for reasons other than a core reset (e.g. a hold off or core_stall) clk_mstr input clk_mstr master input clock from cgm module clk_osc input ? master clock direct from oscillator bypassing cgm module clk_scan input ? scan mode clock hold_dram input ? hold off request from data ram hold_ipbb input clk_mstr hold off request from ipbus bridge signal description system integration module (sim), rev. 4 freescale semiconductor 4-7 n1clken input clk_mstr nclk enable signal from 56800e core jhawkcoretap_en input clk_mstr re synchronized to clk_sys_cont and used to disable clk_cpu_pclk after reset if core tap disabled core_stall input ? core stall request from sbc for dma mastership table 4-3. reset ge nerator inputs/outputs name type clock domain function rst_core output clk_sys_cont synchronized and extended reset to 56800e core rst_periph output clk_sys_cont synchronized and extended reset to general peripheral logic rst_tod output clk_sys_cont synchronized and extended reset to modules using only power on reset (the tod and cop modules) rst_cgm output clk_osc synchronized and extended reset to cgm module rst_pin input ? reset request from external reset pin rst_por input ? reset request from power-on reset module rst_cop input ? reset request from cop module table 4-4. register inputs/outputs name type clock domain function mode_cba input ? from modec, b, a input pads, captured at reset in sim control register to indicate software boot mode pram_dbl output clk_ipb redirect program ram accesses to external memory if dram_dbl output clk_ipb redirect data ram accesses to external memory if stop_dbl output clk_ipb direct the core to disable the stop instruction wait_dbl output clk_ipb direct the core to disable the wait instruction table 4-5. power mode control inputs/outputs name type clock domain function stopmd output clk_sys_cont indicates sim is in stop mode waitmd output clk_sys_cont indicates sim is in wait mode runmd output clk_sys_cont indicates sim is in run mode osc_lopwr output clk_sys_cont puts oscillator into low power mode configuration during stop mode pll_shutdown ou tput clk_sys_cont shuts down pll and puts it into bypass mode when entering stop mode p5stop input clk_sys_cont input from core indicating stop instruction executed p5wait input clk_sys_cont input from core indicating wait instruction executed int_pend input clk_sys_cont input from in tc indicating interrupt is pending jtdebreq input clk_sys_cont input from core indicating a jtag debug mode request table 4-2. clock generato r inputs/outputs (continued) name type clock domain function module memory map 5685x digital signal controller user manual, rev. 4 4-8 freescale semiconductor 4.5 module memory map the system integration module (sim) contains three programmable 16-bit registers. the address range from $1fff08 to $1fff0f is allocated to the sim. the register is accessed by each of the eight-memory mapped addresses, delineated in tables 4-7 . to avoid unpredictable behavior, reserved registers must not be written. a read from an address without an associated register returns unknown data. de input clk_sys_cont input from de input pad used to enter once debug mode omr6_sd input clk_sys_cont from core omr6 register to enable fast stop mode recovery bscan_ebl input ? from external tap controller indicating boundary scan mode table 4-6. derived clock inputs name type clock domain function clk_sys_cont_in input clk_sys_cont continuous clock fed by synthesized clock tree originating at sim output clk_sys_cont table 4-7. system integration m odule memory map (sim_base = $1fff08) address offset register acronym register name access type chapter location base + $0 scr sim control register read/write section 4.6.1 base + $1 scd1 software control register 1 read/write section 4.6.2 base + $2 scd2 software control register 2 read/write section 4.6.3 add. offset register name 151413121110987654321 0 $0 scr r 0 boot mode chip rev 0 eonce ebl clkout dbl pram dbl dram dbl sw dbl stop dbl wait dbl w $1 scid1 r software control data 1 w $2 scd2 r software control data 2 w r 0 read as 0 w reserved figure 4-2. sim register map summary table 4-5. power mode control inputs/outputs (continued) name type clock domain function register descriptions (sys_base = $1fff08) system integration module (sim), rev. 4 freescale semiconductor 4-9 4.6 register descriptions (sys_base = $1fff08) 4.6.1 sim control register (scr) figure 4-3. sim control register (scr) see programmer?s sheet on appendix page b-8 4.6.1.1 reserved?bit 15 this bit is reserved or not implemented. it is read as 0, but it cannot be modified by writing. 4.6.1.2 boot mode?bits 14?12 these boot mode bits replace the mode bits in the 56800e omr. this field is set to the value on the input pins, moda, modb, and modc, when the last active reset source?reset pin, power-on reset?deasserts. synchronous reset (software or cop) do not update boot mode assuming applications software will set the desired field value prior to the reset. the core always begins execution after reset from the base on the on-chip rom. the software in rom will perform one of the several boot actions based on the value of boot mode. note: a cop reset via cop_rst does not alter these registers since a cop reset by definition occurs unexpectedly during system operation, therefore possibly no longer providing the required mode inputs. note: a software reset via rst_ sw does not alter these registers, thereby allowing users to reboot in a different mode without altering the hardware. the 56800e core begins execution from the base of the on-chip rom. the software in rom will perform one of several boot actions based on the value of boot mode. some boot modes, specifically those transferring code to internal pram for execution, require header data to synchronize the peripheral, define the transfer start address in pram, and define the number of words to load. the following four points describe the required format for boot mode: 1. the four byte ascii sequence boot (mode 1 only) 2. two words (4 bytes) defining the number of program words to be loaded (modes 0, 1, 4, 5, and 6 only) base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 boot mode chip rev 0 eonce ebl clkout dbl pram dbl dram dbl sw rst stop dbl wait dbl write reset 0 0 0 000010 0 0 0 0 0 0 0 register descriptions (sys_base = $1fff08) 5685x digital signal controller user manual, rev. 4 4-10 freescale semiconductor 3. two word (4 bytes) starting address where loaded in the program memory (modes 0, 1, 4, 5, and 6 only) 4. the user program (two bytes for each 16-bit program word) on all boot modes in boot mode 1, the four-byte string boot loads b first in boot mode one. the bytes/words for the remaining data are loaded least significant byte/word first. the boot code is general-purpose, and assumes the number of program words and starting address are valid for the users system. if the values are invalid, unpredictable results will occur. if a reserved mode is specified, the debughlt instruction will be executed causing the software to enter an infinite loop. once the bootstrap program completes loading the specified number of words, if applicable to that boot mode, the bootstrap program jumps to the starting address and executes the loaded program. some of the bootstrap routines reconfigure the memory map by setting the pram disable field. some bootstrap routines also make specific assumptions about the external clock frequency being applied to the part. 4.6.1.2.1 boot mode 0: bootstrap from byte-wide external memory the pram disable remains zero, leaving both internal program and data ram enabled. the bootstrap program loads program memory from a byte-wide memory located at $040000 using cs0 as the chip select, before jumping to the start of the user code. 4.6.1.2.2 boot mode 1: bootstrap from spi the pram disable remains zero, leaving both internal program and data ram enabled. the bootstrap program loads program memory from a serial eeprom via the spi. gpiof3 is an alternative function of the ss , which when configured and programmed, can be used as the ss output. this mode is compatible with atmel at25xxx and at45xxx series serial eeproms. in order to determine the correct spi configuration, the first four bytes in the serial memory must be the string boot in ascii. they are: $42, $4f, $4f and $54. if, after trying all three configurations, boot is not read, the part will move to the debug halt state. after the string boot, the data should continue as described in the data sequence above. after loading the user program, gpiof3 is returned to its power-on reset state?input under peripheral control?and the bootstrap program jumps to the start of the user code. this boot loader assumes the external clock is being applied at a frequency between 2mhz and 4mhz. for some external devices, it enables the pll during boot loading but always leaves the pll off when complete. 4.6.1.2.3 boot mode 2: normal expanded mode the pram disable remains at zero, leaving both internal program and data ram enabled. no code is loaded. the bootstrap program simply vectors to external program memory location p:$040000 using cs0 as the chip select. register descriptions (sys_base = $1fff08) system integration module (sim), rev. 4 freescale semiconductor 4-11 4.6.1.2.4 boot mode 3: development expanded mode the pram disable is set to one, leaving internal data ram enabled, but the internal program ram is disabled. all references to internal program memory space are subsequently directed to external program memory. no code is loaded. the bootstrap program simply vectors to program memory location p:$000000 using cs0 as the chip select. 4.6.1.2.5 boot mode 4: bootstrap from host port?single strobe clocking the pram disable remains at zero, leaving both internal program and data ram enabled. the bootstrap program configures the host port for single strobe access, loading program memory from the host port before jumping to the start of the user code. note: this mode becomes a reserved mode on parts lacking a host port interface. 4.6.1.2.6 boot mode 5: bootstrap from host port?dual strobe clocking the pram disable remains at zero, leaving both internal program and data ram enabled. the bootstrap program configures the host port for dual strobe access, loading program memory from the host port before jumping to the start of the user code. note: this mode becomes a reserved mode on parts lacking a host port interface. 4.6.1.2.7 boot mode 6: bootstrap from sci the pram disable remains at zero, leaving both internal program and data ram enabled. it configures the sci for 38400 baud transfers with a 4mhz or 19200 with a 2mhz crystal. it also enables the pll to operate during the boot process. the bootstrap program then loads program memory from the sci port and jumps to the start of the user code. external clocking must be at 2mhz or 4mhz. it uses the pll but leaves it off when complete. the data format is: ? one start bit ? eight-data bits ? no parity bit ? one stop bit ? flow control off 4.6.1.2.8 boot mode 7: reserved for future use 4.6.1.3 chip revision (chip rev)?bits 11?8 static read only value (currently 0001) indicating chip revision. this is intended to be used by applications software to facilitate support of backwards compatibility. changes to the programming interface can be tied to their associated chip revision. register descriptions (sys_base = $1fff08) 5685x digital signal controller user manual, rev. 4 4-12 freescale semiconductor 4.6.1.4 reserved?bit 7 this bit is reserved or not implemented. it is a read/write bit, initializing to one. 4.6.1.5 enhanced once enable (eonce_ebl)?bit 6 the clock for the 56800e core on-chip emulator debug features is normally enabled with the core tap interface. setting this bit continuously enables the clock. this powers the core to perform i/o with its mapped eonce registers without regard for the tap state. this is useful when doing real time debugging. ? 0 = eonce clock to core is enabled only when core tap is enabled ? 1 = eonce clock to core is always enabled 4.6.1.6 clkout disable (clkout_dbl)?bit 5 ? 0 = clkout (clko) output pin presents clk_mstr/8 (this is half the peripheral bus clock frequency) ? 1 = clkout (clko) output pin presents static zero 4.6.1.7 program ram disable (pram_dbl)?bit 4 ? 0 = internal program ram enabled ? 1 = internal program ram disabled and accesses redirected to external memory 4.6.1.8 data ram disable (dram_dbl)?bit 3 note: this field replaces the ex bit in the core omr. ? 0 = internal data ram enabled ? 1 = internal data ram disabled and accesses redirected to external memory 4.6.1.9 software reset (sw_reset)?bit 2 writing 1 to this field results in the part to reset. 4.6.1.10 stop disable (stop_dbl)?bit 1 ? 0 = the stop mode is entered when the core executes a stop instruction ? 1 = the core stop instruction will not cause entry into the stop mode 4.6.1.11 wait disable (wait_dbl)?bit 0 ? 0 = the wait mode is entered when the core executes a wait instruction ? 1 = the core wait instruction will not cause entry into the wait mode register descriptions (sys_base = $1fff08) system integration module (sim), rev. 4 freescale semiconductor 4-13 4.6.2 sim software control data 1 (scd1) figure 4-4. sim software c ontrol data 1 register (scd1) see programmer?s sheet on appendix page b-9 4.6.2.1 software control data 1 (scd1)?bits 15?0 this register is reset only by the power-on reset (por). it has no part specific functionality. it is intended for use by software developers to contain data to be unaffected by the other reset sources: ? reset pin ? software reset ?cop reset 4.6.3 sim software control data 2 (scd2) figure 4-5. sim software c ontrol data 2 register (scd2) see programmer?s sheet on appendix page b-9 4.6.3.1 software control data 2 (scd2)?bits 15?0 this register is reset only by the power-on reset (por). it has no part specific functionality. it is intended for software developers to contain data to be unaffected by the other reset sources: ? reset pin ? software reset ?cop reset base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read software control data 1 write por 0000000000000000 reset xxxxxxxxxxxxxxxx base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read software control data 2 write por 0000000000000000 reset xxxxxxxxxxxxxxxx clock generation concepts 5685x digital signal controller user manual, rev. 4 4-14 freescale semiconductor 4.7 clock generation concepts the 568500e system bus is pipelined. the data cycle occurs two system clock cycles after the address cycle with a between cycle between the two. the sim also supports two system bus masters, the core and multi-channel dma. the sim contains features to maintain the integrity of this continuous pipeline during the operation of the system. a hold-off mechanism is furnished to provide system bus slaves extra clock cycles when needed to maintain synchronization with the pipeline. a core stall mechanism is provided to keep the 56800e core?s internal pipeline from advancing when the dma is master. the peripheral bus clock has no hold-off, or stall. it runs at one-half the frequency of the system bus. the peripheral bus reads and writes are single cycle. ipbb is the only master on the peripheral bus. a wait state mechanism permits peripheral bus transactions to take extra cycles when required by slower peripherals. the ipbus bridge (ipbb) coordinates the system and peripheral buses. the ipbb presents hold-off requests to the system bus pipeline when the system bus transactions generate multiple peripheral bus transactions, or the peripheral is programmed to generate wait states. all generated clocks are true for the first-half period and false for the second-half period. any mechanism inhibiting a clock such as hold-off, or core stall, causes the clock to remain low during the entire period. the clk_mstr input can be fed by the pll output, by the oscillator running with a crystal, or by the oscillator input being clocked externally. the system bus clock frequency is always clk_mstr/2. the peripheral bus clock frequency is always clk_mstr/4. the clkout frequency is always clk_mstr/8. generated clocks system integration module (sim), rev. 4 freescale semiconductor 4-15 4.8 generated clocks a description of the system integrated module (sim) clock signals is shown in table 4-8 . table 4-8. sim clock signals clock output frequency enable condition used by clk_sys_dram clk_mstr/2 ((~hold off)? hold_dram) and (~stop mode) data ram clk_sys_ipbb clk_mstr/2 ((~hold off) ?hold_ipbb) and (~stop mode) ipbus bridge clk_sys_cpuclk clk_mstr/2 (~c7waitst) and run mode core clk_cpu_pclk clk_mstr/2 (~stop mode) and ((~rst_core )? jhawkcoretap_en ? eonce ebl note: jhawkcoretap_en is re synchronized before use core eonce clock clk_cpu_nclk clk_mstr/2 (~stop mode) and (~rst_core )? n1clken) core eonce clock clk_cpu_wclk clk_scan always enabled core scan clock clk_sys_genrl clk_mstr/2 (~hold off) and (~stop mode) sim, program ram, sbc, sad, rom clk_sys_genrl_inv clk_mstr/2 (~hold off), (~stop mode), and (tmode_bist) ram and rom bist clk_cpu_cont clk_mstr/2 always enabled sim clk_per_cont clk_mstr/4 (~stop mode) peripherals clk_per_cont_inv clk_mstr/4 (~stop mode) emi clk_clkout clk_mstr/8 (~clkout disable) output pad clkout pclk_phase ? identical to clk_per_cont, but phase shifted to rise earlier dma, ipbb hold off ? hold_dram ? hold_ipbb pad, ipbb c7waitst ? (hold off? core-stall) and rst_core core power mode controls 5685x digital signal controller user manual, rev. 4 4-16 freescale semiconductor 4.9 power mode controls the power mode control module controls movement between the three power modes supported by the core: 1. run mode provides full functionality 2. functions disabled in wait mode: ? execution of the core ? any unnecessary system clocks 3. functions disabled in stop mode: ? 56800e core ? all system clocks ? peripheral bus clock ? pll optionally ? osc optionally all system clocks continue running in the wait mode, allowing the dma to operate in the wait mode. the time-based clock generated by the oscillator and clock generation module (cgm) are not affected by low power modes. time based functions such as a time-of-day (tod) module and computer operating properly (cop) module must be individually disabled for maximum low-power effects. likewise, power mode controls do not affect pull-up/pull-down resistor enabling. power loss through input and bidirectional i/o cell pull-up/pull down resistors can be eliminated by disabling the resistor in the software where supported, or in the case of bidirectional i/o, by putting the cell in an output state and avoiding external contention. when the core executes a stop or wait instruction it will wait until any stall or hold-off activity is completed (c7waitst has deasserted) then it asserts the p5stop or p5wait sim input and the sim will enter the corresponding low power mode. the sim control register also contains stop and wait disable bits and feed the core. when asserted, these cause the core to ignore stop and wait instructions, not assert p5stop or p5wait. recovery from stop or wait mode to run mode occurs if there is a pending enabled interrupt (int_pend input asserts), or if there is a debug mode request from the core due to a jtag initiated debug mode entry request (jtdebreq input asserts), or if there is a debug mode entry request from the de input pin (de asserts). these three inputs are asynchronous so they are metastabilized and re-timed to the system clock domain before use. resets system integration module (sim), rev. 4 freescale semiconductor 4-17 the sim has special control relationships with both the oscillator (osc) module and the phase locked loop (pll) module. by default, the sim provides an extreme low power stop mode (when omr6_sd set to zero), by shutting down the pll and, if possible, the oscillator output amplifiers. alternatively (when omr6_sd set to one), the sim supports a fast stop mode recovery and does not affect the state of the pll or oscillator when the stop mode is entered. extreme low power stop mode works in this manner: upon entering the stop mode, the sim asserts its pll_shutdown output causing the pll to be disabled and bypassed. one cycle later, it asserts its osc_lopwr output. this feeds the low_pwr_mode input of the osc. when the tod clock prescaler in the osc module is used (tod_sel bit in cgm control register is zero), and osc_lopwr is asserted high, the osc module shuts off its output clock amplifiers for maximum power savings. when the cgm tod clock prescaler is used (tod_sel bit is one), osc_lopwr is ignored because the cgm depends on clocking from osc to generate the tod clock. when a fast stop mode recovery is applied (the omr6_sd bit in the core is set) neither osc_lopwr nor pll_shutdown will assert during the stop mode entry. in this case, the stop mode entry leaves the clock generation system alone. when there is a return to the run mode, the clock (pll based or direct), will be just as it was when stop was entered, avoiding any need to wait for pll lock. the sim does not automatically restart and engage the pll upon recovery from extreme low power mode. this responsibility is left to the applications software. refer to the documentation of the oscillator module for details on its low power mode input. a final note on timing: entry into either the wait or stop modes occurs at the next system clock edge after p5stop or p5wait asserts. their disabling effect on clock generation will start one clock cycle after that. the timing of entry into low power modes, especially the stop mode, is critical and is managed by a state machine in the power mode control module. this module ensures while in the stop mode entry, pll_shutdown asserts and the pll is disabled and in bypass mode before osc_lopwr asserts possibly shutting off the clock input to the pll. 4.10 resets the sim supports four sources of reset. the two asynchronous sources are the external reset pin and the power-on reset (por). the two synchronous sources are the software reset, generated within the sim itself, and the cop reset. the reset generation module has two reset detectors. a chip internal reset is detected when any of the sources assert. a por reset is detected only when the por input asserts. the detectors remain asserted until the last active reset source deasserts. the chip-internal reset detector output is the primary reset used within the sim. the only exception is the software control registers, reset by the por reset detector and the boot mode field in the simctl register, reset by the mode reset detector. resets 5685x digital signal controller user manual, rev. 4 4-18 freescale semiconductor the sim generates four reset outputs. all are active low. these all are activated by one of the two detectors but remain asserted for 32-system clock cycles after the detector deasserts. this permits the sim to generate 32-system clock cycles of continuous clocking to the part while the reset remains asserted. this is required to clear synchronous resets within the 56800e core and elsewhere in the part. the rst_core , rst_periph , and rst_cgm outputs are activated by the chip-internal reset detector and the rst_tod output is activated by the por reset detector. the rst_core output is used to reset the core. the rst_tod output is used to reset all controls used to configure time-of-day clock to retain their value once the part is powered on. see tod, cop, osc chapters. the rst_cgm is re-timed to the osc_clk and is used to reset the cgm module, in turn using the oscillator clock directly. the rst_periph reset is used to reset everything else. standards require the part to be held in reset during boundary scan operations. when the bscan_ebl input is asserted, all resets used within the sim and all reset outputs of the sim will go to their active asserted state. this prevents accidental damage due to random inputs applied during boundary scan testing. power modes discussed in section 4.9 affect reset function. cop reset is not honored if the osc module is in its low power mode since the osc module shuts off all clocking to the part and without a clock, the sim can?t see the synchronous cop reset. cop reset will be honored immediately upon return to run mode when clocks resume. there are two ways to permit a cop reset to be honored in stop mode: 1. either set omr6_sd (core register omr6 bit sd), or 2. set tod_sel in the cgm control register setting omr6_sd configures for fast stop mode recovery. setting tod_sel selects the cgm?s time-of-day clock prescaler for use rather than the one in the osc module. either, or both, prevent the osc from shutting off its clock outputs. in turn, this provides an active clk_mstr input to the sim, allowing an immediate cop reset. the software reset is only operable in run mode when the cpu can write to the sim control register to activate software reset. the low power modes and controls are explained in detail in the next chapter. external memory interface (emi), rev. 4 freescale semiconductor 5-1 chapter 5 external memory interface (emi) 5685x digital signal controller user manual, rev. 4 5-2 freescale semiconductor features external memory interface (emi), rev. 4 freescale semiconductor 5-3 5.1 introduction the external memory interface (emi) provides an interface allowing 56800e core to utilize external asynchronous memory. the emi for the 56800e core operates from the system bus. the 56800e core emi is implemented as a core bus peripheral. data can be transferred through the emi to the core directly. the emi described in this document is intended to be interfaced to 16-bit wide external memory. external arrays may be implemented either using single 16-bit wide parts or pairs of 8-bit wide memories. an external data space memory interface to the 56800e core accommodating single 8-bit wide external data memories could be implemented (at a substantial performance penalty) with appropriate programming of the csor register(s). 5.2 features the external memory interface supports the following general characteristics: ? can convert any internal bus memory request to a request for external memory ? can manage multiple internal bus requests for external memory access ? has up to four cs n configurable outputs for external device decoding ? each cs can be configured for program or data space ? each cs can be configured for read only, write only, or read/write access ? each cs can be configured for the number of wait states required for device access ? each cs can be configured for the size and location of its activation ? each cs is independently configured for setup and hold timing controls for both read and write functional description 5685x digital signal controller user manual, rev. 4 5-4 freescale semiconductor 5.3 functional description the 56800e core architecture contains three separate buses for access to memory/peripherals. the emi attaches to all of these buses and provides an interface to external memory over a single external bus. the emi serializes these internal requests to external memory in a manner avoiding conflicts and contention. 5.3.1 core interface detail managing the core access to the external memory consists of four issues: (please refer to figure 5-1 . ) 1. any of the three buses can request external access at any time. this means the emi can potentially have three requests it must be completed before the core can proceed. the emi must hold-off further execution of the core until it can serialize the requests over the external bus. this provides simultaneous data for all buses to the core for read operations. 2. there may be a mixture of read and write requests on the core buses. for instance, the program memory bus may request a read operation while the primary data bus (xab1) is requesting a write operation. 3. the primary data bus (xab1) may request an 8-bit transfer. this request must access the appropriate external byte. 4. the primary data bus (xab1) may request a 32-bit transfer. this request requires two accesses of the external bus. the emi must hold-off further core execution until all 32 bits have been transferred. this action may happen in conjunction with item one above. block diagram external memory interface (emi), rev. 4 freescale semiconductor 5-5 5.4 block diagram a simplified block diagram illustrating the connections to the emi is illustrated in figure 5-1 . the left side of the figure shows connections to the 56800e core buses and clocks. all available external emi signals are shown on the right side of the figure. in some cases, pin count restrictions may limit the number of emi signals brought out of the package. figure 5-1. emi block diagram xab1[23:0] cbw[31:0] cdbr_m[31:0] primary data access secondary data read xab2[23:0] xdb2_m[15:0] program memory access pab[20:0] cdbw[15:0] pdb_m[31:0] xab1[23:0] cdbw[31:0] cdbr_m[31:0] xab2[23:0] xdb2_m[15:0] pab[20:0] pdb_m[31:0] c7waitst holdoff clk a[23:0] d[16:0] cs [7:0] rd wr flash_security_en optional emi 56800e core clock gen. module memory map 5685x digital signal controller user manual, rev. 4 5-6 freescale semiconductor 5.5 module memory map the address of a register is the sum of a base address and an address offset. the base address is defined at the device level. registers are summarized in table 5-1 . table 5-1. emi module memo ry map (emi_base = $1ffe40) address offset register acronym register name chapter location base + $0 csbar0 chip select base address register 0 section 5.6.1 base + $1 csbar1 chip select base address register 1 base + $2 csbar2 chip select base address register 2 base + $3 csbar3 chip select base address register 3 base + $8 csor0 chip select option register 0 section 5.6.2 base + $9 csor1 chip select option register 1 base + $a csor2 chip select option register 2 base + $b csor3 chip select option register 3 base + $10 cstc0 chip select timing control register 0 section 5.6.3 base + $11 cstc1 chip select timing control register 1 base + $12 cstc2 chip select timing control register 2 base + $13 cstc3 chip select timing control register 3 base + $18 bcr bus control register section 5.6.4 register descriptions (emi_base = $1ffe40) external memory interface (emi), rev. 4 freescale semiconductor 5-7 figure 5-2. emi register map summary 5.6 register descriptions (emi_base = $1ffe40) 5.6.1 chip select base address registers 0?3 (csbar0?csbar3) the csbar registers are defined in figure 5-3 . it determines the active address range of a given cs n . the block size (blksz) field determines the size of the memory map covered by the cs n . this field also determines which of the address bits to use when specifying the base address of the cs n . this encoding is detailed in table 5-2 . when the active bits match the address and the constraints specified in the csor are also met, the cs n is asserted. the chip-select address compare logic uses only the most significant bits to match an address within a block. the value of the base address must be an integer multiple of the block size (i.e., add. offset register name 15141312111098765432 1 0 $0 csbar0 r adr 23 adr 22 adr 21 adr 20 adr 19 adr 18 adr 17 adr 16 adr 15 adr 14 adr 13 adr 12 blksz w $1 csbar1 r adr 23 adr 22 adr 21 adr 20 adr 19 adr 18 adr 17 adr 16 adr 15 adr 14 adr 13 adr 12 blksz w $2 csbar2 r adr 23 adr 22 adr 21 adr 20 adr 19 adr 18 adr 17 adr 16 adr 15 adr 14 adr 13 adr 12 blksz w $3 csbar3 r adr 23 adr 22 adr 21 adr 20 adr 19 adr 18 adr 17 adr 16 adr 15 adr 14 adr 13 adr 12 blksz w $8 csor0 r rws byte_en r/w ps/ds wws w $9 csor1 r rws byte_en r/w ps/ds wws w $a csor2 r rws byte_en r/w ps/ds wws w $b csor3 r rws byte_en r/w ps/ds wws w $10 cstc0 r wwss wwsh rwss rwsh 0 0 0 0 0 mdar w $11 cstc1 r wwss wwsh rwss rwsh 0 0 0 0 0 mdar w $12 cstc2 r wwss wwsh rwss rwsh 0 0 0 0 0 mdar w $13 cstc3 r wwss wwsh rwss rwsh 0 0 0 0 0 mdar w $18 bcr r drv bmdar 0 0 bwws brws w r 0 read as 0 w reserved register descriptions (emi_base = $1ffe40) 5685x digital signal controller user manual, rev. 4 5-8 freescale semiconductor the base address can be at block size boundaries only). for example, for a block size of 64k, the base address can be 64k, 128k, 192k, 256k, 320k, etc. note: the default reset value for cs n will enable a 32k block of external memory starting at address zero. this may be defined to be something else for a specific chip in which case the chip user manual will detail the specific reset value. figure 5-3. chip select base address registers 0?3 (csbar0?csbar3) see programmer?s sheet on appendix page b-9 5.6.2 chip select option registers 0?3 (csor0?csor3) a chip select option register is required for every chip select. this register specifies the mode of operation of the chip select and the timing requirements of the external memory. note: the cs n logic can be used to define external memory wait states even if the cs n pin is used as gpio. note: the cs n output can be disabled by setting either the ps/ds, r/w or byte_en fields to zero. base + $0 - $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read adr23 adr22 adr21 adr20 adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 blksz write reset 0000000000000011 table 5-2. csbar encoding of the blksz field blksz block size address lines compared 0000 4k x: adr[23:12], p: adr[20:12] 0001 8k x: adr[23:13], p: adr[20:13] 0010 16k x: adr[23:14], p: adr[20:14] 0011 32k x: adr[23:15], p: adr[20:15] 0100 64k x: adr[23:16], p: adr [20:16] 0101 128k x: adr[23:17], p: adr[20:17] 0110 256k x: adr[23:18], p: adr[20:18] 0111 512k x: adr[23:19], p: adr [20:19] 1000 1m x: adr[23:20], p: adr[20:20] 1001 2m x: adr[23:21]. all program address space decoded. 1010 4m x: adr[23:22]. no program address space decoded. 1011 8m x: adr[23:23]. no program address space decoded. 1100 16m all data address space decoded. no program address space decoded. 1101 reserved no data address space decoded. no program address space decoded. 1110 reserved no data address space decoded. no program address space decoded. 1111 reserved no data address space decoded. no program address space decoded. register descriptions (emi_base = $1ffe40) external memory interface (emi), rev. 4 freescale semiconductor 5-9 figure 5-4. chip select option registers 0?3 (csor0?csor3) see programmer?s sheets on appendix page c- 10 5.6.2.1 read wait states (rws)?bits 15?11 the rws field specifies the number of additional system clocks, 0-30 (31 is invalid) to delay for read access to the selected memory. the value of rws should be set as indicated in section 5.7.1 . 5.6.2.2 upper/lower byte option (byte_en)?bits 10?9 this field specifies whether the memory is 16 bits wide or one byte wide. if the memory is byte wide, the option of upper or lower byte of a 16-bit word is selectable. table 5-3 provides the encoding of this field. 5.6.2.3 read/write enable (r/w)?bits 8?7 this field determines the read/write capabilities of the associated memory as shown in table 5-4 . 5.6.2.4 program/data space select (ps/ds)?bits 6?5 the mapping of a chip select to program and/or data space is shown in table 5-5 . base + $8 - $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rws byte_en r/w ps/ds wws write reset 1011100000010111 table 5-3. csor encoding byte_en values value meaning 00 disable 01 lower byte enable 10 upper byte enable 11 both bytes enable table 5-4. csor encodi ng of read/write values value meaning 00 disable 01 write-only 10 read-only 11 read / write register descriptions (emi_base = $1ffe40) 5685x digital signal controller user manual, rev. 4 5-10 freescale semiconductor 5.6.2.5 write wait states (wws)?bits 4?0 the wws field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for write access to the selected memory. the value of wws should be set as indicated in section 5.7.2 . 5.6.3 chip select timing control registers 0?3 (cstc0?cstc3) a chip select timing control (cstc) register is required for every chip select. this register specifies the detailed timing required for accessing devices in the selected memory map. at reset, these registers are configured for minimal timing in the external access waveforms. therefore, these registers need only be adjusted if required by slower memory/peripheral devices. figure 5-5. chip select timing control registers 0?3 (cstc0?cstc3) see programmer?s sheet on appendix page b-12 5.6.3.1 write wait states setup delay (wwss)?bits 15?14 this field affects the write cycle timing diagram, illustrated in figure 5-16 . additional time (clock cycles) is provided between the assertion of cs n and address lines and the assertion of wr . the value of wwss should be set as indicated in section 5.7.2 . 5.6.3.2 write wait states hold delay (wwsh)?bits 13?12 this field affects the write cycle timing diagram, illustrated in figure 5-17 . the wwsh field specifies the number of additional system clocks to hold the address, data, and cs n signals after the wr signal is deasserted. the value of wwsh should be set as indicated in section 5.7.2 . table 5-5. csor encoding of ps/ds values value meaning flash_security_enable = 0 flash_security_enable = 1 00 disable disable 01 ds only ds only 10 ps only disable 11 both ps and ds ds only base + $10 - $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read wwss wwsh rwss rwsh 0 0 0 0 0 mdar write reset 0000000000000011 register descriptions (emi_base = $1ffe40) external memory interface (emi), rev. 4 freescale semiconductor 5-11 5.6.3.3 read wait states setup delay (rwss)?bits 11?10 this field affects the read cycle timing diagram, illustrated in figure 5-10 . additional time (clock cycles) is provided between the assertion of cs n and address lines and the assertion of rd . the value of rwss should be set as indicated in read timing. 5.6.3.4 read wait states hold delay (rwsh)?bits 9?8 this field affects the read cycle timing diagram, illustrated in figure 5-11 . the rwsh field specifies the number of additional system clocks to hold the address, data, and cs n signals after the rd signal is deasserted. the value of rwsh should be set as indicated in section 5.7.1 . note: if both, the rwss and rwsh fields are set to zero the emi read timing is set for consecutive mode. in this mode the rd signal will remain active during back-to-back reads from the same cs n controlled memory space. 5.6.3.5 reserved?bits 7?3 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.3.6 minimal delay after read (mdar)?bits 2?0 this field specifies the number of system clocks to delay between reading from memory in a cs n controlled space and reading from another device. since a write to the device implies activating the digital signal controller on the bus, this is also considered a read from another device. figure 5-6 illustrates the timing issue requiring the introduction of the mdar field. in this diagram, cs1 is assumed to operate a slow flash memory in p-space while cs2 is operating a faster ram in x-space. in some bus contention cases, it is possible to encounter data integrity problems where the contention is occurring at the time the data bus is sampled. register descriptions (emi_base = $1ffe40) 5685x digital signal controller user manual, rev. 4 5-12 freescale semiconductor figure 5-6. data bus contention ti ming requiring mdar field assertion 5.6.4 bus control register (bcr) the bcr register defines the default read timing for external memory accesses to addresses not covered by the cs /csor/cstc registers. the timing specified by the bcr register applies to both program and data space accesses because the ps and ds control signals are not directly available on the chip pinouts. note: any of the cs n signals can be configured to mirror the ps and/or ds function, but then the associated cs n configuration registers control the timing. figure 5-7. bus control register (bcr) see programmer?s sheets on appendix page c- 12 5.6.4.1 drive (drv)?bit 15 the drive (drv) control bit is used to specify what occurs on the external memory port pins when no external access is performed (whether the pins remain driven or are placed in tri-state). table 5-6 summarizes the action of the emi when the drv bit is cleared or is set. drv bit is cleared on hardware reset, but should be set in most customer applications. base + $18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read drv bmdar 0 0 bwws brws write reset 0000001011110111 thzoe tace tcs_ram tcs_ram tohz tce tcs _ flash t cs_flash flash read bus contention int_semi_clk flash cs1 flash_data ram cs2 ram_data bus contention with two devices driving data at the same time. ram read register descriptions (emi_base = $1ffe40) external memory interface (emi), rev. 4 freescale semiconductor 5-13 5.6.4.2 base minimal delay after read (bmdar)?bits 14?12 this bit field specifies the number of system clocks to delay after reading from memory not in cs controlled space. since a write to the device implies activating the digital signal controller on the bus, this is also considered a read from another device, therefore activating the bmdar timing control. please see the description of the mdar field of the cstc registers for a discussion of the function of this control. 5.6.4.3 reserved?bits 11?10 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.4.4 base write wait states (bwws)?bits 9?5 this bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for write access to the selected memory when the memory address does not fall within cs controlled range. the value of bwws should be set as indicated in timing specifications. 5.6.4.5 base read wait states (brws)?bits 4?0 this bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for read access to the selected memory when the memory address does not fall within cs controlled range. the value of brws should be set as indicated in section 5.7 . table 5-6. operation with drv 800e core operating state drv pins a23:a0 rd , wr , cs n d15:d0 emi is between external memory accesses 0 tri-stated tri-stated tri-stated reset mode tri-stated pulled high internally tri-stated emi is between external memory accesses 1 driven driven (rd , wr , cs n are deasserted) tri-stated reset mode tri-stated pulled high internally tri-stated timing specifications 5685x digital signal controller user manual, rev. 4 5-14 freescale semiconductor 5.7 timing specifications 5.7.1 read timing 5.7.1.1 consecutive mode operation figure 5-8 illustrates the read timing for external memory access . for comparison, a single read cycle is illustrated followed by a null cycle and then a back-to-back read. figure 5-8 assumes zero wait states are required for the access. figure 5-9 illustrates a timing diagram with one wait state added. there are two read setup timing parameters for each read cycle. the core will latch the data on the rising edge of the internal clock while t rsd indicates the core setup time. the external timing of the address and controls is adjusted so they may be changing at this time. therefore, a data latch is introduced to capture the data (at the pin) a quarter clock earlier, on the rising edge of the internal delayed clock. the setup time required for this latch is illustrated by t rsdp in the diagrams. for slow clock speeds, t rsdp is more critical, while t rsd may be harder to meet for faster clock rates. note: during back-to-back reads, rd remains low to provide the fastest read cycle time. figure 5-8. external read cycle with clock and rws = 0 t access t ohz t access t oev t rh t rl t csv t av t av t csrh t clka t rc read (rws = 0) read (rws = 0) idle t c t rsd t rsd t rhd t rsd data in data in data in int_sys_clk int_sys_clk_delay a[23:0] cs [7:0] rd , oe wr d[15:0] read (rws = 0) t rsdp t rsdp t rsdp timing specifications external memory interface (emi), rev. 4 freescale semiconductor 5-15 note: int_sys_clk is the internal system clock from which everything is referenced. figure 5-9. external read cycle with rws = 1, rwsh = 0 and rwss = 0 5.7.1.2 read setup and hold timing although most memory devices can perform consecutive reads by holding the csn and rd (oe ) signals in the active state and changing the address, there are peripheral devices that require rd (oe ) to transition to the inactive state between reads of certain registers. this timing can be accommodated with the read setup (rwss) and/or read hold (rwsh) control fields illustrated in figure 5-10 and figure 5-11 . time added to figure 5-8 by setting rws = 1 t access t ohz t access t oev t rh t rl t csv t av t av t rdh t csrh t clka t rc read (rws = 1) read (rws = 1) idle t c t rsd t rsdp t rsd t rsdp t rhd t rsd t rsdp data in data in data in int_sys_clk int_sys_clk_delay a[23:0], ps , ds cs [7:0] rd , oe wr d[15:0] read (rws = 1) timing specifications 5685x digital signal controller user manual, rev. 4 5-16 freescale semiconductor figure 5-10. external read cycle with rwss = rws = 1, and rwsh = 0 time added to by setting rwss = 1 t access t oev t ohz t access t oev t rh t rl t csv t av t av t csrh t rc read (rwss = rws = 1) read (rwss = rws = 1) idle read (rwss = rws = 1) t rsd t rsdp t rsd t rsdp t rsd t rsdp data in data in data in int_sys_clk int_sys_clk_delay a[23:0], ps , ds cs [7:0] rd , oe wr d[15:0] timing specifications external memory interface (emi), rev. 4 freescale semiconductor 5-17 figure 5-11. external read cycle rws = rwsh = 1 and rwss = 0 5.7.2 write timing figure 5-12 shows the write timing for external memory access . for comparison, a single write cycle is shown followed by a null cycle and then a back-to-back write.this figure assumes zero wait states are required for the access. t access t oev t ohz t access t oev t rh t rl t csv t av t av t csrh read (rws = rwsh = 1) read (rws = rwsh = 1) idle read (rws = rwsh = 1) t rsd t rsdp t rsd t rsdp t rsd t rsdp data in data in data in int_sys_clk int_sys_clk_delay a[23:0], ps , ds cs [7:0] rd , oe wr d[15:0] t rc time added to figure 5-10 by setting rwsh = 1 timing specifications 5685x digital signal controller user manual, rev. 4 5-18 freescale semiconductor figure 5-12. external write cycle note: when wws = 0 the timing of the wr strobe is generated from different clock edges than when it is set to some other value. this change in timing allows the possibility of single cycle write operation, but reduces the pulse width of wr to one quarter clock. this may make it difficult to meet write timing requirements for most devices when operating at normal clock rates. t cwh t cwh t csv t whz t av t av t wac idle write (wws = 0) write (wws = 0) idle t c t wrh t avw t dh t dw t wrl t dh t dw int_sys_clk(core) int_delay_semi_clk a[23:0] rd = oe d[16:0] cs2 wr t wc t wde t wdo t cwl t avw t whz t wdo t wde t cwl t avw t csl t csv write (wws = 0) timing specifications external memory interface (emi), rev. 4 freescale semiconductor 5-19 figure 5-13. external write cycle with wws = 1, wwsh = 0, and wwss = 0 5.7.2.1 write setup and hold timing since the timing of the strobes is different when wws = 0 than it is when wws > 0, two sets of timing diagrams are illustrated in figure 5-14 , figure 5-15 , figure 5-16 , and figure 5-17 . 5.7.2.2 wws = 0 although most memory devices require a zero setup and hold time, there are some peripheral devices where a setup/hold time is required. the wwss and wwsh field of the cstc register provides the ability to allow for a write setup and/or hold time requirement as shown in figure 5-14 and figure 5-15 . t cwh t cwl t cwl t csv t wdo t whz t av t wac t wc idle write (wws = 1) write (wws = 1) idle write (wws = 1) t c t wrl t avw t dw t avw t dh t dw t wrl t avw int_sys_clk(core) int_delay_semi_clk a[23:0] rd = oe d[16:0] cs2 wr t av t wde t csv t cwh t csl t dh t cwh t wrh t whz time added to figure 5-12 by setting wws = 1 t wdo timing specifications 5685x digital signal controller user manual, rev. 4 5-20 freescale semiconductor figure 5-14. external write cycle with wwss = 1, wws = 0 and wwsh = 0 t cwh (4.3) t cwl (4.3) t cwh (4.3) t cwl (4.3) t csv (4.3) t csv (4.3) t whz (3) t wdo (6.5+6.3) t whz (3) t wde t wdo (6.5+6.3) t av (4.3) t av (4.3) t wac tt csl tt wc idle write (wwss=1,wws=0) write (wwss=1,wws=0) idle tt c write (wwss=1,wws=0) t t avw (0) t wrh (7) t dh (0) t dw (3) t avw (0) t t dh (0) t dw (3) t wrl (7) t avw (0) 35.7 mhz int_sys_clk(core) int_delay_semi_clk a[23:0] rd = oe d[16:0] cs2 wr time added to figure 5-12 by setting wwss = 1 timing specifications external memory interface (emi), rev. 4 freescale semiconductor 5-21 figure 5-15. external write cycle with wws = 0, wwsh = 1, wwss = 0 5.7.2.3 wws > 0 although most memory devices require a zero setup and hold time, there are some peripheral devices where a setup/hold time is required. the wwss and wwsh field of the cstc register provides the ability to allow for a write setup and/or hold time requirement as shown in figure 5-16 and figure 5-17 respectively. t cwh t cwl t cwh t cwl t csv t csv t whz t wdo t wde t whz t wde t wdo t av t av t wac t csl t wc idle write (wws=0, write (wws=0,wwsh=1) idle t c write (wws=0,wwsh=1) t avw t wrh t dh t dw t avw t wrl t dh t dw t avw int_sys_clk(core) int_delay_semi_clk a[23:0] rd = oe d[16:0] cs2 wr wwsh=1) time added to figure 5-12 by setting wwss = 1 timing specifications 5685x digital signal controller user manual, rev. 4 5-22 freescale semiconductor figure 5-16. external write cycle with wwss = wws = 1 and wwsh = 0 time added to figure 5-13 by setting wwss = 1 t cwl t cwh t csv t csv t wdo t whz t wde t wdo t av t av t wac idle write(wwss = wws = 1) write (wwss = wws = 1) idle write (wwss = wws = 1) t wrl t wrh t avw t dh t avw t wrl t dh t avw int_sys_clk(core) int_delay_semi_clk a[23:0] rd = oe d[16:0] cs2 wr t csl t dw t cwl t dw t dw t dh t whz resets external memory interface (emi), rev. 4 freescale semiconductor 5-23 figure 5-17. external write cycle with wws = wwsh = 1 (wwss = 0) 5.1 clocks the emi operates from clocks internal to the chip and does not require/provide clocks external to the chip. 5.1 interrupts there are no interrupts generated by this module. 5.1 resets all reset types are equivalent for the emi and therefore have the same effect. the emi outputs during reset are controlled by the drv bit of the bcr. during reset this bit is set to zero. therefore, table 5-6 defines the reset state of all emi pins. t cwl t cwh t cwl t csv t wdo t whz t wde t wdo t av t wac idleidle write (wws = wwsh = 1) idle t wrl t dh t dw t wrh t avw t dw t avw t wrl t dh t dw t avw int_sys_clk (core) int_delay_semi_clk a[23:0] rd = oe d[16:0] cs2 wr time added to figure 5-13 by setting wwsh = 1 t whz t dh write(wws = wwsh = 1) write (wws = wwsh = 1) t av t csl t csv resets 5685x digital signal controller user manual, rev. 4 5-24 freescale semiconductor on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-1 chapter 6 on-chip clock synthesis (occs) 5685x digital signal controller user manual, rev. 4 6-2 freescale semiconductor introduction on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-3 6.1 introduction the on-chip clock synthesis (occs) module allows product design using an inexpensive 4mhz crystal or an external clock source to run the dsp56853/54/55/57/58 at any frequency from 0 to 120mhz. the occs module is comprised of two major blocks: the oscillator (osc), and the pll/cgm (analog - phase locked loop/digital - clock generation module (cgm)). the osc output clocks feed the pll/cgm block. the pll/cgm generates a time clock for computer operating properly (cop) timer use. the pll/cgm also generates a master clock consumed by the system integration module (sim). the sim generates derivative clocks for consumption by the core logic and ipbus peripherals. the sim divides the mstr_clk (typically 240mhz) by 2 to create the 56800e core clock (typically 120mhz) and by 4 to create the ipbus_clk (typically 60 mhz). all peripherals on the dsp56853/54/55/57/58 run off the ipbus clock frequency. the cop and tod peripherals also consumes the much lower frequency time_clk (typically 31.25 khz). the pll may be used to generate a high frequency clock from the low-frequency crystal-referenced (or external clock driven) osc circuit. the pll provides an exact integer multiple of the oscillator?s output reference frequency (fref). the frequency multiplication is in the range of 20 to 120. the cgm controls the pll?s output frequency. the cgm also selects between the pll (pll_out) and osc (fref) as potential master clock sources and routes the selection to the sim. the cgm also contains circuitry to detect if the pll is unlocked and generates an interrupt signal for the condition. figure 6-1. occs integration overview out of reset, the cgmcr[sel] control bit is 0, selecting the fref path as the source of mstr_clk. the core will proceed to execute code using a clock divided down from the 0 1 osc oscillator extal xtal o s c _ l o p w r * pll / cgm phase locked loop clock generation module cgmcr[sel] (4 mhz) (240 mhz) bold represents default states or typical conditions. * see stop mode features for further details p l l _ s h u t d o w n * time of day cop other peripherals ipbb ip bus bridge sim system integration module divide by 4 56800e core mstr_clk (120 mhz) (60 mhz) time_clk (31.25 khz) ipbus_clk (60 m hz) clkout (30 mhz) loss_of_lock_interrupt occs on-chip clock synthesis pll_out 4 mhz ftime (31.25 khz) fref (4 mhz) osc (oscillator) circuit detail 5685x digital signal controller user manual, rev. 4 6-4 freescale semiconductor oscillator?s fref output. the core will run at fref/2 and the ipbus_clk will run at fref/4. among the first things applications typically do is turn on the pll, wait for lock indication and set cgmcr[sel] to 1, enabling high speed operation. 6.1.1 occs features ? osc connects to external crystals in the range of 2 to 4mhz ? osc can optionally accept an external active clock (0 to 240mhz) ? pll generates any integer multiple frequency, allowing dc to 120mhz execution ? cgm provides glitch-free transition between osc and pll clock sources ? cgm provides digital loss of lock detection ? ultra low power modes are available while cop timer and tod are kept alive 6.2 osc (oscillator) circuit detail figure 6-2. osc supplying clocks to pll/cgm a typical connection for the osc module is shown above. the weak differential signal coming in directly from extal/xtal pin pair is routed to a very low power differential amplifier. because the amplifier is so low in power, it has a usable bandwidth limit somewhat above just 4mhz. the resulting clock frequency is divided down by a fixed value of 128 to yield a 31.25khz clock. out of reset, the register cgmcr[tod_sel] is 0, so this is the path selected through the mux to create the time_clk used by the cop and tod. if the signal present on xtal is above 4mhz (e.g. driven by an external active clock) then it is necessary to set cgmcr[tod_sel] to 1. the signal from xtal is buffered up (becoming fref) and is consumed everywhere else. rbias 1 0 extal cgmcr[tod_sel] ?0? is default path note (1) bold represents default states and typical conditions. 1) see stop mode features for further details 2) when osc_lopwr is asserted, this grayed portion of the occs is disabled. osc_lopwr assertion is prevented whenever cgmcr[tod_sel] = 1. this automatic interlock prevents time_clk from being killed accidentally. fref (4 mhz) time_clk (31.25 khz ) xtal cgmtod[tod] . . 128 . . 2 . . (1) osc_lopwr notes (1) & (2) bandwidth limited to 4 mhz time_clk feeds the tod and cop watchdog timer. 4 mhz rs cl1 cl2 oscillator pll / cgm ftime (31.25 khz) osc (oscillator) circuit detail on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-5 6.2.1 using an external crystal figure 6-3 illustrates the typical application details for using an external crystal. a 4mhz, at cut, parallel resonant crystal is mounted across xtal and extal pins. a 1 mohm bias resistor is paralleled to that connection. the default path for time_clk generation (the differential amplifier path) is recommended and therefore cgmcr[tod] register setting is a don?t care. please see section 6.2.4 for further details. figure 6-3. using an external crystal the values of rs, cl1 and cl2 are determined with assistance of your crystal manufacturer. in general, cl1 and cl2 are used to pull the crystal to the intended frequency and establish the equivalent series resistance (esr). rs eliminates some of the inverter?s gain (by an amount appropriate for the resulting esr). note: the cgmcr register?s tod_sel field may be set to either 0 or 1. the recommended setting of 0 allows very low power operation when executing a stop instruction. 1 mohm 1 0 extal cgmcr[tod_sel] = 0 note (1) bold represents default states and typical conditions. 1) see stop mode features for further details 2) at cut quartz crystal or ceramic resonator. crystal vendor to supply values for rs, cl1 and cl2 fref (4 mhz) time_clk (31.25 khz ) xtal 128 . . 2 . . (1) osc_lopwr notes (1) bandwidth limited to 4 mhz 4 mhz note (2) rs cl1 cl2 ftime (31.25 khz) . . cgmcr[tod] = (don?t care) osc (oscillator) circuit detail 5685x digital signal controller user manual, rev. 4 6-6 freescale semiconductor 6.2.2 using an external active clock source below 4 mhz when using an external active clock source of a frequency less than, or equal to, 4mhz then the connections shown below are recommended. here, the extal pin is biased to 1.65v and xtal is driven with a 0 to 3.3v square wave clock signal. the time_clk source path is the same as above, using the fixed divide by 128 block and channel 0 of the mux. figure 6-4. using an external active low frequency clock, < 4 mhz note: the cgmcr register?s tod_sel field may be set to either 0 or 1. the recommended setting of 0 allows very low power operation when executing a stop instruction. if, however, a setting of 1 is used, then extal can be tied to ground, to mid-rail (as shown), or high. if tod_sel is set to 1, then the optimal connection of extal is to ground. 1 0 extal cgmcr[tod_sel] = 0 note (1) bold represents default states and typical conditions. 1) see stop mode features for further details fref (4 mhz) time_clk (31.25 khz ) xtal 128 . . 2 . . (1) osc_lopwr notes (1) bandwidth limited to 4 mhz ftime (31.25 khz) low frequency digital clock (4 mhz) . . cgmcr[tod] = (don?t care) osc (oscillator) circuit detail on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-7 6.2.3 using an external active clock source above 4 mhz when using an external active clock source of a higher frequency than 4mhz (up to 240mhz is allowable) the settings detailed below should be used. figure 6-5. using an external active high frequency clock, > 4 mhz since the differential amplifier is band limited to just over 4mhz, in this example the default time_clk path?s divide by 128 counter will no longer have an adequate signal for proper operation. instead, the user programmable divide by circuit should be used. this requires correct setting of both the cgmcr[tod] and [tod_sel] register fields as shown in the figure. in this particular example, the externally applied clock, and hence fref, are running at 30 mhz. this requires tod_sel be set to 1 and the tod register set to 480. the input frequency of 30mhz divided down by 480 and then again by a fixed value of 2 yields the desired 31.25khz time_clk frequency. note: with the cgmcr register?s tod_sel field set to 1, extal can be tied to ground (as shown), to mid-rail, or high. the optimal connection of extal is to ground. 6.2.4 stop mode features in an attempt to conserve power, applications may power the device down by executing stop or wait instructions. the dsp5685x occs module supports three variants of stop mode processing. 1. case where cgmcr[tod_sel] = 0 a stop instruction will result in the mstr_clk clock source being forced back to fref and the pll being powered down (pll_shutdown asserts. if cgmcr[tod_sel] is 0, then osc_lowpwr will assert, bringing the osc module into its lowest power alive state. only the inverter, differential amplifier and the fixed divide-by 128 block remain 10 extal cgmcr[tod_sel] = 1 note (1) fref (30 mhz) time_clk (31.25 khz ) xtal 128 . . 2 . . (1) osc_lopwr notes (1) ftime (invalid signal) bold represents default states and typical conditions. 1) see stop mode features for further details . . cgmcr[tod] = 480 high frequency digital clock (30 mhz) the amplifier?s bandwidth is limited to 4 mhz, so its output is invalid in a high frequency input scenario. cgmcr[tod] must be set to 1 and the cgmcr[tod] divider must be set to a reasonable value in order to enable a valid time_clk signal. pll (phase locked loop) circuit detail 5685x digital signal controller user manual, rev. 4 6-8 freescale semiconductor enabled, but that is enough to keep time_clk and the associated cop counter alive and running. fref is held quiescent. when waking up from this deep stop , the pll will need to be re-started, lock status re-queried and the pll output re-selected to source mstr_clk. 2. case where cgmcr[tod_sel] =1 a stop instruction will result in the mstr_clk clock source being forced back to fref and the pll being powered down (pll_shutdown asserts). if cgmcr[tod_sel] is 1 when the stop instruction is executed, then the sim will not assert osc_lowpwr for in doing so, the time_clk (and cop) would be killed. this is usually an undesirable situation from an applications perspective. 3. fast stop recovery a fast stop recovery is available in which neither the osc_lowpwr or pll_shutdown signal are asserted. as such, no time is required to re-start the pll, but it comes at the cost of increased power consumption by the pll during stop. fast stop recovery is available by setting the omr register?s bit 6 to 1. for further details on stop and fast stop recovery, please see section 4.9 , power mode controls. 6.3 pll (phase locked loop) circuit detail figure 6-6. pll block diagram phase/freq fref detector down up vco_out vco pll_out postscaler down counter (n = 19 to 119) charge loop pump filter lock detector (part of cgm) loss of lock interrupt pll (phase locked loop) circuit detail on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-9 6.3.1 phase frequency detector the phase frequency detector (pfd) compares the clock signal from the feedback divider to the input clock. when the input clock comes before the feedback clock the pfd generates a down pulse signal. the down pulse signal continues until the feedback clock signal arrives. if the feedback clock arrives at the pfd before the input clock, the pfd generates an up pulse, continuing until the input clock signal arrives. 6.3.2 charge pump the charge pump draws charge into or out of the loop filter depending upon the signals from the phase frequency detector. as charge is added to the loop filter the vco control voltage increases. as charge is pulled out of the loop filter, the vco control voltage decreases. 6.3.3 loop filter the loop filter produces a voltage proportional to the amount of charge pumped into or out of the loop filter by the charge pump. the loop filter is a single pole rc filter. 6.3.4 voltage controlled oscillator the voltage controlled oscillator (vco) produces a frequency inversely proportional to the value of the control voltage signal coming out of the loop filter. the vco gain is approximately 109mhz/volt. the vco has a frequency range of 80mhz to 380mhz with a center frequency of 240mhz. 6.3.5 down counter the down counter is a programmable divide by n counter where the divide integer n is user-set to develop the pll output frequency of interest. by presenting only one return pulse out of n input pulses to the return clock of the phase frequency detector, the pfd will drive the charge pump to raise the vco frequency until the down counter return signal is in frequency and phase lock with the input clock signal. the output of the vco will, therefore, be n times the frequency of the input clock signal. the value of n has a valid range of 19 to 119. the selected value of n depends upon the desired vco output frequency and the input clock frequency (fref). for the 2mhz input crystal the valid range of n will range from 39 to 119, producing a vco frequency output of 80mhz to 240mhz according to the formula: fvco_out = fref (n+1) the vco?s output frequency is routed through a postscaler so the final pll output frequency is given by: fpll_out = fvco_out / 2 m pll (phase locked loop) circuit detail 5685x digital signal controller user manual, rev. 4 6-10 freescale semiconductor where m is the value on the postscaler and can range from 0 to 7. example: let fref = 32mhz, n = 4, and m = 3, using the formulas gives: fpll_out = (32mhz (4+1)) / 8 fpll_out = 20mhz. for the 4mhz input crystal the valid range of n will be from 19 to 59, producing the same vco output range, 80mhz to 240mhz. 6.3.6 pll lock time user notes the pll?s voltage controlled oscillator (vco) has a characterized operating range extending from 80mhz to 240mhz. the pll is programmable via a divide by n+1 register, able to take on values varying between 1 and 128. for higher values of n , pll lock time becomes an issue. it is recommended to avoid values of n resulting in the vco frequency being greater than 240mhz. the graphic in figure 6-7 depicts the range of recommended output frequencies of vco_out, plotting n versus the input frequency (fref). the lower the value of n , the quicker the pll will be able to lock. pll (phase locked loop) circuit detail on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-11 figure 6-7. pll output frequency vs. input frequency the lock time of the pll is, in many applications, the most critical pll design parameter. proper use of the pll ensures the highest stability and lowest lock time. 6.3.6.1 pll lock time determination typical control systems refer to the lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition regardless of the size of the step input. when the pll is coming from a powered down state (pdn is high) to a powered up condition (pdn is low) the maximum lock time is 10msec. other systems refer to lock time as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the lock time varies according to the original error in the output. minor errors may be shorter or longer in many cases. 1 10 100 1000 0 5 10 15 20 25 30 35 40 fref [mhz] cgmdb[plldb] or "n" fvco_out = 80 fvco_out = 240 the recommended vco output range is bounded by a high frequency of 240 mhz and a low frequency of 80 mhz. the lower the value of cgmdb[plldb] ("n"), the faster the lock time for the pll. cgm functional detail 5685x digital signal controller user manual, rev. 4 6-12 freescale semiconductor 6.3.6.2 pll parametric influences on reaction time lock time is designed to be as short as possible while still providing the highest possible stability. many factors directly and indirectly affect the lock time. the most critical parameter affecting the reaction time of the pll, is the reference frequency (fref). this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference frequency (fref), the longer it takes to make these corrections. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. 6.4 cgm functional detail the cgm controls the pll, detects pll lock, and is used to generate the master clock to the sim. the cpu clock is one half the frequency of the master clock while the ipbus clock is one fourth the frequency. the sim handles these clock divisions. the master clock source can be either the oscillator output or the analog pll output. the oscillator output (fref) will typically be 4mhz, but a faster active clock can be driven into the xtal pin at speeds of up to 240mhz. the pll output can be up to 240mhz. in order to use the pll, the proper divide by factor and post scaler values should be programmed into the cgmdb register. next, the pll is turned on by setting the power-down (pdn) bit in the cgmcr to zero. the user should then wait for the pll to achieve lock before changing the sel bit to select the pll output as the master clock. 6.4.1 pll frequency lock detector this cgm function monitors the vco output clock and sets the lck1 and lck0 bits in the cgm control register based on the frequency accuracy. the lock detector is enabled with the lckon bit of the cgmcr as well as the pdn bit. once enabled, the detector starts two counters whose outputs are periodically compared. the input clocks to these counters are the vco output clock divided by the divide-by factor, feedback, and the crystal reference clock, fref. the period of the pulses being compared cover one whole period of each clock because the feedback clock doesn?t guarantee a 50 percent duty cycle. counts are compared after 16, 32, and 64 cycles. if the counts match after 32 cycles, the lck0 bit is set to 1. if the counts match after 64 cycles, the lck1 bit is also set. the lck bits stay set until the counts fail to match or if a new value is written to the plldb field or on reset caused by lckon, pdn, or chip level reset. when the circuit sets lck1, the two counters are reset and register descriptions (cgm_base = $1fff10) on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-13 start the count again. the lock detector is designed so if lck1 is reset to 0 because the counts did not match when checked after 64 cycles, the lck0 bit can remain high if the counts matched after 32 cycles. this provides the processor the accuracy of the two clocks with respect to each other. 6.5 module memory map there are three registers on the cgm peripheral described in table 6-1 . 6.6 register descriptions (cgm_base = $1fff10) 6.6.1 clock generation module (cgm) control register figure 6-9. cgm control register (cgmcr) see programmer?s sheet on appendix page b-14 6.6.1.1 reserved?bits 15?14 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. table 6-1. cgm memory map $1fff10 address offset register acronym register name access type chapter location base + $0 cgmcr control register read/write section 6.6.1 base + $1 cgmdb divide-by register read/write section 6.6.2 base + $2 cgmtod time-of-day register read/write section 6.6.3 add. offset register name 151413121110987654321 0 $0 cgmcr r 0 0 lck1 lck0 sel 0 0 0 0 lck1_ie lck0_ie lck on tod_ sel pdn w $1 cgmdb r post 0 0 0 0 0 0 plldb w $2 cgmtod r 0 0 0 0 tod w r 0 read as 0 w reserved figure 6-8. occs register map summary base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 lck1 lck0 sel 0 0 0 0 lck1_ie lck0_ie lckon tod_sel pdn write reset 00 0 0 0 0000 0 0 0 0 0 0 1 register descriptions (cgm_base = $1fff10) 5685x digital signal controller user manual, rev. 4 6-14 freescale semiconductor 6.6.1.2 lock 1 status (lck1)?bit 13 this bit shows the status of the lock detector state for the lck1 circuit. changes in the state of this bit can be used to cause interrupts in conjunction with the lck1 interrupt enable bits. the lck1 interrupt is cleared by writing 1 to this bit. ? 0 = pll not locked ? 1 = pll locked 6.6.1.3 lock 0 status (lck0)?bit 12 this bit shows the status of the lock detector state for the lck0 circuit. changes in the state of this bit can be used to cause interrupts in conjunction with the lck0 interrupt enable bits. the lck0 interrupt is cleared by writing 1 to this bit. ? 0 = pll not locked ? 1 = pll locked 6.6.1.4 clock source select (sel)?bit 11 this bit is used to control the source of the master clock to the sim. ? 0 = oscillator output selected by default ? 1 = pll output selected 6.6.1.5 reserved?bits 10?7 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. 6.6.1.6 lock 1 interrupt enable (lck1_ie)?bits 6?5 an optional interrupt can be generated if the pll lock status bit (lck1) changes. ? 00 = disable interrupt by default ? 01 = enable interrupt on rising edge of lck1 ? 10 = enable interrupt on falling edge of lck1 ? 11 = enable interrupt on any edge of lck1 6.6.1.7 lock 0 interrupt enable (lck0_ie)?bits 4?3 an optional interrupt can be generated if the pll lock (lck0) status bit changes. ? 00 = disable interrupt by default register descriptions (cgm_base = $1fff10) on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-15 ? 01 = enable interrupt on rising edge of lck0 ? 10 = enable interrupt on falling edge of lck0 ? 11 = enable interrupt on any edge of lck0 6.6.1.8 lock detector on (lckon)?bit 2 ? 0 = lock detector disabled by default ? 1= lock detector enabled 6.6.1.9 time-of-day clock source select (tod_sel)?bit 1 this bit is used to select between two possible time_clk sources. the oscillator can generate the time_clk only when the input clock on either the extal or xtal pins in 4mhz or less. when driving high speed clocks into xtal, the cgm must generate the time_clk using the cgmtod register. this bit is only reset by power-on reset (por) conditions. ? 0 = time_clk is generated by oscillator as default ? 1 = time_clk is generated by cgm 6.6.1.10 pll power-down (pdn)?bit 0 the pll can be turned off by setting the pdn bit to one. there is a four ipbus clock delay from changing the bit to signaling the pll. when the pll is powered down, the clock select logic automatically switches to the oscillator output in order to prevent loss of clock to the core. ? 0 = pll turned on ? 1 = pll powered down by default 6.6.2 clock generation module (cgm) divide-by register figure 6-10. cgm divi de-by register (cgmdb) see programmer?s sheet on appendix page b-16 6.6.2.1 pll post scaler (post)?bits 15?13 the output of the pll is postscaler by 1 to 128 based on this field. when changing this field, it is recommended the sel bit is set to choose the oscillator output, changing this field, then the sel bit is returned to selecting the pll?s postscaler output. ? 000 = pll output is divided by one by default ? 001 = pll output is divided by two base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read post 0 0 0 0 0 0 plldb write reset 0000000000111011 occs resets 5685x digital signal controller user manual, rev. 4 6-16 freescale semiconductor ? 010 = pll output is divided by four ? 011 = pll output is divided by eight ? 100 = pll output is divided by 16 ? 101 = pll output is divided by 32 ? 110 = pll output is divided by 64 ? 111 = pll output is divided by 128 6.6.2.2 reserved?bits 12?7 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. 6.6.2.3 pll divide-by (plldb)?bits 6?0 the vco output frequency is controlled by the pll divide-by value. each time a new value is written into the plldb field, the lock detector circuit is reset. before changing the divide-by value, it is recommended the sel bit be set to choose the oscillator output. the vco output frequency is determined by using the following formula: fvco_out = fref (plldb + 1) 6.6.3 clock generation module (cgm) time-of-day register figure 6-11. cgm time-of-day register (cgmtod) see programmer?s sheet on appendix page b-17 6.6.3.1 reserved?bits 15?12 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. 6.6.3.2 tod scale factor (tod)?bits 11?0 the output of the oscillator is divided by (tod + 1) and then divided by 2, generating the time_clk used by the cop module when tod_sel is high. the value of tod should be chosen to result in a tod clock frequency in the range of 15.12khz to 31.25khz. this register is only reset during power-on reset (por). 6.7 occs resets the cgm registers are reset by a chip level reset. this forces all registers to their reset state and selects the oscillator output as the master clock source for the sim. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 tod write reset 0000000000000000 occs interrupts on-chip clock synthesis (occs), rev. 4 freescale semiconductor 6-17 6.8 occs interrupts the cgm generates a single interrupt request to the intc. this interrupt is generated by the lock detector circuitry lck0 and lck1 outputs and is enabled by the lck0 interrupt enable and lck1 interrupt enable bits in the cgmcr. this interrupt can be used to detect when the pll goes into lock or when it falls out of lock. the interrupt is cleared by writing a 1 to the lck0 and/or lck1 bits of the cgmcr. occs interrupts 5685x digital signal controller user manual, rev. 4 6-18 freescale semiconductor power-on reset (por) and computer operating properly (cop), rev. 4 freescale semiconductor 7-1 chapter 7 power-on reset (por) and computer operati ng properly (cop) 5685x digital signal controller user manual, rev. 4 7-2 freescale semiconductor features power-on reset (por) and computer operating properly (cop), rev. 4 freescale semiconductor 7-3 7.1 introduction the power-on reset (por) function monitors the core power supply, the i/o, and analog power supply. if either of those power supplies are below their thresholds, the por output for each respective supply is held high. once the power supply goes above the thresholds, the por outputs are held low. computer operating properly (cop) is also discussed in this chapter as it relates to resets. 7.2 features ? the circuit monitors both the core power supply and peripheral power supply ? holds a wide chip reset once either of these supply voltages are below the thresholds ? generates the address of the reset vector provided to the core after exit reset ? the address of reset vector (same as the cop reset) is located at $1f0000 the cop module design features include: ? programmable time-out period = (cop_prescaler (ct + 1)) oscillator clock cycles, where ct can be from $0000 to $ffff ? programmable wait and stop mode operations ? cop timer is disabled while host cpu is in debug mode block diagram 5685x digital signal controller user manual, rev. 4 7-4 freescale semiconductor 7.3 block diagram figure 7-1. por module block diagram 7.4 method of operation starting with the chip unpowered, the analog and digital power supplies turned on, the bandgap voltage reference and the comparators will begin to function. the bandgap voltage reference will apply a temperature and supply stable voltage reference to the positive inputs of the comparators. negative inputs of the comparators are connected to voltage points that move proportionately with respect to the analog and digital power supplies. initially, the bandgap voltage reference point is greater than the power supply reference signals and the output of the comparators is high. as each power supply goes above it?s trip point, the voltage on the respective comparators negative input will become higher in value than the bandgap voltage reference voltage on the positive input to the comparator and the output of the comparator will go low. if either power supply drops below the trip point the respective por output will again go high. for the analog power supply, the por trip point is: absolute minimum nominal absolute maximum 2.8v 2.85v 2.9v + ? bandgap voltage reference - + voltage level shifter voltage level shifter analog power gnd digital power gnd por_1.8 por_3.3 computer operating properly (cop) module power-on reset (por) and computer operating properly (cop), rev. 4 freescale semiconductor 7-5 for the digital power supply the por trip point is: this means, as long as the analog power supply is below 2.8v, the por_3p3 will be high. when the analog power supply exceeds 2.9v the por_3p3 output will be low. respectively, for the digital power supply, when the digital power supply is below 1.62v the por_1p8 output will be high. when the digital power supply is above 1.7v the por_1p8 output will be low. 7.5 computer operating properly (cop) module the computer operating properly (cop) module is used to help software recover from runaway code. the cop is a free-running down counter, once enabled is designed to generate a reset upon reaching zero. software must periodically service the cop in order to clear the counter and prevent a reset. 7.5.1 cop functional description when the cop is enabled, each positive edge of oscclk will cause the counter to decrement by one. if the count reaches a value of $0000, then the cop_rst signal is asserted and the chip is reset. in order for the cpu to show it is operating properly, it must perform a service routine prior to the count reaching $0000. the service routine consists of writing $5555 followed by $aaaa to copctr. 7.5.2 time-out specifications the cop uses a 16-bit counter, being clocked by the crystal oscillator clock prescaled by 128. table 7-1 presents the range of time-out values supported as a function of oscillator frequency. for a crystal operating at 4mhz the clock to the cop counter will be 31.25khz. the value of the copto register can be programmed from 1 to 65535 giving a time-out period range from 32sec minimum to 2.1sec maximum. absolute minimum nominal absolute maximum 1.62v 1.66v 1.7v table 7-1. cop time-out ranges as a function of oscillator frequency ct 2 mhz 4mhz $0000 64 sec 32 sec $ffff 4.2 sec 2.1 sec operating modes 5685x digital signal controller user manual, rev. 4 7-6 freescale semiconductor 7.5.3 cop after reset copctl is cleared out of reset. thus the counter is disabled by default. in addition, copto is set to it?s maximum value of $ffff during reset so the counter is loaded with a maximum time-out period when reset is released. 7.5.4 wait mode operation if both cen and cwen are set to 1 and the wait mode is entered, the cop counter will continue to count down. if either cen or cwen is set to 0 when wait mode is entered, the counter will be disabled and will reload using the value in the copto register. 7.5.5 stop mode operation if both cen and csen set to 1 and the stop mode is entered, the cop counter will continue to count down. if either cen or csen is set to 0 when stop mode is entered, the counter will be disabled and will reload using the value in the copto register. 7.5.6 debug mode operation the cop counter does not count when the chip is in the debug mode. additionally, the cen bit in the copctl always reads as 0 when the chip is in the debug mode. the actual value of cen is unaffected by debug however, and it resumes it?s previously set value upon exiting debug. 7.6 operating modes the cop module design contains two major modes of operation: ? functional mode the cop by default is in this mode and will remain in this mode for as long as the scantestmode input remains low. ? debug mode the cop timer is stopped while the processor is in debug mode. if the cop is enabled, the timer will resume, counting upon exiting debug mode. the cen bit in copctl register always reads as 0 when in the debug mode, even when it has a value of 1. module memory map power-on reset (por) and computer operating properly (cop), rev. 4 freescale semiconductor 7-7 7.7 block diagram figure 7-2. cop module bloc k diagram and interface signals 7.8 module memory map there are three registers on the cop peripheral described in table 7-2 . table 7-2. cop module memory map (cop_base = $1fffd0) address offset register acronym register name access type chapter location base + $0 copctl control register read/write section 7.9.1 base + $1 copto time-out register read/write section 7.9.2 base + $2 copctr counter register read/write section 7.9.3 add. offset register name 151413121110987654321 0 $0 copctl r 0 0 0 0 0 0 0 0 0 0 0 byps csen cwen cen cwp w $1 copto r timeout w $2 copctr r count w service r 0 read as 0 w reserved figure 7-3. cop register map summary counter registers oscclk ipbus clk ipbus cop_rst ipbus i/f register descriptions (cop_base = $1fffd0) 5685x digital signal controller user manual, rev. 4 7-8 freescale semiconductor 7.9 register descriptions (cop_base = $1fffd0) 7.9.1 cop control register (copctl) figure 7-4. cop control register (copctl) see programmer?s sheet on appendix page b-18 7.9.1.1 reserved?bits 15?5 this bit field is reserved or not implemented. each bit in the field is read as 0 and cannot be modified by writing. 7.9.1.2 bypass (byps)?bit 4 this bit is intended for factory use only. setting this bit allows testing time of the cop to be accelerated by routing the ipbus clock to the counter instead of the oscclk. this bit should not be set during normal operation of the chip. if this bit is used, however, it should only be changed while the cen bit is set to 0. ? 0 = counter uses oscclk (default) ? 1 = counter uses ipbus clock 7.9.1.3 cop stop mode enable (csen)?bit 3 this bit controls the operation of the cop counter in the stop mode. this bit can only be changed when the cwp bit is set to 0. ? 0 = cop counter will stop in the stop mode (default) ? 1 = cop counter will run in the stop mode if cen is set to 1 7.9.1.4 cop wait mode enable (cwen)?bit 2 this bit controls the operation of the cop counter in the wait mode. this bit can only be changed when the cwp bit is set to 0. ? 0 = cop counter will stop in the wait mode (default) ? 1 = cop counter will run in the wait mode if cen is set to 1 base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 byps csen cwen cen cwp write reset 000 0 0000000 0 0 0 0 0 register descriptions (cop_base = $1fffd0) power-on reset (por) and computer operating properly (cop), rev. 4 freescale semiconductor 7-9 7.9.1.5 cop enable (cen)?bit 1 this bit controls the operation of the cop counter. this bit can only be changed when the cwp bit is set to 0. this bit always reads as 0 when the chip is in the debug mode. ? 0 = cop counter is disabled (default) ? 1 = cop counter is enabled 7.9.1.6 cop write protect (cwp)?bit 0 this bit controls the write protection feature of the cop control (copctl) register and the cop time-out (copto) register. once set, this bit can only be cleared by resetting the module. ? 0 = copctl and copto are readable and writable (default) ? 1 = copctl and copto are read only 7.9.2 cop time-out register (copto) figure 7-5. cop time-out register (copto) see programmer?s sheet on appendix page b-19 7.9.2.1 cop time-out period (timeout)?bits 15?0 the value in this register determines the time-out period of the cop counter. timeout should be written before the cop is enabled. once the cop is enabled, the recommended procedure for changing timeout is to disable the cop, write to copto, then re-enable the cop, ensuring the new timeout is loaded into the counter. alternatively, the cpu can write to copto, then write the proper patterns to copctr, causing the counter to reload with the new timeout value. the cop counter is not reset by a write to copto. changing timeout while the cop is enabled will result in a time-out period differing from the expected value. these bits can only be changed when the cwp bit is set to 0. base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read timeout write reset 1111111111111111 clocks 5685x digital signal controller user manual, rev. 4 7-10 freescale semiconductor 7.9.3 cop counter register (copctr) figure 7-6. cop counter register (copctr) see programmer?s sheet on appendix page b-20 7.9.3.1 cop count (count)?bits 15?0 this is the current value of the cop counter as it counts down from the time-out value to zero. a reset is issued when this count reaches zero. 7.9.3.2 cop service (service)?bits 15?0 when enabled, the cop requires a service sequence be performed periodically in order to clear the cop counter and prevent a reset from being issued. this routine consists of writing $5555 to the copctr followed by writing $aaaa before the time-out period expires. the writes to copctr must be performed in the correct order, but any number of other instructions, and writes to other registers, may be executed between the two writes. 7.10 clocks the cop timer base is the oscillator clock divided by a fixed prescalar value. the prescalar divisor for this chip is 128. all register timing is with regard to the ipbus clock. 7.11 resets any system reset forces all registers to their reset state, clearing the rst signal when it is asserted. the counter will be loaded with its maximum value of $ffff, but it will not start when reset is released because the cen bit is disabled by default. 7.12 interrupts the cop module does not generate any interrupts. it does generate the rst signal when the counter reaches a value of $0000, causing a chip wide reset. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read count write service reset 1111111111111111 overview, rev. 4 freescale semiconductor 8-1 chapter 8 interrupt cont roller (itcn) 5685x digital signal controller user manual, rev. 4 8-2 freescale semiconductor introduction overview, rev. 4 freescale semiconductor 8-3 8.1 introduction the interrupt controller (itcn) is responsible for arbitrating all interrupt requests according to the priority level of the each request. this includes all external interrupt sources, such as irqa , irqb , and so on, peripheral generated interrupt requests and core generated interrupt requests. after arbitration, the interrupt controller will compare the priority of the current interrupt request with the current priority level of the core and if the request has higher priority to generate a single enabled interrupt request signal to the core. there are five levels of interrupt priority provided by the 56800e core, illustrated in table 8-1 : 1. lp = the lowest level is generated by the swilp instruction 2. level 0 = maskable with the lowest priority of the three maskable interrupts 3. level 1 = maskable 4. level 2 = maskable 5. level 3 = the highest priority is a non-maskable interrupt device interrupt priority levels are programmable via the interrupt priority register (ipr). the interrupt controller is also responsible for generating the vector address of the current interrupt request. this is based on the vector address base (vab) register and the event initiating the request. the interrupt controller predefines the vector table offsets for all possible interrupt sources and will generate the vector address of the request by adding the programmable vab register to the vector table offset. external interrupt sources such as irqa and irqb are programmable to either level sensitive or edge triggered. level sensitive interrupts remain active as long as the input remains low and are cleared when the input level goes high. the edge sensitive interrupts are latched as pending on the high-to-low transition of the interrupt input and are cleared when the interrupt is serviced. table 8-1. interrupt priority level ipl description priority interrupt sources lp maskable lowest swilp instruction 0 maskable ? on-chip peripherals, irqa and irqb, swi #0 instruction 1 maskable ? on-chip peripherals, irqa and irqb, swi #1 instruction, eonce interrupts 2 maskable ? on-chip peripherals, irqa and irqb, swi #2 instruction, eonce interrupts 3 non-maskable highest illegal instruction, hws overflow, swi #3 instruction, eonce interrupts, misaligned data access features 5685x digital signal controller user manual, rev. 4 8-4 freescale semiconductor the vector table is structured as two words per vector. this implies the interrupt vector offset, added to the vector base address, will be the vector number multiplied-by two. if the first instruction of an interrupt vector is a jsr or bsr, the core assumes a standard long interrupt. this is the normal case. the core then saves the status register and program counter and vectors to the address pointed to by the jsr. the interrupt is cleared by executing the return from interrupt instruction (rti or rtid) at the end of the interrupt service routine. the interrupt controller can also support up to two fast interrupts. there are four programmable registers in the controller, two for each fast interrupt, allowing set-up of a vector number to be configured as a fast interrupt, and a 21-bit absolute vector address pointing to the interrupt service routine. when the fast interrupt vector number register is programmed, the interrupt controller will intercept the normal vector table processing and insert the absolute address into the core via the vab bus. as long as the first instruction of the interrupt service routine is not a jsr or a bsr, the core will interpret the interrupt as a fast interrupt and begin inserting the code into the pipeline until a fast return from interrupt (frtid) is executed. the interrupt priority must be set to level two for the fast interrupt to operate properly. further, there can not be a jsr or bsr as the first instruction of the fast interrupt service routine. the return from interrupt must use the fast return from interrupt (frtid) instruction to clear the interrupt. reset is considered to be the highest priority interrupt and will take precedence over all other interrupts. if the reset pin is pulled low the interrupt controller will generate a reset vector address for the core and assert the re-signal in the core. 8.2 features the itcn module design includes these capabilities: ? programmable priority levels for each irq ? two programmable fast interrupts ? notification to sim module to restart clocks out of wait and stop modes 8.3 signal description the itcn module interfaces with the ipbus, the 56800e core, and the irq sources. there are no chip outputs driven directly by this module, but the irqa and irqb chip inputs do come to the itcn where they are re-synchronized to the system clock before use. module memory map overview, rev. 4 freescale semiconductor 8-5 8.4 module memory map there are 22 registers on the itcn peripheral described in table 8-2 . table 8-2. itcn module memory map (itcn_base = $1fff20) address offset register acronym register name access type chapter location base + $0 ipr0 interrupt priority register 0 read/write section 8.7.1 base + $1 ipr1 interrupt priority register 1 read/write section 8.7.2 base + $2 ipr2 interrupt priority register 2 read/write section 8.7.3 base + $3 ipr3 interrupt priority register 3 read/write section 8.7.4 base + $4 ipr4 interrupt priority register 4 read/write section 8.7.5 base + $5 ipr5 interrupt priority register 5 read/write section 8.7.6 base + $6 ipr6 interrupt priority register 6 read/write section 8.7.7 base + $7 ipr7 interrupt priority register 7 read/write section 8.7.8 base + $8 ipr8 iinterrupt priority register 8 read/write section 8.7.9 base + $9 vba vector base address register read/write section 8.7.10 base + $a fim0 fast interrupt match register 0 read/write section 8.7.11 base + $b fival0 fast interrupt vector address low 0 read/write section 8.7.12 base + $c fivah0 fast interrupt vector address high 0 read/write base + $d fim1 fast interrupt match register 1 read/write section 8.7.11 base + $e fival1 fast interrupt vector address low 1 read/write section 8.7.13 base + $f fivah1 fast interrupt vector address high 1 read/write section 8.7.14 base + $10 irqp0 irq pending register 0 read only section 8.7.15 base + $11 irqp1 irq pending register 1 read only base + $12 irqp2 irq pending register 2 read only base + $13 irqp3 irq pending register 3 read only base + $14 irqp4 irq pending register 4 read only base + $1a ictl interrupt control register read/write section 8.7.16 module memory map 5685x digital signal controller user manual, rev. 4 8-6 freescale semiconductor add. offset register name 151413121110987654321 0 $0 ipr0 r 0 0 bkpt_u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 w $1 ipr1 r 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl w $2 ipr2 r dma2 ipl dma1 ipl dma0 ipl 0 0 lock ipl 0 0 irqb ipl irqa ipl w $3 ipr3 r ss0_td ipl ss0_tdes ipl ss0_rls ipl ss0_rd ipl ss0_rdes ipl dma5 ipl dma4 ipl dma3 ipl w $4 ipr4 r spi_rcv ipl essi1_tls ipl essi1_td ipl essi1_tdes ipl essi1_rls ipl essi1_rd ipl essi1_ipl essi0_tls ipl w $5 ipr5 r host_xmit ipl host_rcv ipl sci0_rcv ipl sci0_rerr ipl sci0_ridl ipl sci0_tidl ipl sci0_xmit ipl spi_xmit ipl w $6 ipr6 r tovf1 ipl tcmp1 ipl tinp0 ipl tovf0 ipl tcmp0 ipl tod_ipl tod_alrm ipl host_cmd ipl w $7 ipr7 r 0 0 tinp3 ipl tovs3 ipl tcmp3 ipl tinp2 ipl tovf2 ipl tcmp2 ipl tinp1 ipl w $8 ipr8 r 0 0 0 0 0 0 sci1_rcv ipl sci1_rerr ipl sci1_ridl ipl sci1_tidl ipl sci1_xmit ipl w $9 vba r 0 0 0 vector_base_address w $a fim0 r 0 0 0 0 0 0 0 0 0 fast interrupt 0 w $d fim1 r 0 0 0 0 0 0 0 0 0 fast interrupt 1 w $b fival0 r fast interrupt 0 vector address low w $c fivah0 r 0 0 0 0 0 0 0 0 0 0 0 f fast interrupt 0 vector address high w $e fival1 r fast interrupt 1 vector address low w $f fivah1 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt1 vector address high w $10 irqp0 r pending [16:2] 1 w $11 irqp1 r pending [32:17] w $12 irqp2 r pending [48:33] w $13 irqp3 r pending [64:49] w $14 irqp4 r 1 1 1 1 1 1 1 1 1 1 1 pending [69:65] w $1a ictl r int ipic vab int_ dis 0 irqb state irqa state irqb edg irqa edg w r 0 read as 0 w reserved figure 8-1. itcn register map summary functional description overview, rev. 4 freescale semiconductor 8-7 8.5 block diagram the itcn module block diagram is illustrated figure 8-2 . figure 8-2. interrupt controller block diagram 8.6 functional description the interrupt controller is a slave on the ipbus. it contains registers each allowing the 70 interrupt sources to be set to one of four priority levels (excluding certain interrupts of fixed priority). next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. within a given priority level, zero is the highest priority and number 69 is the lowest. 2 >4 decode int1 int70 level 0 any 0 level any 3 level int vab ipic control 7 7 pic_en iack sr[9:8] priority level 2 >4 decode 70 >7 priority encoder level 3 priority level 70 >7 priority encoder register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-8 freescale semiconductor 8.7 register descriptions (itcn_base = $1fff20) 8.7.1 interrupt priority register 0 (ipr0) figure 8-3. interrupt priority register 0 (ipr0) see programmer?s sheet on appendix page b - 21 8.7.1.1 reserved?bits 15?14 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. 8.7.1.2 eonce breakpoint unit 0 interrupt priority level (bkpt_u0 ipl)?bits 13?12 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 8.7.1.3 eonce step counter interrupt priority level (stpcnt ipl)?bits 11?10 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 8.7.1.4 reserved?bits 9?0 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 bkpt_u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 write reset 0 0 0 0 0 0 0000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-9 8.7.2 interrupt priority register 1 (ipr1) figure 8-4. interrupt priority register 1 (ipr1) see programmer?s sheet on appendix page b - 22 8.7.2.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. 8.7.2.2 eonce receive register empty interrupt priority level (rx_reg ipl)?bits 5?4 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 8.7.2.3 eonce transmit register full interrupt priority level (tx_reg ipl)?bits 3?2 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 8.7.2.4 eonce trace buffer interrupt priority level (trbuf ipl)?bits 1?0 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl write reset 000 0000000 0 0 0 0 00 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-10 freescale semiconductor ? 11 = irq is priority level 3 8.7.3 interrupt priority register 2 (ipr2) figure 8-5. interrupt priority register 2 (ipr2) see programmer?s sheet on appendix page b - 23 8.7.3.1 dma 2 done interrupt priority level (dma2 ipl)?bits 15?14 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.3.2 dma 1 done interrupt priority level (dma1 ipl)?bits 13?12 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.3.3 dma 0 done interrupt priority level (dma0 ipl)?bits 11?10 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma2 ipl dma1 ipl dma0 ipl 0 0 lock ipl 0 0 irqb ipl irqa ipl write reset 0000000000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-11 8.7.3.4 reserved?bits 9?8 these bits are reserved, or are not implemented. they are read as 0, but they cannot be modified by writing. 8.7.3.5 pll loss of lock interrupt priority level (lock ipl)?bits 7?6 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.3.6 reserved?bits 5?4 these bits are reserved, or are not implemented. they are read as 0, but cannot be modified by writing. 8.7.3.7 external irq b interrupt priority level (irqb ipl)?bits 3?2 this bit field is used to set the interrupt priority levels for certain eonce irqs. these irqs are limited to priorities one through three and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.3.8 external irq a interrupt priority level (irqa ipl)?bits 1?0 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-12 freescale semiconductor 8.7.4 interrupt priority register 3 (ipr3) figure 8-6. interrupt priority register 3 (ipr3) see programmer?s sheet on appendix page b - 25 8.7.4.1 essi0 transmit data interrupt priority level (essi0_td ipl)?bits 15?14 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.4.2 essi0 transmit data with exception status interrupt priority level (essi0_tdes ipl)?bits 13?12 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.4.3 essi0 receive last slot interrupt priority level (essi0_rls ipl)?bits 11?10 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read ess0_td ipl ess0_tdes ipl ess0_rls ipl ess0_rd ipl ess0_rde s ipl dma5 ipl dma4 ipl dma3 ipl write reset 0000000000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-13 8.7.4.4 essi0 receive data interrupt priority level (essi0_rd ipl)?bits 9?8 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.4.5 essi0 receive data with exception status interrupt priority level (essi0_rdes ipl)?bits 7?6 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.4.6 dma 5 done interrupt priority level (dma5 ipl)?bits 5?4 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.4.7 dma 4 done interrupt priority level (dma4 ipl)?bits 3?2 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-14 freescale semiconductor ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.4.8 dma 3 done interrupt priority level (dma3 ipl)?bits 1?0 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.5 interrupt priority register 4 (ipr4) figure 8-7. interrupt priority register 4 (ipr4) see programmer?s sheet on appendix page b - 27 8.7.5.1 spi receiver full interrupt priority level (spi_rcv ipl)?bits 15?14 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.5.2 essi1 transmit last slot interrupt priority level (essi1_tls ipl)?bits 13?12 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spi_rcv ipl essi1_tls ipl essi1_td ipl essi1_tdes ipl essi1_rls ipl essi1_rd ipl essi1_rdes ipl essi0_tls ipl write reset 0000000000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-15 8.7.5.3 essi1 transmit data interrupt priority level (essi1_td ipl)? bits 11?10 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.5.4 essi1 transmit data with exception status interrupt priority level (essi1_tdes ipl)?bits 9?8 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.5.5 essi1 receive last slot interrupt priority level (essi1_rls ipl)?bits 7?6 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.5.6 essi1 receive data interrupt priority level (essi1_rd ipl)?bits 5?4 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-16 freescale semiconductor 8.7.5.7 essi1 receive data with exception status interrupt priority level (essi1_rdes ipl)?bits 3?2 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.5.8 essi0 transmit last slot interrupt priority level (essi0_tls ipl)?bits 1?0 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.6 interrupt priority register 5 (ipr5) figure 8-8. interrupt priority register 5 (ipr5) see programmer?s sheet on appendix page b - 29 8.7.6.1 host i/f transmit interrupt priority level (host_xmit ipl)?bits 15?14 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read host_xmit ipl host_rcv ipl sci0_rcv ipl sci0_rerr ipl sci0_ridl ipl sci0_tidl ipl sci0_xmit ipl spi_xmit ipl write reset 0000000000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-17 ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.6.2 host i/f receive data interrupt priority level (host_rcv ipl)?bits 13?12 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.6.3 sci 0 receiver full interrupt priority level (sci0_rcv ipl)?bits 11?10 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.6.4 sci0 receiver error interrupt priority level (sci0_rerr ipl)?bits 9?8 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-18 freescale semiconductor 8.7.6.5 sci0 receiver idle interrupt priority level (sci0_ridl ipl)?bits 7?6 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.6.6 sci0 transmitter idle interrupt priority level (sci0_tidl ipl)?bits 5?4 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.6.7 sci0 transmitter empty interrupt priority level (sci0_xmit ipl)?bits 3?2 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-19 8.7.6.8 spi transmitter empty interrupt priority level (spi_xmit ipl)?bits 1?0 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.7 interrupt priority register 6 (ipr6) figure 8-9. interrupt priority register 6 (ipr6) see programmer?s sheet on appendix page b - 31 8.7.7.1 timer channel 1 overflow interrupt priority level (tovf1 ipl)?bits 15?14 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.7.2 timer channel 1 compare interrupt priority level (tcmp1 ipl)?bits 13?12 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tovf1 ipl tcmp1 ipl tinp0 ipl tovf0 ipl tcmp0 ipl tod ipl tod_alrm ipl host_cmd ipl write reset 0000000000000000 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-20 freescale semiconductor 8.7.7.3 timer channel 0 input edge interrupt priority level (tinp0 ipl)?bits 11?10 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.7.4 timer channel 0 overflow interrupt priority level (tovf0 ipl)?bits 9?8 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.7.5 timer channel 0 compare interrupt priority level (tcmp0 ipl)?bits 7?6 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-21 8.7.7.6 time of day 1 second interval interrupt priority level (tod1 ipl)?bits 5?4 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.7.7 time of day alarm interrupt priority level (tod_alrm ipl)?bits 3?2 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.7.8 host i/f command interrupt priority level (host_cmd ipl)?bits 1?0 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.8 interrupt priority register 7 (ipr7) figure 8-10. interrupt priority register 7 (ipr7) see programmer?s sheet on appendix page b - 33 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 tinp3 ipl tovs3 ipl tcmp3 ipl tinp2 ipl tovf2 ipl tcmp2 ipl tinp1 ipl write reset 0000000000000000 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-22 freescale semiconductor 8.7.8.1 reserved?bits 15?14 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. 8.7.8.2 timer channel 3 input edge interrupt priority level (tinp3 ipl)?bits 13?12 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.8.3 timer channel 3 overflow interrupt priority level (tovf3 ipl)?bits 11?10 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.8.4 timer channel 3 compare interrupt priority level (tcmp3 ipl)?bits 9?8 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-23 8.7.8.5 timer channel 2 input edge interrupt priority level (tinp2 ipl)?bits 7?6 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.8.6 timer channel 2 overflow interrupt priority level (tovf2 ipl)?bits 5?4 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.8.7 timer channel 2 compare interrupt priority level (tcmp2 ipl)?bits 3?2 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.8.8 timer channel 1 input edge interrupt priority level (tinp1 ipl)?bits 1?0 this bit field is used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-24 freescale semiconductor 8.7.9 interrupt priority register 8 (ipr8) figure 8-11. interrupt priority register 8 (ipr8) 8.7.9.1 reserved?bits 15?10 these bits are reserved or not implemented. they are read as 0, but cannot be modified by writing. 8.7.9.2 receiver full interrupt priority level (sci1_rcv ipl)?bits 9?8 these fields are used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.9.3 receiver error interrupt priority level (sci1_rerr ipl)?bits 7?6 these fields are used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 sci1_rcv ipl sci1_rerr ipl sci1_ridl ipl sci1_tidl ipl sci1_xmit ipl write reset 0000000000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-25 8.7.9.4 receiver idle interrupt priority level (sci1_ridl ipl)?bits 5?4 these fields are used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.9.5 transmitter idle interrupt priority level (sci1_tidl ipl)?bits 3?2 these fields are used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.9.6 transmitter empty interrupt priority level (sci1_xmit ipl) ?bits 1?0 these fields are used to set the interrupt priority levels for certain peripheral irqs. these irqs are limited to priorities zero through two and are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 8.7.10 vector base address register (vba) figure 8-12. vector base address register (vba) see programmer?s sheet on appendix page b - 37 base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 vector_base_address write reset 000000000 0 000000 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-26 freescale semiconductor 8.7.10.1 reserved?bits 15?13 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. 8.7.10.2 interrupt vector base address (vector_base_address)?bits 12?0 the value in this register is used as the upper 13 bits of the interrupt vector vector address bus (vab)[20:0]. the lower eight bits are determined based on the highest priority interrupt and are then appended onto this field (vba) before presenting the full vector address bus (vab) to the 56800e core. 8.7.11 fast interrupt match registers (fim0 and fim1) figure 8-13. fast interrupt 0 match register (fim0) see programmer?s sheet on appendix page b - 38 note: although the 56800e core allows an unlimited number of fast interrupts, the 568xx family of chips limits this number to two in order to keep the size of the interrupt vector table small in terms of memory usage, and to reduce the overhead caused by each interrupt source having to provide a separate fast interrupt vector. 8.7.11.1 reserved?bits 15?7 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. 8.7.11.2 fast interrupt 0 vector number (fast interrupt 0) these values are used to declare which two irqs will be fast interrupts. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level 2. unexpected results will occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq. please refer to table 8-3 . base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 0 write reset 0000000000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-27 figure 8-14. fast interrupt 1 match register (fim1) see programmer?s sheet on appendix page b - 39 8.7.11.3 reserved?bits 15?7 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. 8.7.11.4 fast interrupt 1 vector number (fast interrupt 1) these values are used to declare which two irqs will be fast interrupts. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level 2. unexpected results will occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest priority level 2 interrupt regardless of their location in the interrupt table prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq. please refer to table 8-3 . 8.7.12 fast interrupt vector address registers (fival0, fivah0, fival1, fivah1) the following four registers are combined to form two, 21-bit vector addresses for the fast interrupts defined in the fim0 and fim1 registers. figure 8-15. fast interrupt 0 vector address low register (fival0) see programmer?s sheet on appendix page b - 40 8.7.12.1 fast interrupt 0 vector address low?bits 15?0 lower 16 bits of vector address for fast interrupt 0. base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 1 write reset 0000000000000000 base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 0 vector address low write reset 0000000000000000 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-28 freescale semiconductor figure 8-16. fast interrupt 0 vector address high register (fivah0) see programmer?s sheet on appendix page b - 40 8.7.12.2 reserved?bits 15?5 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. 8.7.12.3 fast interrupt 0 vector address high?bits 4?0 upper five bits of vector address for fast interrupt 0. 8.7.13 fast interrupt 1 vector address low register (fival1) figure 8-17. fast interrupt 1 vector address low register (fival1) see programmer?s sheet on appendix page b - 41 8.7.13.1 fast interrupt 1 vector address low?bits 15?0 lower 16 bits of vector address for fast interrupt 1 8.7.14 fast interrupt 1 vector address high register (fivah1) figure 8-18. fast interrupt 1 vector address high register (fivah1) see programmer?s sheet on appendix page b - 41 8.7.14.1 reserved?bits 15?5 these bits are reserved or not implemented. they are read as 0, but they cannot be modified by writing. base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high write reset 0000000000000000 base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 1 vector address low write reset 0000000000000000 base + $f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high write reset 0000000000000000 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-29 8.7.14.2 fast interrupt 1 vector address low?bits 4?0 upper five bits of vector address for fast interrupt 1. 8.7.15 irq pending registers (irqp0, irqp1, irqp2, irqp3, irqp4) these registers combine to represent the pending irqs for interrupt vector numbers two through 69. figure 8-19. irq pending register 0 (irqp0) see programmer?s sheet on appendix page b - 42 figure 8-20. irq pending register 1 (irqp1) see programmer?s sheet on appendix page b - 42 figure 8-21. irq pending register 2 (irqp2) see programmer?s sheet on appendix page b - 42 figure 8-22. irq pending register 3 (irqp3) see programmer?s sheet on appendix page b - 42 base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[16:1] 1 write reset 1111111111111111 base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[32:17] write reset 1111111111111111 base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[48:33] write reset 1111111111111111 base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending[64:49] write reset 1111111111111111 register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-30 freescale semiconductor figure 8-23. irq pending register 4 (irqp4) see programmer?s sheet on appendix page b - 42 8.7.15.1 pending irqs (pending)?bits 2?69 ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 8.7.15.2 reserved?bits 70?80 these bits are reserved or not implemented. they are read as 1, but they cannot be modified by writing. 8.7.16 interrupt control register (ictl) figure 8-24. interrupt control register (ictl) see programmer?s sheet on appendix page b - 43 8.7.16.1 interrupt (int)?bit 15 this bit reflects the state of the interrupt to the 56800e core. ? 0 = no interrupt is being sent to the core ? 1 = an interrupt is being sent to the core 8.7.16.2 interrupt priority level (ipic)?bits 14?13 these bits reflect the state of the new interrupt priority level bits being presented to the 56800e core at the time the last irq was taken. this field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be updated before the original interrupt service routine can read it. ? 00 = required nested exception priority levels are 0, 1, 2, or 3 base + $14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 pending[69:65] write reset 1111111111111111 base + $1a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int ipic vab int_dis 0 irqb state irqa state irqb edg irqa edg write reset 0 000000000 0 0 1 1 0 0 register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-31 ? 01 = required nested exception priority levels are 1, 2, or 3 ? 10 = required nested exception priority levels are 2 or 3 ? 11 = required nested exception priority level is 3 8.7.16.3 vector number (vab)?bits 12?6 this bit field shows the vector number, described in table 8-3 of the last irq taken. this bit field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 8.7.16.4 interrupt disable (int_dis)?bit 5 this bit allows the user to disable all interrupts. ? 0 = normal operation (default) ? 1 = all interrupts disabled 8.7.16.5 reserved?bit 4 this bit is reserved or not implemented. it is read as 0, but they cannot be modified by writing. 8.7.16.6 state of irqb (irqb state)?bit 3 this bit reflects the state of the external irqb pin. 8.7.16.7 state of irqa (irqa state)?bit 2 this bit reflects the state of the external irqa pin. 8.7.16.8 irqb edge (irqb edg)?bit 1 this bit controls whether the external irqb interrupt is edge or level sensitive. during stop and wait modes it is automatically level sensitive. ?0 = irqb interrupt is low level sensitive (default) ?1 = irqb interrupt is falling edge sensitive 8.7.16.9 irqa edge (irqa edg)?bit 0 this bit controls whether the external irqa interrupt is edge or level sensitive. during stop and wait modes it is automatically level sensitive. ?0 = irqa interrupt is low level sensitive (default) ?1 = irqa interrupt is falling edge sensitive register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-32 freescale semiconductor 8.7.17 interrupt vector map table 8-3 provides the list of interrupt vectors on the 56853 through 858 devices. as noted in the table, the total vector table size is 128 vectors or 256 words of memory. this table also provides the allowable priority range or fixed priority for each irq. table 8-3. interrupt vector table contents peripheral vector number priority level vector base address + interrupt function chip exceptions core 0 3 p:$00 reserved core 1 3 p:$02 reserved core 2 3 p:$04 illegal instruction ? core 3 3 p:$06 sw interrupt 3 ? core 4 3 p:$08 hw stack overflow ? core 5 3 p:$0a misaligned long word access ? core 6 1-3 p:$0c eonce step counter ? core 7 1-3 p:$0e eonce breakpoint unit 0 ? core 8 1-3 p:$10 reserved core 9 1-3 p:$12 eonce trace buffer ? core 10 1-3 p:$14 eonce transmit register empty ? core 11 1-3 p:$16 eonce receive register full ? core 12 0-3 p:$18 reserved core 13 0-3 p:$1a reserved core 14 2 p:$1c sw interrupt 2 ? core 15 1 p:$1e sw interrupt 1 ? core 16 0 p:$20 sw interrupt 0 ? core 17 0-2 p:$22 irqa ? core 18 0-2 p:$24 irqb ? core 19 0-2 p:$26 reserved pll 20 0-2 p:$28 pll loss of lock ? ? 21 0-2 p:$2a reserved dma 22 0-2 p:$2c dma_done 0 ? dma 23 0-2 p:$2e dma_done 1 ? dma 24 0-2 p:$30 dma_done 2 ? dma 25 0-2 p:$32 dma_done 3 ? dma 26 0-2 p:$34 dma_done 4 ? dma 27 0-2 p:$36 dma_done 5 ? essi 0 28 0-2 p:$38 essi 0 receive data with exception status ? essi 0 29 0-2 p:$3a essi 0 receive data ? essi 0 30 0-2 p:$3c essi 0 receive last slot ? essi 0 31 0-2 p:$3e essi 0 transmit data with exception status ? register descriptions (itcn_base = $1fff20) overview, rev. 4 freescale semiconductor 8-33 essi 0 32 0-2 p:$40 essi 0 transmit data ? essi 0 33 0-2 p:$42 essi 0 transmit last slot ? essi 1 34 0-2 p:$44 essi 1 receive data w/ exception status only for 857-858 essi 1 35 0-2 p:$46 essi 1 receive data only for 857-858 essi 1 36 0-2 p:$48 essi 1 receive last slot only for 857-858 essi 1 37 0-2 p:$4a essi 1 transmit data w/ exception status only for 857-858 essi 1 38 0-2 p:$4c essi 1 transmit data only for 857-858 essi 1 39 0-2 p:$4e essi 1 transmit last slot only for 857-858 spi 40 0-2 p:$50 spi receiver full not on 855 spi 41 0-2 p:$52 spi transmitter empty not on 855 sci 0 42 0-2 p:$54 sci 0 transmitter empty ? sci 0 43 0-2 p:$56 sci 0 transmitter idle ? sci 0 44 0-2 p:$58 sci 0 receiver idle ? sci 0 45 0-2 p:$5a sci 0 receiver error (receiver overrun, noise error, framing error, parity error) ? sci 0 46 0-2 p:$5c sci 0 receiver full ? hi8 47 0-2 p:$5e host receive data not on 855 hi8 48 0-2 p:$60 host transmit data not on 855 hi8 49 0-2 p:$62 host command (default) not on 855 tod 50 0-2 p:$64 tod alarm ? tod 51 0-2 p:$66 tod one second interval ? timer 52 0-2 p:$68 timer compare 0 ? timer 53 0-2 p:$6a timer overflow 0 ? timer 54 0-2 p:$6c timer input edge flag 0 ? timer 55 0-2 p:$6e timer compare 1 ? timer 56 0-2 p:$70 timer overflow 1 ? timer 57 0-2 p:$72 timer input edge flag 1 ? timer 58 0-2 p:$74 timer compare 2 ? timer 59 0-2 p:$76 timer overflow 2 ? timer 60 0-2 p:$78 timer input edge flag 2 ? timer 61 0-2 p:$7a timer compare 3 ? timer 62 0-2 p:$7c timer overflow 3 ? timer 63 0-2 p:$7e timer input edge flag 3 ? core 64 -1 p:$80 sw interrupt lp ? sci 1 65 0-2 p:$82 sci 1 transmitter empty ? sci 1 66 0-2 p:$84 sci 1 transmitter idle ? sci 1 67 0-2 p:$86 sci 1 receiver idle ? sci 1 68 0-2 p:$88 sci 1 receiver error (receiver overrun, noise error, framing error, parity error) ? table 8-3. interrupt vector table contents (continued) peripheral vector number priority level vector base address + interrupt function chip exceptions register descriptions (itcn_base = $1fff20) 5685x digital signal controller user manual, rev. 4 8-34 freescale semiconductor sci 1 69 0-2 p:$8a sci 1 receiver full ? hi8 70 p:$8c available for host command not on 855 hi8 71 p:$8e available for host command not on 855 hi8 72 p:$90 available for host command not on 855 hi8 73 p:$92 available for host command not on 855 hi8 74 note: controlled by vector 49 p:$94 available for host command not on 855 hi8 75 p:$96 available for host command not on 855 hi8 76 p:$98 available for host command not on 855 hi8 77 p:$9a available for host command not on 855 hi8 78 p:$9c available for host command not on 855 hi8 79 p:$9e available for host command not on 855 hi8 80 p:$a0 available for host command not on 855 hi8 81 p:$a2 available for host command not on 855 hi8 82 p:$a4 available for host command not on 855 hi8 83 p:$a6 available for host command not on 855 hi8 84 p:$a8 available for host command not on 855 hi8 85 p:$aa available for host command not on 855 hi8 86 p:$ac available for host command not on 855 hi8 87 p:$ae available for host command not on 855 hi8 88 p:$b0 available for host command not on 855 hi8 89 p:$b2 available for host command not on 855 hi8 90 p:$b4 available for host command not on 855 hi8 91 p:$b6 available for host command not on 855 hi8 92 p:$b8 available for host command not on 855 hi8 93 p:$ba available for host command not on 855 hi8 94 p:$bc available for host command not on 855 hi8 95 p:$be available for host command not on 855 hi8 96 p:$c0 available for host command not on 855 hi8 97 p:$c2 available for host command not on 855 hi8 98 p:$c4 available for host command not on 855 hi8 99 p:$c6 available for host command not on 855 hi8 100 p:$c8 available for host command not on 855 hi8 101 p:$ca available for host command not on 855 hi8 102 p:$cc available for host command not on 855 hi8 103 p:$ce available for host command not on 855 hi8 104 p:$d0 available for host command not on 855 hi8 105 p:$d2 available for host command not on 855 hi8 106 p:$d4 available for host command not on 855 hi8 107 p:$d6 available for host command not on 855 hi8 108 p:$d8 available for host command not on 855 hi8 109 p:$da available for host command not on 855 hi8 110 p:$dc available for host command not on 855 table 8-3. interrupt vector table contents (continued) peripheral vector number priority level vector base address + interrupt function chip exceptions host control interrupt vector overview, rev. 4 freescale semiconductor 8-35 8.8 wait and stop mode operations the system clocks and the 56800e are turned off during wait and stop modes. the itcn will signal a pending irq to the system integration module (sim) to restart the clocks and service the irq. an irq can only wake up the core if the irq is enabled prior to entering the wait or stop mode. also, the irqa and irqb signals automatically become low level sensitive in these modes even if the control register bits are set to make them falling edge sensitive. this is because there is no clock available to detect the falling edge. 8.9 host control interrupt vector the host command irq, vector 49, acts differently than the other irqs. the vector 49 value driven onto the lower eight bits of vab in response to this irq isn?t fixed as it is for the other irqs. the host i/f module supplies these lower bits and the itcn uses them when the interrupt to the 56800e is in response to the host command irq. the itcn also asserts the hp_irq_ack signal back to the host port module when the itcn receives acknowledgement from the cpu in response to the host command irq. hi8 111 p:$de available for host command not on 855 hi8 112 note: controlled by vector 49 p:$e0 available for host command not on 855 hi8 113 p:$e2 available for host command not on 855 hi8 114 p:$e4 available for host command not on 855 hi8 115 p:$e6 available for host command not on 855 hi8 116 p:$e8 available for host command not on 855 hi8 117 p:$ea available for host command not on 855 hi8 118 p:$ec available for host command not on 855 hi8 119 p:$ee available for host command not on 855 hi8 120 p:$f0 available for host command not on 855 hi8 121 p:$f2 available for host command not on 855 hi8 122 p:$f4 available for host command not on 855 hi8 123 p:$f6 available for host command not on 855 hi8 124 p:$f8 available for host command not on 855 hi8 125 p:$fa available for host command not on 855 hi8 126 p:$fc available for host command not on 855 hi8 127 p:$fe available for host command not on 855 table 8-3. interrupt vector table contents (continued) peripheral vector number priority level vector base address + interrupt function chip exceptions resets 5685x digital signal controller user manual, rev. 4 8-36 freescale semiconductor 8.10 resets 8.10.1 reset handshake timing the itcn provides the 56800e with a reset vector address on the vab pins whenever rst is asserted. the reset vector will be presented until the first rising clock edge after rst is released. the general timing is shown in figure 8-25 . figure 8-25. reset interface 8.10.2 itcn after reset after reset, all of the itcn registers are in their default states. this means all interrupts are disabled except the core irqs with fixed priorities. those are: ? illegal instruction ? sw interrupt 3 ? hw stack overflow ? misaligned long word access ? sw interrupt 2 ? sw interrupt 1 ? sw interrupt 0 ? sw interrupt lp core irqs are enabled at their fixed priority levels. 8.11 interrupts 8.11.1 interrupt handshake timing the control logic looks a the current interrupt processing level using the sr_reg[9:8] bits from the 56800e core and determines if an interrupt request of sufficient priority exists to assert the interrupt output to the core. upon asserting int to the core, the interrupt controller also asserts new values for the ipic_level pins. these pins indicate the priority level required to interrupt clk vab reset_vector_adr res pab read_adr interrupts overview, rev. 4 freescale semiconductor 8-37 this newly requested interrupt. the core will latch ipic_level and it will be driven back to the interrupt controller as new values on the sr_reg[9:8] pins. when the 56800e core recognizes the assertion of the interrupt pin, it will deassert pic_en which tells the interrupt controller to drive vab with the address corresponding to the highest priority interrupt request in order to start the interrupt service routine. when the 56800e core asserts the iack signal, the interrupt controller will deassert the interrupt signal to the core. the controller will not reassert the interrupt signal until pic_en is asserted by the 56800e core. figure 8-26. interrupt handshake timing 8.11.2 interrupt nesting interrupt exceptions may be nested to allow an irq of higher priority than the current exception to be serviced. the following tables define the nesting requirements for each priority level. table 8-4. interrupt mask bit definition sr sr exceptions permitted exceptions masked 0 0 priorities 0, 1, 2, 3 none 0 1 priorities 1, 2, 3 priority 0 1 0 priorities 2,3 priorities 0, 1 1 1 priority 3 priorities 0, 1, 2 vab clk int pic_en sr_reg[9:8] 00 01 iack ipic_level 00 01 01 00 01 v0 v0 irq_b interrupts 5685x digital signal controller user manual, rev. 4 8-38 freescale semiconductor table 8-5. interrupt priority encoding ipic_level current interrupt priority level required nested exception priority 00 no interrupt or swilp priorities 0, 1, 2, 3 01 priority 0 priorities 1, 2, 3 10 priority 1 priorities 2, 3 11 priorities 2 or 3 priority 3 interrupts overview, rev. 4 freescale semiconductor 8-39 interrupts 5685x digital signal controller user manual, rev. 4 8-40 freescale semiconductor direct memory access (dma), rev. 4 freescale semiconductor 9-1 chapter 9 direct memory access (dma) 5685x digital signal controller user manual, rev. 4 9-2 freescale semiconductor signal description direct memory access (dma), rev. 4 freescale semiconductor 9-3 9.1 introduction the direct memory access (dma) controller transfers data between points in the memory map without intervention by the cpu. the dma controller allows movements of data to and from internal data memory or internal peripherals such as ssi, sci, spi, and so on, to occur in the background of cpu operation. the 5685x packages include six independent programmable dma channels, allowing six different contexts for dma operation. 9.2 features the dma features consist of: ? dma perpetration independently of the cpu ? six channels supporting six independent block transfers ? the dma controller has access to a maximum of one-third of the system bus traffic. this duty cycle is governed by the 5685x system bus controller. ? each channel has independently programmable peripheral selection. ? each channel?s source and destination address registers indices can be configured. for each memory fetch and put , the address may be post-incriminated, post-decremented, or remain constant. ? each read/write transfer may be initiated by selected events, specified peripheral requests, or direct cpu triggering may launch a new dma transaction. ? upon completion of a block transfer, each dma channel may send an interrupt to the cpu. ? the dma includes a circular queue operational mode to provide continuous dma operation with no additional processor intervention. 9.3 signal description the dma controller signals are described in table 9-1 through table 9-3 . table 9-1. dma common signals name type function clock domain reset input dma reset clears all internal registers and resets dma state machine. ? signal description 5685x digital signal controller user manual, rev. 4 9-4 freescale semiconductor table 9-2. dma ipbus signals name type function clock domain ipbus_clk input ipbus clock ? ipbus_addr[2:0] input dma ipbus register select ipbus_clk ipbus_data_in[15:0] input write data from ipbus to dma registers ipbus_clk ipbus_data_out[15:0] output read data to ipbus from dma registers ipbus_clk ipbus_r/w input ipbus read/write signal ipbus_clk ipbus_sel input select signal for dma controller ipbus_clk ipbus_req[30:0] input dma request signal from ipbus peripheral ipbus_clk dma_intr output dma interrupt request signal (active low) ipbus_clk ip_phase input data signal indicating ipbus phase sys_clk table 9-3. dma x1 bus signals name type function clock domain sys_clk input system clock ? x1_bus_request output dma request to system bus controller (sbc) sys_clk x1_bus_grant input dma grant signal from sbc sys_clk x1_addr_out[23:0] output dma-provided data space address sys_clk x1_w_data[31:0] output dma-provided data sys_clk x1_w output dma system bus write signal sys_clk x1_r_data[31:0] input sbc-provided system bus read data sys_clk x1_r output dma system bus read signal sys_clk x1_size output size of data written (byte, word, long) sys_clk module memory maps direct memory access (dma), rev. 4 freescale semiconductor 9-5 9.4 module memory maps the 5685x devices contain six independent dma channels. each dma channel includes seven user-programmable 16-bit registers. base addresses of each register set are provided in table 9-4 through table 9-9 . table 9-4. dma 0 register address map (dma0_base = $1ffec0) address offset register acronym register name accesss type chapter location base + $0 dma_3_tc transfer control read/write section 9.6.1 base + $1 dma_3_cqs circular queue size read/write section 9.6.2 base + $2 dma_3_tc transfer count read/write section 9.6.3 base + $3 dma_3_dal destination address-low read/write section 9.6.4 base + $4 dma_3_dah destination address-high read/write section 9.6.5 base + $5 dma_3_sal source address-low read/write section 9.6.6 base + $6 dma_3_sah source address-high read/write section 9.6.7 table 9-5. dma 1 register address map (dma1_base = $1ffec8) address offset register acronym register name accesss type chapter location base + $0 dma_3_tc transfer control read/write section 9.6.1 base + $1 dma_3_cqs circular queue size read/write section 9.6.2 base + $2 dma_3_tc transfer count read/write section 9.6.3 base + $3 dma_3_dal destination address-low read/write section 9.6.4 base + $4 dma_3_dah destination address-high read/write section 9.6.5 base + $5 dma_3_sal source address-low read/write section 9.6.6 base + $6 dma_3_sah source address-high read/write section 9.6.7 table 9-6. dma 2 register address map (dma2_base = $1ffed0) address offset register acronym register name access type chapter location base + $0 dma_3_tc transfer control read/write section 9.6.1 base + $1 dma_3_cqs circular queue size read/write section 9.6.2 base + $2 dma_3_tc transfer count read/write section 9.6.3 base + $3 dma_3_dal destination address-low read/write section 9.6.4 base + $4 dma_3_dah destination address-high read/write section 9.6.5 base + $5 dma_3_sal source address-low read/write section 9.6.6 base + $6 dma_3_sah source address-high read/write section 9.6.7 module memory maps 5685x digital signal controller user manual, rev. 4 9-6 freescale semiconductor table 9-7. dma 3 register address map (dma3_base = $1ffed8) address offset register acronym register name access type chapter location base + $0 dma_3_tc transfer control read/write section 9.6.1 base + $1 dma_3_cqs circular queue size read/write section 9.6.2 base + $2 dma_3_tc transfer count read/write section 9.6.3 base + $3 dma_3_dal destination address-low read/write section 9.6.4 base + $4 dma_3_dah destination address-high read/write section 9.6.5 base + $5 dma_3_sal source address-low read/write section 9.6.6 base + $6 dma_3_sah source address-high read/write section 9.6.7 table 9-8. dma 4 register address map (dma4_base = $1ffee0) address offset register acronym register name access type chapter location base + $0 dma_4_tc transfer control read/write section 9.6.1 base + $1 dma_4_cqs circular queue size read/write section 9.6.2 base + $2 dma_4_tc transfer count read/write section 9.6.3 base + $3 dma_4_dal destination address-low read/write section 9.6.4 base + $4 dma_4_dah destination address-high read/write section 9.6.5 base + $5 dma_4_sal source address-low read/write section 9.6.6 base + $6 dma_4_sah source address-high read/write section 9.6.7 table 9-9. dma 5 register address map (dma5_base = $1ffee8) address offset register acronym register name access type chapter location base + $0 dma_5_tc transfer control read/write section 9.6.1 base + $1 dma_5_cqs circular queue size read/write section 9.6.2 base + $2 dma_5_tc transfer count read/write section 9.6.3 base + $3 dma_5_dal destination address-low read/write section 9.6.4 base + $4 dma_5_dah destination address-high read/write section 9.6.5 base + $5 dma_5_sal source address-low read/write section 9.6.6 base + $6 dma_5_sah source address-high read/write section 9.6.7 dma controller block diagram direct memory access (dma), rev. 4 freescale semiconductor 9-7 9.5 dma controller block diagram one channel of the dma controller is depicted in figure 9-2 . figure 9-2. dma controller add. offset register name 151413121110987654321 0 $0 dmatc r dma on intr on intr pend data size 0 0 0 periph sel ss/m ds/m w 0 0 0 $1 dmacqs r dma circular queue size w $2 dmacnt r dma transfer count w $3 damdal r dma destination address (low) w $4 dmadah r 0 0 0 0 0 0 0 0 dma destination address (high) r 0 0 0 0 0 0 0 0 $5 dmasal r dma source address (low) w $6 dmasah r 0 0 0 0 0 0 0 0 dma source address (high) w 0 0 0 0 0 0 0 0 r 0 read as 0 w reserved figure 9-1. dma register map summary x1_bus_grant ipbus_addr ipbus_data_in ipbus_data_out ipbus_r/w ipbus_sel ipbus_clk ip_phase dma_req_[n] reset x1_bus_request x1_addr-out x1_w_data x1_w x1_r x1_size x1_r_data sys_clk dma_intr 24 2 32 32 3 16 31 16 register descriptions (dma_bases = $1ffec0, $1ffec8, $1ffed0, $1ffed8, $1ffee0, $1ffee8) 5685x digital signal controller user manual, rev. 4 9-8 freescale semiconductor 9.6 register descriptions (dma_bases = $1ffec0, $1ffec8, $1ffed0, $1ffed8, $1ffee0, $1ffee8) 9.6.1 dma transfer control (dmatc) figure 9-3. dma transfer control (dmatc) see programmer?s sheet on appendix page b - 51 9.6.1.1 direct memory access on (dmaon)?bit 15 this bit enables/disables dma operation. when the circular queue operation is disabled and the dmacqs register is zero, this bit is automatically cleared at the conclusion of a dma block transfer or when the transfer count register decrements to zero. ? 0 = dma operation is disabled ? 1 = dma operation is enabled 9.6.1.2 interrupt on (intron)?bit 14 this bit enables/disables dma interrupt operation. if dma interrupt operation is enabled, the dma controller issues an interrupt whenever the dma transfer count register (dmacnt) decrements to zero. ? 0 = dma interrupt operation is disabled ? 1 = dma interrupt operation is enabled 9.6.1.3 interrupt pending (intrpend)?bit 13 this bit is the dma interrupt pending bit. when this bit is asserted, a dma interrupt is pending; when this bit is deasserted, no dma interrupt is pending. ? 0 = a dma interrupt is not pending ? 1 = a dma interrupt is pending 9.6.1.4 data size (datasize)?bit 12 this bit defines the data size of the dma transfers and determines whether the dma address registers point to words or bytes. ? 0 = dma transfers are performed in bytes (8 bits), with address registers pointing to bytes. ? 1 = dma transfers are performed in words (16 bits), with address registers pointing to words. base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dmaon intron intr_pend data_ size 0 0 0 periph sel ss/m ds/m write 0 0 0 reset 0 0 0 0 00000000000 0 register descriptions (dma_bases = $1ffec0, $1ffec8, $1ffed0, $1ffed8, $1ffee0, $1ffee8) direct memory access (dma), rev. 4 freescale semiconductor 9-9 9.6.1.5 reserved?bits 11?9 these bits are reserved or not implemented. they are read as, and written with 0s. 9.6.1.6 peripheral select (periph_sel)?bits 8?4 this five-bit field selects one of 16 possible dma peripherals. table 9-10 illustrates the peripheral selected for each setting of this field. when the dma is enabled, the peripheral chosen by this field controls the start of the dma operation. that is, when the selected dma_req [peripheral select] line is asserted, the dma operation begins. note: if peripheral select is equal to zero, dma operation begins immediately after dma operation is enabled (via asserting the dma on bit). this mechanism may be used for memory-to-memory transfers. if a peripheral-to-peripheral dma transfer is desired, peripheral select should be set to the slower of the two peripherals to prevent data overruns. note: whenever doing dma transfers with peripherals, datasize should be set as word mode. table 9-10. dma_req connections dma_req line peripheral transfer control register peripheral select field 15 hi8 high transmitter 16 14 hi8 high receiver 15 13 essi1 transmitter 2 14 12 essi1 transmitter 1 13 11 essi1 transmitter 0 12 10 essi1 receiver 11 9 essi0 transmitter 2 10 8 essi0 transmitter 1 9 7 essi0 transmitter 0 8 6 essi0 receiver 7 5 sci1 transmitter 6 4 sci1 receiver 5 3 sci0 transmitter 4 2 sci0 receiver 3 1 spi transmitter 2 0 spi receiver 1 register descriptions (dma_bases = $1ffec0, $1ffec8, $1ffed0, $1ffed8, $1ffee0, $1ffee8) 5685x digital signal controller user manual, rev. 4 9-10 freescale semiconductor to select a peripheral to trigger a dma operation, the peripheral select field of the dma transfer control register is written with the value dma_req line + 1. for example, if you want the sci1 receiver to initiate a dma request, write the value 5 into the peripheral select field of the dma transfer control register. 9.6.1.7 source sign/magnitude (ss/m)?bits 3?2 this two-bit field determines how the dma source address register gets changed after each dma read operation. the source address register may remain unchanged, be post-incriminated, or be post-decremented as follows: ? 0x = do not change the address register ? 10 = increment the address register (by the data size amount) after each read ? 11 = decrement the address register (by the data size amount) after each read 9.6.1.8 destination sign/magnitude (ds/m)?bits 1?0 this two-bit field determines how the dma destination address register gets changed after each dma write operation. the destination address register may remain unchanged, be post-incriminated, or be post-decremented as follows: ? 0x = do not change the address register ? 10 = increment the address register (by the data size amount) after each read ? 11 = decrement the address register (by the data size amount) after each read 9.6.2 dma circular queue size (dmacqs) figure 9-4. dma circular queue size (dmacqs) see programmer?s sheet on appendix page b - 50 9.6.2.1 circular queue size (dmacqs)?bits 15?0 this register determines the size of the circular queue. it defaults to all zeros. when zero, circular queue operation is disabled. when the circular queue size is non-zero, circular queue mode is operational. in this mode, the dma destination address register changes with post-increments or post-decrements for each dma write operation. the circular queue size is decremented after each write. when the circular queue size reaches zero it is restored to its initial value. the dma destination address register is also restored to its initial value. this base+ $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma circular queue size write reset 0000000000000000 register descriptions (dma_bases = $1ffec0, $1ffec8, $1ffed0, $1ffed8, $1ffee0, $1ffee8) direct memory access (dma), rev. 4 freescale semiconductor 9-11 restoration allows the circular queue to continuously update with new data without additional central processing unit (cpu) intervention. note: if interrupts are enabled while in the circular queue mode the dma transfer count register is used to determine when interrupts are issued. note: if both the source and destination registers are set to change using post- increment or post-decrement, both registers will be returned to their initial values. 9.6.3 dma transfer count (dmacnt) figure 9-5. dma transfer count (dmacnt) see programmer?s sheet on appendix page b - 49 9.6.3.1 transfer count (dmacnt)?bits 15?0 this is the count of the number of items (bytes or words) to transfer in the dma data block. this value is decremented after each dma write operation. if dma interrupts are enabled, a dma interrupt will be asserted when this count reaches zero. if circular queue operation is enabled, the transfer count register is reloaded with its initial count value when it reaches zero. this permits continuous dma operation without additional central processing unit (cpu) intervention. in the circular queue operational mode and interrupts enabled an interrupt is issued each time the transfer count reaches zero, if dma. each interrupt indicates the complete transfer of one count-sized block of data. 9.6.4 dma destination address low (dmadal) figure 9-6. dma destination address low (dmadal) see programmer?s sheet on appendix page b - 48 9.6.4.1 destination address low (dmadal)?bits 15?0 this is the lower word of the dma destination address. dma data is written from this address. if post-incrementing (or decrementing) is enabled, this value is updated with each write transaction. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma transfer count write reset 0000000000000000 base+ $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma destination address (low) write reset 0000000000000000 register descriptions (dma_bases = $1ffec0, $1ffec8, $1ffed0, $1ffed8, $1ffee0, $1ffee8) 5685x digital signal controller user manual, rev. 4 9-12 freescale semiconductor 9.6.5 dma destination side address high (dmadah) figure 9-7. dma destination address high (dmadah) see programmer?s sheet on appendix page b - 47 9.6.5.1 reserved?bits 15?8 these bits are reserved or not implemented. they are read as, and written with 0s. 9.6.5.2 destination address high (dmadah)?bits 7?0 this is the upper byte of the dma destination address. dma data is written from this address. if post-incrementing (or decrementing) is enabled, this value is updated with each write transaction. 9.6.6 dma source address low (dmasal) figure 9-8. dma source address low (dmasal) see programmer?s sheet on appendix page b - 46 9.6.6.1 source address low (dmasal)?bits 15-0 this is the lower word of the dma source address. dma data is read from this address. if post-incrementing (or decrementing) is enabled, this value is updated with each read transaction. 9.6.7 dma source address high (dmasah) figure 9-9. dma source address high (dmasah) see programmer?s sheet on appendix page b - 45 9.6.7.1 reserved?bits 15?8 these bits are reserved or not implemented. they are read as, and written with 0s. base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 dma destination address (high) write 0 0 0 0 0 0 0 0 reset 0000000000000000 base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma source address (low) write reset 0000000000000000 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 dma source address (high) write 0 0 0 0 0 0 0 0 reset 0000000000000000 programming examples direct memory access (dma), rev. 4 freescale semiconductor 9-13 9.6.7.2 source address high (dmasah)?bits 7?0 this is the upper byte of the dma source address. dma data is read from this address. if post-incrementing (or decrementing) is enabled, this value is updated with each read transaction. 9.7 programming examples three different scenarios are described to illustrate the use of dma. 9.7.1 peripheral-to-memory dma operation in the first scenario, transfer data from an spi peripheral to a 16-word block of data memory starting at address $1000 is desired. the spi data receive register is located at x:$1fffea. the spi receive is assigned to dma_req[1] and is provided in table 9-10 . in this scenario, assume the spi is configured to transfer data by16-bit words. we would like the dma to interrupt the core when the transfer is completed. to configure the dma to perform this operation, follow these seven steps: 1. write $001f to the dma source address (high) register 2. write $ffea to the dma source address (low) register 3. write $0000 to the dma destination address (high) register 4. write $1000 to the dma destination address (low) register 5. write $0010 (hex = 16 decimal) to the dma transfer count register 6. write $0000 to the dma circular queue size register to disable the circular queue 7. write $d012 to the dma transfer control register steps 1 through 6 above may be performed in any order; however, step seven must be performed last. in step seven follow these steps: ? the dma is enabled (dmaon = 1) ? dma interrupts are enabled (intron = 1) ? the dma interrupt pending bit is cleared (intrpend = 0) ? the dma data size is set to word (datasize = 1) ? the spi peripheral (dma_req[1]) is selected for monitoring. ? the dma source is set to not change values, to repeatedly read spi data from the spi data receive register (ssim = 0) ? the dma destination address is set to increment (cdsim = 10) (by words because datasize = 1) programming examples 5685x digital signal controller user manual, rev. 4 9-14 freescale semiconductor 9.7.2 memory-to-memory dma operation i n this scenario assume there are 256 bytes of data at address $1000 and the data is to be moved in reversed order to memory starting at $200 with a 256-byte buffer. figure 9-10 depicts this oper- ation. figure 9-10. memory-to-memory dma mode in this scenario, the dma is to interrupt the core when the transfer is completed. to configure the dma to perform this operation, follow these steps: 1. write $0000 to the dma source address (high) register 2. write $1000 to the dma source address (low) register (first write is from $00001000) 3. write $0000 to the dma destination address (high) register 4. write $20ff to the dma destination address (low) register (first write is from $000020ff) 5. write $0100 to the dma transfer count register (block is 256 bytes long) 6. write $0000 to the dma circular queue size register (disable circular queue) 7. write $c00b to the dma transfer control register steps 1 through 6 above may be performed in any order; however, step seven must be performed last. addr data addr data $1000 $01 $2000 $00 $1001 $02 $2001 $ff $1002 $03 $2002 $fe $1003 $04 $2003 $fd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $10fe $ff $20fe $02 $10ff $00 $20ff $01 programming examples direct memory access (dma), rev. 4 freescale semiconductor 9-15 note: because this scenario wishes to store the byte sized data in reverse order , the initial destination address $2000 + $100 -1 = $20ff. note: the transfer control register is written to increment the source address register and decrement the destination address register. in step seven, the dma is enabled (damon =1), dma interrupts are enabled (intron = 1), the dma interrupt pending bit is cleared, the dma data size is set to byte, $0 is written to the peripheral select field (indicating a memory-to-memory dma operation), the dma source is set to increment by bytes (cssim = 0), and the dma destination address is set to decrement by bytes (dsim = 11). 9.7.3 peripheral-to-memory circular queue dma operation in this scenario, assume you want to transfer data from a sci peripheral in a continuous transfer mode. the sci0 data read register is at $1fffe4. the sci0 is assigned to dma_req[3], illustrated in table 9-10 . the sci is transferring one byte at a time, but it is stored as a word. you want the dma to interrupt the core at the completion of each 40-word packet . the data is to be placed into a 400-word circular queue beginning at address $5000. figure 9-11 illustrates this operation. programming examples 5685x digital signal controller user manual, rev. 4 9-16 freescale semiconductor note: in the circular queue mode, the dma operation runs endlessly until the dma is explicitly turned off by the processor. if the byte mode is selected, source and destination addresses have no boundary restrictions. figure 9-11. dma circular queue operation to configure the dma to perform this operation, the following steps would be taken: 1. write $001f to the dma source address (high) register 2. write $ffe4 to the dma source address (low) register 3. write $0000 to the dma destination address (high) register 4. write $5000 to the dma destination address (low) register 5. write $0028 (hex = 40 decimal) to the dma transfer count register 6. write $0190 (hex = 400 decimal) to the dma circular queue size register 7. write $d032 to the dma transfer control register steps 1 through 6 above may be performed in any order; however, step seven must be performed last. in step seven follow these steps: ? the dma is enabled (dmaon = 1) ? dma interrupts are enabled (intron = 1) ? the dma interrupt pending bit is cleared (interpend = 0) 40-word packet 40-word packet 40-word packet 40-word packet 40-word packet 40-word packet 40-word packet 40-word packet 40-word packet 40-word packet 400-word circular buffer $5000 $518f dma intr dma intr dma intr dma intr dma intr dma intr dma intr dma intr dma intr dma intr programming examples direct memory access (dma), rev. 4 freescale semiconductor 9-17 ? the dma data size is set to word (datasize = 1) ? the sci0 peripheral (dma_req[3]) is selected for monitoring. ? the dma source is set to not change values to repeatedly read sci data from the sci0 data receive register (ssim = 00) ? the dma destination address is set to increment by words (dsim = 10) programming examples 5685x digital signal controller user manual, rev. 4 9-18 freescale semiconductor serial communications interface (sci), rev. 4 freescale semiconductor 10-1 chapter 10 serial communications interface (sci) 5685x digital signal controller user manual, rev. 4 10-2 freescale semiconductor features serial communications interface (sci), rev. 4 freescale semiconductor 10-3 10.1 introduction this chapter describes the serial communications interface (sci) module. the module allows asynchronous serial communications with peripheral devices and other digital signal controllers (dscs). 10.2 features ? full-duplex or single wire operation ? standard mark/space non-return-to-zero (nrz) format ? thirteen-bit baud rate selection ? programmable 8- or 9-bit data format ? separately enabled transmitter and receiver ? separate receiver and transmitter cpu interrupt requests ? programmable polarity for transmitter and receiver ? two receiver wake up methods: ? idle line ? address mark ? interrupt-driven operation with seven flags: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? noise error ? framing error ? parity error ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection block diagram 5685x digital signal controller user manual, rev. 4 10-4 freescale semiconductor 10.3 block diagram figure 10-1. sci block diagram 10.4 external pin descriptions 10.4.1 transmit data (txd) pin the transmit data (txd) pin is the sci transmitter pin. txd is available for general- purpose i/o when it is not configured for transmitter operation, such as te = 0. 10.4.2 receiver data (rxd) pin the receiver data (rxd) pin is the sci receiver pin. rxd is available for general- purpose i/o when it is not configured for receiver operation, such as re = 0. data in table 10-1 are external i/o signals for the chip interface. table 10-1. external i/o signals signal name i/o type description reset state txd output transmit data pin 1 rxd input receiver data pin ? sci data receive shift register sci data register transmit shift register register baud rate generator sbr12?sbr0 rxd txd module transmit control 16 receive and wake up data format control control pf fe nf or rerr rdrf tiie tidle ridle raf loop rwu re pe pol pt wake m clock rerr reie tidle interrupt interrupt pin rsrc sbk loop te rsrc request request riie ridle interrupt request teie tdre tdre interrupt request tde request tdma rdma rfie request rdrf/or interrupt request rdme pin module memory maps serial communications interface (sci), rev. 4 freescale semiconductor 10-5 10.5 module memory maps the five accessible registers on the sci0 are listed in table 10-2 while the five accessible registers on the sci1 are listed in table 10-3 . table 10-2. sci0 module memory map (sci0_base = $1fffe0) address offset register acronym register name access type chapter location base + $0 sci_0_br sci baud rate register read/write section 10.9.1 base + $1 sci_0_cr sci control register read/write section 10.9.2 base + $2 sci_0_cr2 sci control register 2 read/write section 10.9.3 base + $3 sci_0_sr sci status register read only section 10.9.4 base + $4 sci_0_dr sci data register read/write section 10.9.5 table 10-3. sci1 module memory map (sci1_base = $1ffdf8) address offset register acronym register name access type chapter location base + $0 sci_1_br sci baud rate register read/write section 10.9.1 base + $1 sci_1_cr sci control register read/write section 10.9.2 base + $2 sci_1_cr2 sci control register 2 read/write section 10.9.3 base + $3 sci_1_sr sci status register read only section 10.9.4 base + $4 sci_1_dr sci data register read/write section 10.9.5 add. offset register name 151413121110987654321 0 $0 scibr r 0 0 0 sbr w $1 scicr r loop swai rsrc m wake pol pe pt teie tiie rfie reie te re rwu sbk w $2 scicr2 r 0 0 0 0 0 0 0 0 0 0 0 0 0 riie tde rde w $3 scisr r tdre tidle rdrf ridle or nf fe pf 0 0 0 0 0 0 0 raf w $4 scidr r 0 0 0 0 0 0 0 receive data w transmit data r 0 read as 0 w reserved figure 10-2. sci register map summary functional description 5685x digital signal controller user manual, rev. 4 10-6 freescale semiconductor 10.6 functional description figure 10-1 explains the structure of the sci module. the sci allows full duplex, asynchronous, nrz serial communication between the dsc and remote devices, including other digital signal controllers. the sci transmitter and receiver operate independently, although they use the same baud rate generator. the monitors the status of the sci, writes the data to be transmitted, and processes received data. when initializing the sci, be sure to set the proper peripheral enable bits in the gpio registers as well as any pull-up enables. 10.6.1 data frame format the sci uses the standard non-return-to-zero (nrz) mark/space data frame format illustrated in figure 10-3 . figure 10-3. sci data frame formats each data character is contained in a frame including a start bit, eight or nine data bits, and a stop bit. clearing the m bit in the sci control register (scicr) configures the sci for 8-bit data characters. a frame with eight data bits has a total of 10 bits. setting the m bit configures the sci for 9-bit data characters. a frame with nine data bits has a total of 11 bits. table 10-4. example 8-bit data frame formats start bit data bits address bit parity bit stop bit 18001 17011 171 1 1. the address bit identifies the frame as an address character. please see section 10.6.4.8 01 bit 5 start bit bit 0 bit 1 next stop bit start bit 9-bit data format bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit bit m in scicr set 8-bit data format bit m in scicr clear bit 5 bit 0 bit 1 bit 2 bit 3 bit 4 bit 6 bit 7 bit 8 stop bit next start bit start bit functional description serial communications interface (sci), rev. 4 freescale semiconductor 10-7 10.6.2 baud rate generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. a value of 1 to 8191 written to the sbr bits determines the module clock divisor. a value of zero disables the baud rate generator. the sbr bits are bits 12:0 of the sci baud rate (scibr) register. the baud rate clock is synchronized with the bus clock, driving the receiver. the baud rate clock, divided by 16, drives the transmitter. the receiver has an acquisition rate of 16 samples per bit time. baud rate generation is subject to two sources of error: 1. integer division of the module clock may not give the exact target frequency. 2. synchronization with the bus clock can cause phase shift. table 10-6 lists examples of achieving target baud rates with a module clock frequency of 60mhz. note: maximum baud rate is module clock rate, divided by 16. system overhead may preclude processing the data at this speed. table 10-5. example 9-bit data frame formats start bit data bits address bit parity bit stop bit 19001 18002 18011 181 1 01 1. the address bit identifies t he frame as an address character. please see section 10.6.4.8 table 10-6. example baud rates (module clock = 60mhz) sbr bits receiver clock (hz) transmitter clock (hz) target baud rate error (%) 98 612245 38265 38,400 -0.35 195 307692 19231 19,200 0.16 391 153453 9591 9600 -0.09 781 76825 4802 4800 0.04 1563 38388 2399 2400 -0.04 3125 19200 1200 1200 0.00 6250 9600 600 600 0.00 functional description 5685x digital signal controller user manual, rev. 4 10-8 freescale semiconductor 10.6.3 sci transmitter block diagram figure 10-4. sci transmitter block diagram 10.6.3.1 character length the sci transmitter can accommodate either 8- or 9-bit data characters. the state of the m bit in the sci control register (scicr) determines the length of data characters. 10.6.3.2 character transmission during an sci transmission, the transmit shift register shifts a frame out to the txd pin. the data is written through the sci data register. to initiate an sci transmission: 1. enable the transmitter by writing a logic 1 to the transmitter enable (te) bit in the sci control register (scicr). pe pt h876543210l 11-bit transmit shift register stop start tidle tiie teie sbk tdre parity generation msb sci data register load from scidr shift enable preamble (all ones) break (all 0s) transmitter control m internal bus sbr12?sbr0 baud divider 16 txd tidle interrupt request tdre interrupt request module loop loop rsrc clock te to control receiver pol tde tdma request functional description serial communications interface (sci), rev. 4 freescale semiconductor 10-9 2. clear the transmit data register empty (tdre) flag by first reading the sci status register (scisr) and then writing output data to the sci data register (scidr). 3. repeat step 2 for each subsequent transmission. modifying the te bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if m = 0) or 11 logic 1s (if m = 1). after the preamble shifts out, control logic automatically transfers the data from the sci data register into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position of the frame. hardware supports odd or even parity. when parity is enabled, the most significant bit (msb) of the data character is replaced by the parity bit. the transmit data register empty (tdre) flag in the sci status register (scisr) becomes set when the sci data register transfers a character to the transmit shift register. the tdre flag indicates when the sci data register can accept new data from the internal data bus. if the transmitter empty interrupt enable (teie) bit in the sci control register (scicr) is also set, the tdre flag generates a transmitter interrupt request. if tde is enabled, the dma request will suppress the tdre interrupt and a dma request will be made instead. when the transmit shift register is not transmitting a frame and te = 1, the txd pin goes to the idle condition, logic 1. if, at any time, software clears the te bit in the sci control register (scicr), the transmitter relinquishes control of the port i/o pin upon completion of the current transmission causing the txd pin to go to a highz state. if software clears te while a transmission is in progress (tidle = 0), the frame in the transmit shift register continues to shift out. then transmission stops even if there is data pending in the sci data register. to avoid accidentally cutting off the last frame in a message, always wait for tdre to go high after the last frame before clearing te. to separate messages with preambles with minimum idle line time, use this sequence between messages: 1. write the last character of the first message to the scidr. 2. wait for the tdre flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the te bit. 4. write the first character of the second message to the scidr. functional description 5685x digital signal controller user manual, rev. 4 10-10 freescale semiconductor 10.6.3.3 break characters writing a logic 1 to the send break bit sbk in the sci control register (scicr) loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in the sci control register (scicr). as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of the last break character guarantees the recognition of the start bit of the next frame. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: ? sets the framing error (fe) flag ? sets the receive data register full (rdrf) flag ? clears the sci data register (scidr) ? may set the overrun (or) flag, noise flag (nf), parity error (pe) flag, or the receiver active flag (raf). please see the sci status register in section 10.9.4 . 10.6.3.4 preambles a preamble contains all logic 1s and has no start, stop, or parity bit. a preamble length depends on the m bit in the sci control register (scicr). the preamble is a synchronizing mechanism initiating the first transmission begun after modifying the te bit from 0 to 1. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues a preamble to be sent after the frame currently being transmitted. note: toggle the te bit for a queued preamble when the tdre flag becomes set and immediately before writing the next character to the sci data register. when queueing a preamble, return the te bit to logic 1 before the stop bit of the current frame shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the sci data register to be lost. 10.6.3.5 receiver figure 10-5 explains the block diagram of the sci receiver with detailed discussion of the receiver function in the following paragraphs. functional description serial communications interface (sci), rev. 4 freescale semiconductor 10-11 10.6.4 sci receiver block diagram figure 10-5. sci receiver block diagram 10.6.4.1 character length the sci receiver can accommodate either 8- or 9-bit data characters. the state of the m bit in the sci control register (scicr) determines the length of data characters. 10.6.4.2 character reception during an sci reception, the receive shift register shifts a frame in from the rxd pin. the data is read from the sci data register (scidr). after a complete frame shifts into the receive shift register, the data portion of the frame transfers to the sci data register. the receive data register full (rdrf) flag in the sci status register (scisr) becomes set, indicating the received character can be read. if the receive full interrupt enable (rfie) bit in the sci control register (scicr) is also set, the rdrf flag generates an rdrf interrupt request. if rde is set, the rdrf interrupt is suppressed and a receive dma request is generated instead. all ones m wake pe pt re h876543210l 11-bit receive shift register stop start data wake up parity checking msb sci data register rfie reie rwu rdrf or nf fe pe internal bus rxd module rerr interrupt request rdrf/or interrupt request sbr12?sbr0 baud divider loop loop rsrc from txd pin or transmitter clock rerr raf recovery control logic pol rde receiver dma request riie ridle ridle interrupt request functional description 5685x digital signal controller user manual, rev. 4 10-12 freescale semiconductor 10.6.4.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock illustrated in figure 10-6 is resynchronized: ? after every start bit ? after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 10-6. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 10-7 summarizes the results of the start bit verification samples. if the start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. table 10-7. start bit verification rt8, rt9, and rt10 samples data bit determination noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 samples rt clock rt clock count start bit rxd start bit qualification start bit data sampling 11 1 1 1 1 110000 0 00 lsb verification functional description serial communications interface (sci), rev. 4 freescale semiconductor 10-13 if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 10-8 summarizes the results of the data bit samples. note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit (logic 0). to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 10-9 summarizes the results of the stop bit samples. figure 10-7 illustrates the verification samples rt3 and rt5 determine the first low detected was noise and not the beginning of a start bit. the rt clock is reset and the start bit search begins again. the noise flag is not set because the noise occurred before the start bit was found. table 10-8. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 10-9. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 functional description 5685x digital signal controller user manual, rev. 4 10-14 freescale semiconductor figure 10-7. start bit search example 1 figure 10-8 shows noise is perceived as the beginning of a start bit although the verification sample at rt3 is high. the rt3 sample sets the noise flag. although the perceived bit time is misaligned, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 10-8. start bit search example 2 figure 10-9 illustrates a large burst of noise is perceived as the beginning of a start bit, although the test sample at rt5 is high. the rt5 sample sets the noise flag. although this is a worst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 0 1 111000 00 lsb 0 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt11 rt10 rt9 rt14 rt13 rt12 rt2 rt1 rt16 rt15 rt3 rt4 rt5 rt6 rt7 samples rt clock rt clock count actual start bit rxd 11 1 1 11000 0 lsb 0 0 perceived start bit functional description serial communications interface (sci), rev. 4 freescale semiconductor 10-15 figure 10-9. start bit search example 3 figure 10-10 illustrates the effect of noise early in the start bit time. although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. figure 10-10. start bit search example 4 figure 10-11 demonstrates a burst of noise near the beginning of the start bit that resets the rt clock. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt13 rt12 rt11 rt16 rt15 rt14 rt4 rt3 rt2 rt1 rt5 rt6 rt7 rt8 rt9 samples rt clock rt clock count actual start bit rxd 10 1 11000 0 lsb 0 perceived start bit reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count perceived and actual start bit rxd 11 1 1100 1 lsb 1 1 1 1 functional description 5685x digital signal controller user manual, rev. 4 10-16 freescale semiconductor figure 10-11. start bit search example 5 figure 10-12 shows a noise burst makes the majority of data samples rt8, rt9, and rt10 high. this sets the noise flag but does not reset the rt clock. in start bits only, the rt8, rt9, and rt10 data samples are ignored. figure 10-12. start bit search example 6 10.6.4.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error (fe) flag in the sci status register (scisr). a break character also sets the fe flag because a break character has no stop bit. the fe flag is set at the same time as the rdrf flag. the fe flag inhibits further data reception until it is cleared. reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 samples rt clock rt clock count start bit rxd 11 1 1101 0 lsb 1 1 1 1 1 00 0 00 0 0 0 no start bit found reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 1 1100 0 lsb 1 1 1 1 0 11 0 functional description serial communications interface (sci), rev. 4 freescale semiconductor 10-17 10.6.4.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming frame, it resynchronizes the rt clock on any valid falling edge within the frame. re-synchronization within frames corrects misalignments between transmitter bit times and receiver bit times. 10.6.4.6 slow data tolerance figure 10-13 explains how much a slow received frame can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1, it arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 10-13. slow data for an 8-bit data character, data sampling of the stop bit takes the receiver 9-bit 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 10-13 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9-bit 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: for a 9-bit data character, data sampling of the stop bit takes the receiver 10-bit 16 rt cycles + 10 rt cycles = 170 rt cycles. msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 154 147 ? 154 ----------------------- - 100 4.54% = functional description 5685x digital signal controller user manual, rev. 4 10-18 freescale semiconductor with the misaligned character, shown in figure 10-13 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is10 bit 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: 10.6.4.7 fast data tolerance figure 10-14 demonstrates how much a fast received frame can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but it is still sampled at rt8, rt9, and rt10. figure 10-14. fast data for an 8-bit data character, data sampling of the stop bit takes the receiver 9-bit 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 10-14 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: for a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 10-14 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit 16 rt cycles = 176 rt cycles. 170 163 ? 170 ----------------------- - 100 4.12% = idle or next frame stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ----------------------- - 100 3.90% = functional description serial communications interface (sci), rev. 4 freescale semiconductor 10-19 the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 10.6.4.8 receiver wake up in order for the sci to ignore transmissions intended only for other receivers in multiple- receiver systems, the receiver can be placed into a standby state. setting the receiver wake up (rwu) bit in the sci control register (scicr) places the receiver into a standby state while receiver interrupts are disabled. the transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. the wake bit in the sci control register (scicr) determines how the sci is brought out of the standby state to process an incoming message. the wake bit enables either idle line wake up or address mark wake up: ? idle input line wake up (wake = 0)?in this wake up method, an idle condition on the rxd pin clears the rwu bit and wakes up the sci. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which the message is addressed process the following frames. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another preamble appears on the rxd pin. idle line wake up requires messages be separated by at least one preamble and no message contains preambles. the preamble waking a receiver does not set the receiver idle (idle) bit or the receive data register full (rdrf) flag. ? address mark wake up (wake = 1)?in this wake up method, a logic 1 in the most significant bit (msb) position of a frame clears the rwu bit and wakes up the sci. the logic 1 in the msb position marks a frame as an address frame, containing the addressing information. all receivers evaluate the addressing information as well as the receivers for which the message is addressed in the following frames. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another address frame appears on the rxd pin. the logic 1 msb of an address frame clears the receiver?s rwu bit before the stop bit is received, setting the rdrf flag. 170 176 ? 170 ----------------------- - 100 3.53% = functional description 5685x digital signal controller user manual, rev. 4 10-20 freescale semiconductor address mark wake up allows messages to contain preambles but it requires the msb to be reserved for use in address frames. note: with the wake bit clear, setting the rwu bit after the rxd pin has been idle can cause the receiver to wake up immediately. 10.6.5 single wire operation normally, the sci uses two pins for transmitting and receiving. in the single wire operation, the rxd pin is disconnected from the sci and is available as a general purpose i/o (gpio) pin. the sci uses the txd pin for both receiving and transmitting. setting the te bit in the sci control register (scicr) configures txd as the output for transmitted data. clearing the te bit configures txd as the input for received data. figure 10-15. single wire operation (loop = 1, rsrc = 1) enable single wire operation by setting the loop bit and the receiver source (rsrc) bit in the sci control register (scicr). setting the loop bit disables the path from the rxd pin to the receiver. setting the rsrc bit connects the receiver input to the output of the txd pin driver. 10.6.6 loop operation in loop operation the transmitter output goes to the receiver input. the rxd pin is disconnected from the sci and is available as a gpio pin. setting the te bit in the sci control register (scicr) connects the transmitter output to the txd pin. clearing the te bit disconnects the transmitter output from the txd pin. figure 10-16. loop operation (loop = 1, rsrc = 0) txd rxd transmitter receiver te general purpose i/o txd rxd te general purpose i/o transmitter receiver dma operation serial communications interface (sci), rev. 4 freescale semiconductor 10-21 enable loop operation by setting the loop bit and clearing the rsrc bit in the sci control register (scicr). setting the loop bit disables the path from the rxd pin to the receiver. clearing the rsrc bit connects the transmitter output to the receiver input. both the transmitter and receiver must be enabled (te = 1 and re = 1). 10.7 dma operation 10.7.1 transmit dma operation setting the tde bit in scicr2 enables transmit dma mode. in this mode, the transmitter empty interrupt is suppressed, allowing a transmitter dma request to be generated. the dma controller can be configured to write to the scidr, clearing the tdre and the dma request. 10.7.2 receive dma operation setting the rde bit in scicr2 enables receiver dma mode. in this mode, the receiver full interrupt is suppressed, allowing a receiver dma request to be generated. the dma controller can then be configured to read to the scidr, clearing the interrupt. 10.7.3 receiver wake up with dma if dma operation is desired during either of the wake up modes of operation, dma requests should only be made for a message addressed to the receiver. for example, wake up operation proceeds normally until a desired receive message is identified. then dma requests are generated to buffer the remainder of the message. an example of the dma receive operations is provided in appendix 10-10, ?receiver wake up with dma.? . table 10-10. receiver wake up with dma 1. configure the sci for standard receive operation 2. sci receives the first frame of the inco ming message and stores it in the scidr 3. a sci receiver full interrupt occurs 4. the isr looks at the message address information and determines: message not for us message is for us 5. configure sci for rwu mode and wait for the end of the message. repeat from setup 1. 5. enable dma operation with a buffer large enough to accommodate the max message size. 6. enable riie so the sci will interrupt at the completion of the message. (assumes the dma buffer does not fill up first.) 7. when the rii interrupt occurs, process the message and return to setup 1. low power modes 5685x digital signal controller user manual, rev. 4 10-22 freescale semiconductor 10.8 low power modes 10.8.1 run mode clearing the transmitter enable (te) or receiver enable (re) bits in the sci control register (scicr) reduces power consumption in the run mode. sci registers are still accessible when te or re is cleared, but clocks to the core of the sci are disabled. 10.8.2 wait mode sci operation in the wait mode depends on the state of the swai bit in the sci control register (scicr). ? if the swai bit is clear, the sci operates normally when the central processing unit (cpu) is in the wait mode. ? if the swai bit is set, sci clock generation ceases and the sci module enters a power-conservation state when the cpu is in the wait mode. in this condition, sci registers are not accessible. setting swai does not affect the state of the receiver enable (re) bit or the transmitter enable (te) bit. if the swai bit is set, any transmission or reception in progress stops at the wait mode entry. the transmission or reception resumes when either an internal or external interrupt brings the digital signal controller out of the wait mode. exiting the wait mode by reset aborts any transmission or reception in progress and resets the sci. 10.8.3 stop mode the sci is inactive in the stop mode for reduced power consumption. the stop instruction does not affect sci register states. sci operation resumes after an external interrupt brings the cpu out of the stop mode. exiting the stop mode by reset aborts any transmission or reception in progress and resets the sci. 10.8.4 wait mode recovery any enabled sci interrupt request can bring the cpu out of the wait mode. sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) serial communications interface (sci), rev. 4 freescale semiconductor 10-23 10.9 sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) 10.9.1 sci baud rate (scibr) this register can be read at anytime. bits 12 through zero can be written at any time, but bits 15 through 13 are reserved and can be modified only in special modes. figure 10-17. sci baud rate register (scibr) see programmer?s sheet on appendix page b-53 the count in this register determines the baud rate of the sci. the formula for calculating baud rate is: sbr = contents of the baud rate registers, a value of 1 to 8191 note: the baud rate generator is disabled until the te or the re bits are set for the first time after reset. the baud rate generator is disabled when sbr = 0. 10.9.2 sci control register (scicr) the sci control register can be read/written at anytime. figure 10-18. sci control register (scicr) see programmer?s sheets on appendix page b-54 base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 sbr write reset 0000 0 00000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read loop swai rsrc m wake pol pe pt teie tiie rfie reie te re rwu sbk write reset 0000 0 00000000000 sci baud rate = sci module clock 16 sbr sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) 5685x digital signal controller user manual, rev. 4 10-24 freescale semiconductor 10.9.2.1 loop select bit (loop)?bit 15 this bit enables loop operation. loop operation disconnects the rxd pin from the sci and the transmitter output goes into the receiver input. both the transmitter and receiver must be enabled to use the internal loop function as opposed to single wire operation, requiring only one or the other to be enabled. please see table 10-11 . ? 0 = normal operation enabled ? 1 = loop operation enabled the receiver input is determined by the rsrc bit. the transmitter output is controlled by the te bit. if the te bit is set and loop = 1, the transmitter output appears on the txd pin. if the te bit is clear and loop = 1, the txd pin is high-impedance. 10.9.2.2 stop in wait mode (swai)?bit 14 this bit disables the sci in the wait mode. ? 0 = sci enabled in wait mode ? 1 = sci disabled in wait mode 10.9.2.3 receiver source (rsrc)? bit 13 when loop = 1, the rsrc bit determines the internal feedback path for the receiver. ? 0 = receiver input internally connected to transmitter output ? 1 = receiver input connected to txd pin 10.9.2.4 data format mode (m)?bit 12 this bit determines whether data characters are eight or nine bits long. ? 0 = one start bit, eight data bits, one stop bit ? 1 = one start bit, nine data bits, one stop bit table 10-11. loop functions loop rsrc function 0x normal operation 1 0 loop mode with internal txd fed back to rxd 1 1 single-wire mode with txd output fed back to rxd sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) serial communications interface (sci), rev. 4 freescale semiconductor 10-25 10.9.2.5 wake up condition (wake)?bit 11 this bit determines which condition wakes up the sci: a logic 1 (address mark) in the msb position of a received data character or an idle condition on the rxd pin. ? 0 = idle line wake up ? 1 = address mark wake up 10.9.2.6 polarity (pol)?bit 10 this bit determines whether to invert the data as it goes from the transmitter to the txd pin and from the rxd pin to the receiver. all bits, start, data, and stop, will be inverted as they leave the transmit shift register and before they enter the receive shift register. ? 0 = doesn?t invert transmit and receive data bits (normal mode) ? 1 = invert transmit and receive data bits (inverted mode) note: it is recommended the pol bit be toggled only when both te and re = 0. 10.9.2.7 parity enable (pe)?bit 9 this bit enables the parity function. when enabled, the parity function replaces the msb of the data character with a parity bit. ? 0 = parity function disabled ? 1 = parity function enabled 10.9.2.8 parity type (pt)?bit 8 this bit determines whether the sci generates and checks for even parity or odd parity of the data bits. with even parity, an even number of ones, clears the parity bit. an odd number of ones sets the parity bit. with odd parity, an odd number of ones, clears the parity bit and an even number of ones sets the parity bit. ? 0 = even parity ? 1 = odd parity 10.9.2.9 transmitter empty interrupt enable (teie)?bit 7 this bit enables the transmit data register empty (tdre) flag to generate interrupt requests. ? 0 = tdre interrupt requests disabled ? 1 = tdre interrupt requests enabled sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) 5685x digital signal controller user manual, rev. 4 10-26 freescale semiconductor 10.9.2.10 transmitter idle interrupt enable (tiie)?bit 6 this bit enables the transmitter idle (tidle) flag to generate interrupt requests. ? 0 = tidle interrupt requests disabled ? 1 = tidle interrupt requests enabled 10.9.2.11 receiver full interrupt enable (rfie)?bit 5 this bit enables the receive data register full (rdrf) flag, or the overrun (or) flag to generate interrupt requests. ? 0 = rdrf and or interrupt requests disabled ? 1 = rdrf and or interrupt requests enabled 10.9.2.12 receive error interrupt enable (reie)?bit 4 this bit enables the receive error (re) flags (nf, pf, fe, and or) to generate interrupt requests. ? 0 = error interrupt requests disabled ? 1 = error interrupt requests enabled 10.9.2.13 transmitter enable (te)?bit 3 this bit enables the sci transmitter and configures the txd pin as the sci transmitter output. the te bit can be used to queue an idle preamble. ? 0 = transmitter disabled ? 1 = transmitter enabled 10.9.2.14 receiver enable (re)?bit 2 this bit enables the sci receiver. ? 0 = receiver disabled ? 1 = receiver enabled 10.9.2.15 receiver wake up (rwu)?bit 1 this bit enables the wake up function, inhibiting further receiver interrupt requests. normally, hardware wakes the receiver by automatically clearing the rwu. please refer to section 10.6.4.8 for a description of receive wake up. ? 0 = normal operation ? 1 = standby state sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) serial communications interface (sci), rev. 4 freescale semiconductor 10-27 10.9.2.16 send break (sbk)?bit 0 toggling sbk sends one break character (10 or 11 logic 0s). as long as sbk is set, the transmitter sends logic 0s. ? 0 = no break characters ? 1 = transmit break characters 10.9.3 sci control register 2 (scicr2) this register can be read/written at anytime. figure 10-19. sci control register 2 (scicr2) see programmer?s sheets on appendix page b-57 10.9.3.1 reserved?bits 15?3 these bits are reserved or not implemented. they are read as 0, but cannot be modified by writing. 10.9.3.2 receiver idle interrupt enable (riie)?bit 2 this read/write riie bit is used to let the processor know a message has completed when using dma in a wake up mode of operation. the receiver is configured normally until a message is detected. the processor code then determines if the message is for it. if so, dma is enabled for the maximum message size, and the riie interrupt is enabled to tell the core when the message has completed. the receive dma operation would be halted by the interrupt service routine at this time. 10.9.3.3 transmitter dma enable (tde)?bit 1 tde enables dma mode transfer of data from the scidr. for transmit dma operation, this bit must be set and a dma channel must be configured to utilize the request. ? 0 = transmit dma disabled ? 1 = transmit dma enabled base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 riie tde rde write reset 0000000000000000 sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) 5685x digital signal controller user manual, rev. 4 10-28 freescale semiconductor 10.9.3.4 receiver dma enable (rde)?bit 0 rde enables dma mode transfer of data to the scidr. for receive dma operation, this bit must be set and a dma channel must be configured to utilized the request. ? 0 = receive dma disabled ? 1 = receive dma enabled 10.9.4 sci status register (scisr) this register can be read at anytime; however, it cannot be modified by writing. writes clear flags. figure 10-20. sci status register (scisr) see programmer?s sheets on appendix page b-58 10.9.4.1 transmit data register empty flag (tdre)?bit 15 this bit is set when the transmit shift register receives a character from the sci data register (scidr). clear tdre by reading scisr with tdre set and then writing to the sci data register in normal mode or by writing the scidr with tde set. ? 0 = no character transferred to transmit shift register ? 1 = character transferred to transmit shift register; transmit data register empty 10.9.4.2 transmitter idle flag (tidle)?bit 14 this bit is set when the tdre flag is set and no data, preamble, or break character is being transmitted. when tidle is set, the txd pin becomes idle (logic 1). clear tidle by reading the sci status register (scisr) with tidle set and then writing to the sci data register (scidr). tidle is not generated when a data character, a preamble, or a break is queued and ready to be sent. ? 0 = transmission in progress ? 1 = no transmission in progress base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tdre tidle rdrf ridle or nf fe pf 0 0 0 0 0 0 0 raf write reset 000 0 000000000000 sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) serial communications interface (sci), rev. 4 freescale semiconductor 10-29 10.9.4.3 receive data register full flag (rdrf)?bit 13 this bit is set when the data in the receive shift register transfers to the sci data register (scidr). clear rdrf by reading the sci status register (scisr) with rdrf set and then reading the sci data register in normal mode or by reading the scidr with rde set. ? 0 = data not available in sci data register ? 1 = received data available in sci data register 10.9.4.4 receiver idle line flag (ridle)?bit 12 this bit is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. once the ridle flag is cleared (the receiver detects a logic 0), a valid frame must again set the rdrf flag before an idle condition can set the ridle flag. ? 0 = receiver input is either active now or has never become active since the ridle flag was last cleared ? 1 = receiver input has become idle (after receiving a valid fame) note: when the receiver wake up (rwu) bit is set, an idle line condition does not set the ridle flag. 10.9.4.5 overrun flag (or)?bit 11 this bit is set when software fails to read the sci data register (scidr) before the receive shift register receives the next frame. the data in the shift register is lost, but the data already in the sci data register is not affected. clear or by reading the sci status register (scisr) with or set, then write the scisr with any value. ? 0 = no overrun ? 1 = overrun 10.9.4.6 noise flag (nf)?bit 10 this bit is set when the sci detects noise on the receiver input. the nf bit is set during the same cycle as the rdrf flag, but it is not set in the case of an overrun. clear nf by reading the scisr then write the sci status register with any value. ? 0 = no noise ?1 = noise sci register descriptions (sci0_base = $1fffe0 and sci1_base = $1ffdf8) 5685x digital signal controller user manual, rev. 4 10-30 freescale semiconductor 10.9.4.7 framing error flag (fe)?bit 9 this bit is set when a logic 0 is accepted as the stop bit. fe bit is set during the same cycle as the rdrf flag but it is not set in the case of an overrun. fe inhibits further data reception until it is cleared. clear fe by reading the scisr with fe set, then write the scisr with any value. ? 0 = no framing error ? 1 = framing error 10.9.4.8 parity error flag (pf)?bit 8 this bit is set when the parity enable (pe) bit is set and the parity of the received data does not match its parity bit. clear pf by reading the scisr then write the scisr with any value. ? 0 = no parity error ? 1 = parity error 10.9.4.9 reserved?bits 7?1 these bits are reserved or not implemented. they are read as 0, but cannot be modified by writing. 10.9.4.10 receiver active flag (raf)?bit 0 this bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. raf is cleared when the receiver detects false start bits (usually from noise or baud rate mismatch) or when the receiver detects a preamble. ? 0 = no reception in progress ? 1 = reception in progress resets serial communications interface (sci), rev. 4 freescale semiconductor 10-31 10.9.5 sci data register (scidr) the sci data register (scidr) can be read and modified at any time. reading accesses sci receive data register (srdr). writing to the register accesses sci transmit data register (stdr). figure 10-21. sci data register (scidr) see programmer?s sheets on appendix page b-61 10.9.5.1 reserved?bits 15?9 these bits are reserved or not implemented. they are read and written as 0. 10.9.5.2 receive data?bits 8?0 data received. 10.9.5.3 transmit data?bits 8?0 data to be transmitted. 10.10 clocks all timing is derived from the ipbus clock at half of the system clock for this module. please see section 10.6.2 for a description of how the data rate is determined. 10.11 resets reset characteristics are determined by the state of control register bit settings. therefore, the register descriptions comprising section 10.9 cover all reset functions. base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 receive data write transmit data reset 000 0 000000000000 interrupts 5685x digital signal controller user manual, rev. 4 10-32 freescale semiconductor 10.12 interrupts 10.12.1 transmitter empty interrupt this interrupt is enabled by setting the teie bit of the scicr. when this interrupt is enabled an interrupt is generated when data is transferred from the sci data register to the transmit shift register. the interrupt service routine should read the scisr and verify the tdre bit is set, and then write the next data to be transmitted to the scidr, clearing the tdre bit. 10.12.2 transmitter idle interrupt this interrupt is enabled by setting the tiie bit of the scicr. this interrupt indicates the tdre flag is set and the transmitter is no longer sending data, preamble, or break characters. the interrupt service routine should read the scisr, verifying the tidle bit is set, then initiate a preamble, break, or write a data character to the scidr. any of these actions will clear the tidle bit because the transmitter is busy at that time. 10.12.3 receiver full interrupt this interrupt is enabled by setting the rie bit of the scicr. this interrupt indicates the receive data is available in the scidr. the interrupt service routine should read the scisr, verifying the rdrf bit is set, then read the data from the scisr. this will clear the rdrf bit. 10.12.4 receive error interrupt this interrupt is enabled by setting the reie bit of the scicr. this interrupt indicates any of the listed errors were detected by the receiver: 1. noise flag (nf) set 2. parity error flag (pf) set table 10-12. sci interrupt sources interrupt source flag local enable transmitter tdre teie transmitter tidle tiie receiver rdrf rfie or receiver fe reie pe nf or receiver ridle riie interrupts serial communications interface (sci), rev. 4 freescale semiconductor 10-33 3. framing error (fe) flag set 4. overrun (or) flag set the interrupt service routine should read the scisr to determine which of the error flags was set. the error flag is set by writing (anything) to the scisr. the appropriate action should then be taken by the software to handle the error condition. 10.12.5 receiver idle interrupt this interrupt is used in conjunction with receive dma operation. please see the riie bit description in section 10.7.3 and section 10.9.3 for a description of the intended operation of this interrupt. when this interrupt occurs the appropriate response of the interrupt service routine would be to disable the riie until the next message receive sequence occurs. interrupts 5685x digital signal controller user manual, rev. 4 10-34 freescale semiconductor serial peripheral interface (spi), rev. 4 freescale semiconductor 11-1 chapter 11 serial peripheral interface (spi) 5685x digital signal controller user manual, rev. 4 11-2 freescale semiconductor features serial peripheral interface (spi), rev. 4 freescale semiconductor 11-3 11.1 introduction this section describes the serial peripheral interface (spi) module available on each chip, with the exception for the 56855. the module allows full-duplex, synchronous, serial communication between the digital signal controllers (dsc) and peripheral devices, including other dscs. software can poll spi status flags or spi operation can be interrupt driven. this block contains four 16-bit memory mapped registers for control parameters, status, and data transfer. 11.2 features features of the spi module include: ? full-duplex operation ? master and slave modes ? double-buffered operation with separate transmit and receive registers ? programmable length transmissions (2 to 16 bits) ? programmable transmit and receive shift order (msb first or last bit transmitted) ? eight master mode frequencies (maximum = bus frequency/2 1 ) ? maximum slave mode frequency = bus frequency ? clock ground for reduced radio frequency (rf) interference ? serial clock with programmable polarity and phase ? two separately enabled interrupts ? sprf (spi receiver full) ? spte (spi transmitter empty) ? mode fault error flag with interrupt capability ? direct memory access (dma) capability for both the transmitter and receiver ? wired or mode functionality to enabling connection to multiple spis ? overflow error flag with interrupt capability 1. this frequency may be further limited by the gpio function. spi block diagram 5685x digital signal controller user manual, rev. 4 11-4 freescale semiconductor 11.3 spi block diagram figure 11-1. spi block diagram spr1 spmstr transmit data register shift register spr0 clk clock select 2 clock divider 8 16 32 clock logic cpha cpol spi sprie dso spe sprf spte ovrf m s pin control logic receive data register sptie spe ipbus peripheral bus (from ipbus) modfen errie control modf spmstr mosi miso sclk ss 2?16 bits ds[3:0] spi transmit dma request spi transmit dsc interrupt request received/error dsc interrupt request spi receive dma request tx_req rx/eer req tdmaen rdmaen signal descriptions serial peripheral interface (spi), rev. 4 freescale semiconductor 11-5 11.4 signal descriptions 11.4.1 master in/slave out (miso) miso is one of the two spi module pins to transmit serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only when the spi is configured as a slave. the spi is configured as a slave when the spmstr bit, illustrated in table 11-4 , is logic 0 and its ss pin is at logic 0. to support a multiple slave system, a logic 1 on the ss pin puts the miso pin in a high impedance state. 11.4.2 master out/slave in (mosi) mosi is one of the two spi module pins to transmit serial data. in full duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. 11.4.3 serial clock (sclk) the serial clock synchronizes data transmission between master and slave devices. in a master dsc, the sclk pin is the clock output. in a slave dsc, the sclk pin is the clock input. in full duplex operation, the master and slave exchange data in the same number of clock cycles as the number of bits of transmitted data. 11.4.4 slave select (ss ) the ss pin has various functions depending on the current state of the spi. for a spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. since it is used to indicate the start of a transmission, the ss must be toggled high and low between each full length data transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. please refer to figure 11-2 . figure 11-2. cpha/ss timing data 1 data 3 miso/mosi data 2 master ss slave ss (cpha = 0) slave ss (cpha = 1) external i/o signals 5685x digital signal controller user manual, rev. 4 11-6 freescale semiconductor when an spi is configured as a slave, the ss pin is always configured as an input. the modfen bit can prevent the state of the ss from creating a modf error. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming sclk clocks, even if it was already in the middle of a transmission. a mode fault will occur if the ss pin changes state during a transmission. when a spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and sclk. for the state of the ss pin to set the modf flag, the modfen bit in the sclk register must be set. 11.5 external i/o signals there are four external spi pins. all are summarized in table 11-2 . table 11-1. spi i/o configuration spe spmstr modfen spi configuration state of ss logic 0 x 1 1. x = don?t care x not enabled ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf ss ignored by spi 1 1 1 master with modf input-only to spi table 11-2. external i/o signals signal name description direction mosi master-out slave-in pad pin bi-directional miso master-in slave-out pad pin bi-directional sclk slack clock pad pin bi-directional ss slave select pad pin (active low) input operating modes serial peripheral interface (spi), rev. 4 freescale semiconductor 11-7 11.6 operating modes the spi has two operating modes: ?master ? slave an operating mode is selected by the spmstr bit in the spscr as follows: ? spmstr = 0 slave mode ? spmstr = 1 master mode note: the spmstr bit should be configured before enabling the spi, setting the spe bit in the spscr. the master spi should be enabled before enabling any slave spi. all slave spis should be disabled before disabling the master spi. 11.6.1 master mode the spi operates in master mode when the spi master bit, spmstr, is set. note: configure the spi module as master or slave before enabling the spi. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. only a master spi module can initiate transmissions. with the spi enabled, software begins the transmission from the master spi module by writing to the spi data transmit register (spdtr). if the shift register is empty, the data immediately transfers to the shift register, setting the spi transmitter empty (spte) bit. the data begins shifting out on the mosi pin under the control of the spi serial clock (sclk). the spr2, spr1 and spr0 bits in the spscr register, control the baud rate generator and determine the speed of the shift register. through the sclk pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the data shifts out on the mosi pin of the master, external data shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full (sprf) bit becomes set. at the same time the sprf becomes set the data from the slave transfer to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi data receive register (spdrr). writing to the spi data transmit register (spdtr) clears the spte bit. figure 11-3 is an example configuration for a full-duplex master-slave configuration. having the ss bit of the master dsc held high is only necessary if modfen = 1. tying the slave dsc ss bit to ground should only be executed if cpha = 1. operating modes 5685x digital signal controller user manual, rev. 4 11-8 freescale semiconductor figure 11-3. full-duplex master/slave connections 11.6.2 slave mode the spi operates in the slave mode when the spmstr bit is clear. while in the slave mode, the sclk pin is the input for the serial clock from the master dsc. before a data transmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low until the transmission is complete or a mode fault error occurs. note: the spi must be enabled (spe = 1) for slave transmissions to be received. note: data in the transmitter shift register will be unaffected by sclk transitions in the event the spi is operating as a slave but is deselected. in a slave spi module, data enters the shift register under the control of the serial clock (sclk) from the master spi module. after a full length data transmission enters the shift register of a slave spi, it transfers to the spi data receive register (spdrr) and the spi receiver full (sprf) bit in the spi status and control register (spscr) is set. if the receive data register (spdrr), and the sprf bit are set in the spscr, a receive interrupt is also generated. to prevent an overflow condition, slave software must read the spdrr before another full length data transmission enters the shift register. the maximum frequency of the sclk for a spi configured as a slave is the bus clock speed. the bus clock speed is twice as fast as the fastest master sclk potential generation. frequency of the sclk for an spi configured as a slave does not have to correspond to any particular spi baud rate. the baud rate only controls the speed of the sclk generated by an spi configured as a master. therefore, the frequency of the sclk for a spi configured as a slave can be any frequency less than, or equal to, the bus speed. shift register shift register baud rate generator master dsc slave dsc v dd mosi mosi miso miso sclk sclk ss ss operating modes serial peripheral interface (spi), rev. 4 freescale semiconductor 11-9 when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with new data for the next transmission by writing to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master begins the next transmission. otherwise, the data already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the cpha bit is set, the first edge of sclk starts a transmission. when cpha is cleared, the falling edge of ss starts a transmission. note: sclk must be in the proper idle state before the slave is enabled to prevent sclk from appearing as a clock edge. 11.6.3 dma mode when the tdmaen or rdmaem bits are set, the spi operates in dma mode. normal spte and/or sprf interrupts are suppressed. instead dma requests are generated, signaling the dma controllers to read the spdrr or spdtr as needed. the dma requests are suppressed in the case of an ovrf or modf interrupt, illustrated in figure 11-4 . if the spi is being used to send and receive data, both tdmaen and rdmaen should be enabled/disabled at the same time. if data is only being received or transmitted tdmaen or rdmaen may be left inactive as appropriate, however in this case errie must not be set to prevent the dma request being masked by a mode-fault error or overflow error. dma mode must be used carefully. in the case where cpha=0, the ss signal to the slave is toggled by software between words. in dma mode there is no way of generating this pulse easily, so the dma should not be used when cpha=0. figure 11-4. spi dma request generation receive dma request transmit dma request spte sprie modf ovrf tdmaen modf ovrf errie sprf rdmaen transmission formats 5685x digital signal controller user manual, rev. 4 11-10 freescale semiconductor 11.6.4 wired or mode wired or functionality is provided to permit the connection of multiple spis. figure 11-5 illustrates a single master controlling multiple slave spis. when the wom bit is set, the outputs switch from conventional complementary cmos output to open drain outputs. figure 11-5. sharing of a slave by multiple masters this lets the internal pull-up resistor bring the line high and whichever spi drives the line pulls it low as needed. 11.7 transmission formats during a spi transmission, data is simultaneously transmitted, or shifted out serially, and received; that is it is shifted in serially. a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. master device 1 master device 2 mosi mosi miso miso sclk sclk ss mosi miso sclk ss slave device v dd ss v dd transmission formats serial peripheral interface (spi), rev. 4 freescale semiconductor 11-11 11.7.1 data transmission length the spi can support data lengths from one to 16 bits. this can be configured in the data size register (spdsr). when the data length is less than 16 bits, the receive data register will pad the upper bits with zeros. it is the responsibility of the software to remove these upper bits since 16 bits will be read when reading the receive data register (spdrr). note: data can be lost if the data length is not the same for both master and slave devices. 11.7.2 data shift ordering the spi can be configured to transmit or receive the msb of the desired data first or last. this is controlled by the data shift order (dso) bit in the spscr. regardless which bit is transmitted or received first, the data shall always be written to the spi data transmit register (spdtr) and read from the receive data register (spdrr) with the lsb in bit 0 and the msb in the correct position, depending on the data transmission size. 11.7.3 clock phase and polarity controls software can select any of four combinations of serial clock (sclk) phase and polarity using two bits in the spi status and control register (spscr). the clock polarity is specified by the (cpol) control bit. in turn, it selects an active high or low clock. it has no significant effect on the transmission format. the clock phase (cpha) control bit selects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions, allowing a master device to communicate with peripheral slaves with different requirements. note: before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable (spe) bit. do not change spe and cpha or cpol at the same time. 11.7.4 transmission format when cpha = 0 figure 11-6 exhibits a spi transmission with cpha as logic 0. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sclk: 1. cpol = 0 2. cpol = 1 the diagram may be interpreted as a master or slave timing diagram since the serial clock (sclk), master in/slave out (miso), and master out/slave in (mosi) pins are directly transmission formats 5685x digital signal controller user manual, rev. 4 11-12 freescale semiconductor connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0 because only the selected slave drives to the master. the ss pin of the master is not shown, but it is assumed to be inactive. while modfen = 1, the ss pin of the master must be high or a mode fault error will occur. if modfen = 0, the state of the ss is ignored. when cpha = 0, the first sclk edge is the msb capture strobe. therefore, the slave must begin driving its data before the first sclk edge and a falling edge on the ss pin is used to start the slave data transmission. the slave?s ss pin must be toggled back to high and then low again between each full length data transmitted as depicted in figure 11-7 . note: figure 11-6 assumes 16-bit data lengths and the msb shifted out first. figure 11-6. transmission format (cpha = 0) figure 11-7. cpha/ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the first bit of its data. once the transmission begins, no new data is allowed into the shift register from the spi data transmit register (spdtr). therefore, the spdtr of the slave must be loaded with bit 14 bit 13 bit 3 bit 2 bit 1 lsb msb bit 14 bit 13 bit 3 bit 2 bit 1 lsb msb 1 2 3 13 14 15 16 sclk cycle # (for reference) sclk (cpol = 0) sclk (cpol =1) mosi (from master) miso (from slave) ss (to slave) capture strobe ........ ........ ........ data 1 data 3 miso/mosi data 2 master ss slave ss (cpha = 0) slave ss (cpha = 1) transmission formats serial peripheral interface (spi), rev. 4 freescale semiconductor 11-13 transmit data before the falling edge of ss . any data written after the falling edge is stored in the spdtr and transferred to the shift register after the current transmission. when cpha = 0 for a master, normal operation would begin by the master initializing the ss pin of the slave high. a transfer would then begin by the master setting the ss pin of the slave low and then writing the spdtr. after completion of a data transfer, the ss pin would be put back into the high state by the master device. 11.7.5 transmission format when cpha = 1 a spi transmission is shown in figure 11-8 where cpha is logic1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for sclk: 1 for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (sclk), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or a mode fault error occurs. when cpha = 1, the master begins driving its mosi pin on the first sclk edge. therefore, the slave uses the first sclk edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and slave driving the miso data line. note: figure 11-8 assumes 16-bit data lengths and the msb shifted out first. figure 11-8. transmission format (cpha = 1) bit 14 bit 13 bit 3 bit 2 bit 1 lsb msb bit 14 bit 13 bit 3 bit 2 bit 1 lsb msb 1 2 3 13 14 15 16 sclk cycle # (for reference) sclk (cpol = 0) sclk (cpol =1) mosi (from master) miso (from slave) ss (to slave) capture strobe ........ ........ ........ transmission formats 5685x digital signal controller user manual, rev. 4 11-14 freescale semiconductor when cpha = 1 for a slave, the first edge of the sclk indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the first bit of its data. once the transmission begins, no new data is allowed into the shift register from the data transmit register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of sclk. any data written after the first edge is stored in the data transmit register and transferred to the shift register after the current transmission. 11.7.6 transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdtr starts a transmission. cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the sclk signal. when cpha = 0, the sclk signal remains inactive for the first half of the first sclk cycle. when cpha = 1, the first sclk cycle begins with an edge on the sclk line from its inactive to its active level. the spi clock rate, selected by spr1:spr0, affects the delay from the write to spdtr and the start of the spi transmission. the internal spi clock in the master is a free-running derivative of the internal clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. since the spi clock is free-running, it is uncertain where the write to the spdtr occurs relative to the slower sclk. this uncertainty causes the variation in the initiation delay, demonstrated in figure 11-9 . this delay is no longer than a single spi bit time. that is, the maximum delay is two bus cycles for div2, four bus cycles for div4, eight bus cycles for div8, and so on up to a maximum of 256 cycles for div256. note: figure 11-9 assumes 16-bit data lengths and the msb shifted out first. transmission data serial peripheral interface (spi), rev. 4 freescale semiconductor 11-15 figure 11-9. transmission start delay (master) 11.8 transmission data the double-buffered data transmit register (spdtr) allows data to be queued and transmitted. for a spi configured as a master, the queued data is transmitted immediately after the previous transmission has completed. the spi transmitter empty (spte) flag indicates when the transmit data buffer is ready to accept new data. write to the spdtr only when the spte bit is high. figure 11-10 illustrates the timing associated with doing back-to-back transmissions with the spi (sclk has cpha: cpol = 1:0). note: figure 11-10 assumes 16-bit data lengths and the msb shifted out first. spdtr initiation delay bus mosi sclk (cpha = 1) sclk (cpha = 0) sclk cycle number msb bit 15 12 clock write to spdtr earliest latest (sclk = internal clock 2; earliest latest 2 possible start points) (sclk = internal clock 8; 8 possible start points) earliest latest (sclk = internal clock 16; 16 possible start points) earliest latest (sclk = internal clock 32; 32 possible start points) write to spdtr write to spdtr write to spdtr bus clock bit 14 3 bus clock bus clock bus clock ? ? ? initiation delayfrom write spdtr to transfer begin to write transmission data 5685x digital signal controller user manual, rev. 4 11-16 freescale semiconductor figure 11-10. sprf/spte interrupt timing the transmit data buffer permits back-to-back transmissions without the slave precisely timing its writes between transmissions as is necessary in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift register is the next data to be transmitted. an idle master or idle slave without loaded data in its transmit buffer, sets the spte again no more than two bus cycles after the transmit buffer empties into the shift register. this allows a queue to send up to a 32-bit value. for an already active slave, the load of the shift register bit 3 mosi sclk (cpha:cpol = 1:0) spte write to spdtr 1 2 3 5 sprf read spscr msb bit 14 bit 13 bit ... bit 2 bit 1 lsb msb bit 14 bit 13 bit ... bit 3 bit 2 bit 1 lsb msb bit 14 8 10 4 6 9 11 bit 13 bit ... data 1 data 2 data 3 7 12 read spdrr dsc writes data 1 to spdtr, clearing the spte bit. data 1transfers from transmit data register to shift register, setting spte bit. dsc writes data 2 to spdtr, queueing data 2 and clearing spte bit. first incoming word transfers from the shift register to the receive data register, setting the sprf bit. data 2 transfers from the transmit data register to shift register, setting the spte bit. dsc reads spscr with the sprf bit set. dsc reads spdrr, clearing sprf bit. dsc writes data 3 to spdtr, queueing data 3 and clearing the spte bit. second incoming data transfers from shift register to receive data register setting the sprf bit. data 3 transfersf rom the transmit data register to the shift register, setting the spte bit. dsc reads spscr with the sprf bit. dsc reads spdrr, clearing the sprf bit. 1 2 12 11 10 3 4 5 6 7 8 9 error conditions serial peripheral interface (spi), rev. 4 freescale semiconductor 11-17 cannot occur until the transmission is completed. this implies a back-to- back write to the data transmit register (spdtr) is not possible. the spte indicates when the next write can occur. 11.9 error conditions the following flags signal spi error conditions: ? overflow (ovrf) ? failing to read the spi data register before the next full length data enters the shift register sets the ovrf bit. the new data will not transfer to the data receive register (spdrr), and the unread data can still be read. ovrf is in the spi status and control register (spscr). ? mode fault error (modf) ? the modf bit indicates the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the spscr. 11.9.1 overflow error the overflow flag (ovrf) becomes set if the data receive register (spdrr) still has unread data from a previous transmission and when bit one?s capture strobe of the next transmission occurs. bit 1 capture strobe occurs in the middle of sclk when the data length = transmission data length - 1. if an overflow occurs, all data received after the overflow, and before the ovrf bit is cleared, does not transfer to the spdrr. it does not set the spi receiver full (sprf) bit. the unread data transferred to the spdrr before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register (spscr), then read the spi data register. ovrf generates a receiver/error interrupt request if the error interrupt enable (errie) bit is also set. it is not possible to enable modf or ovrf individually in order to generate a receiver/error interrupt request. however, leaving modfen low prevents modf from being set. if the sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 11-11 explains how it is possible to miss an overflow. the first element of the same figure illustrates how it is possible to read the spscr and spdrr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit can be set between the time spscr and spdrr are read. error conditions 5685x digital signal controller user manual, rev. 4 11-18 freescale semiconductor figure 11-11. missed read of overflow condition in this case, an overflow can easily be missed. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious data is being lost as more transmissions are completed. to prevent this loss, either enable the ovrf interrupt or take another read of the spscr following the read of the spdrr. this ensures the ovrf was not set before the sprf was cleared. future transmissions can set the sprf bit. figure 11-11 illustrates the described process. generally, to avoid a second spscr read, enable the ovrf to the core by setting the errie bit. read spdrr read spscr ovrf sprf data 1 data 2 data 3 data 4 data 1 sets sprf bit. dsc reads spscr with sprf bit dsc reads data 1 in spdrr, data 2 sets sprf bit. dsc reads spscr with sprf bit set data 3 sets ovrf bit. data 3 is lost. dsc reads data 2 in spdrr, clearing sprf data 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. bit but not the ovrf bit. ovrf bit is not cleared. data 4 is lost. set and ovrf bit clear. and ovrf bit clear. error conditions serial peripheral interface (spi), rev. 4 freescale semiconductor 11-19 figure 11-12. clearing sprf when ovrf interrupt is not enabled 11.9.2 mode fault error setting the spmstr bit selects the master mode, configuring the sclk and mosi pins as outputs and the miso pin as an input. clearing spmstr selects the slave mode, configuring the sclk and mosi pins as inputs and the miso pin as an output. the mode fault (modf) bit becomes set any time the state of the slave select (ss ) pin is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the dsc, a mode fault error occurs if: ?the ss pin of a slave spi goes high during a transmission. ?the ss pin of a master spi goes low at any time. to set the modf flag, the mode fault error enable (modfen) bit must be set. clearing the modfen bit does not clear the modf flag, but it does prevent the modf from being set again after the modf is cleared. modf generates a receiver/error interrupt request if the error interrupt enable (errie) bit is also set. it is not possible to enable modf or ovrf individually to generate a receiver/error interrupt request. however, leaving modfen low prevents modf from being set. read spdrr read spscr ovrf sprf data 1 data 2 data 3 data 4 1 data 1 sets sprf bit. dsc reads spscr with sprf bit set dsc reads data 1 in spdrr, dsc reads spscr again data 2 sets sprf bit. dsc reads spscr with sprf bit set data 3 sets ovrf bit. data 3 is lost. dsc reads data 2 in spdrr, dsc reads spscr again dsc reads data 2 spdrr, data 4 sets sprf bit. dsc reads spscr. dsc reads data 4 in spdrr, dsc reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. error conditions 5685x digital signal controller user manual, rev. 4 11-20 freescale semiconductor in a master spi with the mode fault enable (modfen) bit set, the mode fault (modf) flag is set if ss goes to logic 0. a mode fault in a master spi causes the following events to occur: ? if errie = 1, the spi generates a spi receiver/error interrupt request ? the spe bit is cleared (spi disabled) ? the spte bit is set ? the spi state counter is cleared when configured as a slave (spmstr = 0), the modf flag is set if the ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming sclk goes back to its idle level, following the shift of the last data bit. when cpha = 1, the transmission begins when the sclk leaves its idle level and ss is already low. the transmission continues until the sclk returns to its idle level following the shift of the last data bit. note: setting the modf flag does not clear the spmstr bit. the spmstr bit has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no sclk is sent to that slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates a spi receiver/error interrupt request if the errie bit is set. the modf bit does not clear the spe bit or reset the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note: a logic one voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming sclk clocks, even if it was already in the middle of a transmission. in a master spi, the modf flag will not be cleared until the ss pin is at a logic 1 or the spi is configured as a slave. in a slave spi, if the modf flag is not cleared by writing 1 to the modf bit, the condition causing the mode fault still exists. the modf flag and corresponding interrupt can be cleared by disabling the eerie or modfen bits (if set) or by disabling the spi. it is possible to clear the modf error condition by disabling the spe or modfen bits. disabling the spi using the spe bit will cause a partial reset of the spi and may cause the loss of a message currently being received or transmitted. module memory map serial peripheral interface (spi), rev. 4 freescale semiconductor 11-21 to clear the modf flag, write 1 to the modf bit in the spscr. the clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 11.10 module memory map four registers ( table 11-3 ) control and monitor spi operations . two of the four registers are read/write registers. they should be accessed only with word accesses. accesses other than word lengths result in undefined results. two registers are read- and write-only. table 11-3. spi module memory map (spi_base = $1fffe8) address offset register acronym register name access type chapter location base + $0 spscr spi status and control register read/write section 11.11.1 base + $1 spdscr spi data size and control reg. read/write section 11.11.2 base + $2 spdrr spi data receive register read-only section 11.11.3 base + $3 spdtr spi data transmit register write-only section 11.11.4 note: spi registers are not available on the 56855 chip add. offset register name 151413121110987654321 0 $0 scscr r spr dso errie modf en sprie spms tr cpol cpha spe sptie sprf ovrf modf spte w $1 spdscr r wom tdma en rdma en 0 0 0 0 0 0 0 0 0 tds w $2 spdrr rr15r14r13r12r11r10r9r8r7r6r5r4r3r2r1r0 w $3 spdtr r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 wt15t14t13t12t11t10t9t8t7t6t5t4t3t2t1t0 r 0 read as 0 w reserved figure 11-13. spi register map summary spi register descriptions (spi_base = $1fffe8) 5685x digital signal controller user manual, rev. 4 11-22 freescale semiconductor 11.11 spi register descriptions (spi_base = $1fffe8) table 11-3 lists the spi registers in ascending address, including the acronym, bit names, and address of each register. these read/write registers should be accessed only with word accesses. accesses other than word lengths result in undefined results. 11.11.1 spi status and control register (spscr) the spscr register: ? enables spi module interrupt requests ? selects interrupt requests ? configures the spi module as master or slave ? selects serial clock polarity and phase ? enables the spi module receive data register full interrupt ? enables transmits data register empty interrupt ? selects master spi baud rate figure 11-14. spi status and control register (spscr) see programmer?s sheets on appendix page b-64 note: using bfclr or bfset instructions to modify spscr can cause unintended side effects on the status bits. 11.11.1.1 spi baud rate select bits (spr)?bits 15?13 while in the master mode, these read/write bits select one of eight baud rates depicted in table 11-4 . spr2:0 have no effect in slave mode. reset clears spr2:0 to b011. use the formula below to calculate the spi baud rate. spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use the formula below to calculate the spi baud rate. clk = peripheral bus clock bd = baud rate divisor base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spr dso errie modfen sprie spmstr cpol cpha spe sptie sprf ovrf modf spte write reset 01100 0 0 1 01000000 baud rate = clk bd spi register descriptions (spi_base = $1fffe8) serial peripheral interface (spi), rev. 4 freescale semiconductor 11-23 note: the maximum data transmission rate for the spi is typically limited by the bandwidth of the i/o drivers on the chip. typical technology limits are normal at 40mhz and 10mhz for wired or. these apply to both master and slave modes. the bd field needs to be set to keep the module within these ranges. 11.11.1.2 data shift order (dso)?bit 12 this read/write bit determines whether the msb or lsb bit is transmitted or received first. both master and slave spi modules must transmit and receive the same length packets. regardless how this bit is set, when reading from the spdrr or writing to the spdtr, the lsb will always be at bit location zero. if the data length is less than 16 bits, the data will be zero padded on the upper bits. ? 0 = msb transmitted first (msb > lsb) ? 1 = lsb transmitted first (lsb > msb) 11.11.1.3 error interrupt enable (errie)?bit 11 this read/write bit enables the modf and ovrf bits to generate interrupt requests. reset clears the errie bit. the error interrupt enable (errie) bit enables both the modf and ovrf bits to generate a receiver/error interrupt request. ? 0 = modf and ovrf cannot generate interrupt requests ? 1 = modf and ovrf can generate interrupt requests 11.11.1.4 mode fault enable (modfen)?bit 10 this read/write bit, when set to one, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only pre- vents the modf flag from being set. if configured as a master and modfen = 1, a transmission in progress will stop if ss goes low. it does not affect any other part of spi operation. table 11-4. spi master baud rate selection spr[2:0] baud rate divisor (bd) 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 256 spi register descriptions (spi_base = $1fffe8) 5685x digital signal controller user manual, rev. 4 11-24 freescale semiconductor the mode fault enable (modfen) bit can retard the modf flag from being set. the retarded bit results in only the ovrf bit being enabled by the errie bit. this enabling generates receiver/error interrupt requests. 11.11.1.5 spi receiver interrupt enable (sprie)?bit 9 this read/write bit enables interrupt requests generated by the sprf bit. the sprf bit is set when a full data length transfers from the shift register to the spi data receive register (). the spi receiver interrupt enable (sprie) bit enables the sprf bit to generate receiver interrupt requests regardless of the state of the spe bit. the clearing mechanism for the sprf flag is always just a read to the spdrr. ? 0 = sprf interrupt requests disabled ? 1 = sprf interrupt requests enabled 11.11.1.6 spi master (spmstr)?bit 8 this read/write bit selects master mode operation or slave mode operation. ? 0 = slave mode ? 1 = master mode (default) 11.11.1.7 clock polarity (cpol)?bit 7 this read/write bit determines the logic state of the sclk pin between transmissions. to transmit data between spi modules, the spi modules must have identical cpol values. ? 0 = falling edge of sclk starts transmission ? 1 = rising edge of sclk starts transmission 11.11.1.8 clock phase (cpha)?bit 6 this read/write bit controls the timing relationship between the serial clock and spi data. to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between full length data transmissions. do not use cpha = 0 while in the dma mode. 11.11.1.9 spi enable (spe)?bit 5 this read/write bit enables the spi module. clearing spe causes a partial reset of the spi. when setting/clearing this bit, no other bits in the spscr should be changed. failure to following this statement may result in spurious clocks. ? 0 = spi module disabled ? 1 = spi module enabled. spi register descriptions (spi_base = $1fffe8) serial peripheral interface (spi), rev. 4 freescale semiconductor 11-25 11.11.1.10 spi transmit interrupt enable (sptie)?bit 4 this read/write bit enables interrupt requests generated by the spte bit. spte is set when a full data length transfers from the spi data transmit register (spdtr) to the shift register. the spi transmitter interrupt enable (sptie) bit enables the spte flag to generate transmitter interrupt requests, provided the spi is enabled (spe = 1). the clearing mechanism for the spte flag is always just a write to the spdtr. ? 0 = spte interrupt requests disabled ? 1= spte interrupt requests enabled 11.11.1.11 spi receiver full (sprf)?bit 3 this read-only flag is set each time full length data transfers from the shift register to the spi data receive register (spdrr). sprf generates an interrupt request if the sprie bit in the spi status and control register (spscr) is set also. this bit may not be cleared. ? 0 = data receive register not full ? 1 = data receive register full 11.11.1.12 overflow (ovrf)?bit 2 this read-only flag is set if software does not read the data in the spi data receive register (spdrr) before the next full data enters the shift register. in an overflow condition, the data already in the spdrr is unaffected, and the data shifted in last is lost. clear the ovrf bit by reading the spi status and control register (spdscr) with ovrf set and then reading the spdrr. this bit may be cleared using the proper software sequence. ? 0 = no overflow ? 1 = overflow 11.11.1.13 mode fault (modf)?bit 1 this read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bit by writing one to the modf bit when it is set. the delayed bit results in only the ovrf interrupt being enabled by the errie bit. this enabling generates receiver/error interrupt requests. ?0 = ss pin at appropriate logic level ?1 = ss pin at inappropriate logic level spi register descriptions (spi_base = $1fffe8) 5685x digital signal controller user manual, rev. 4 11-26 freescale semiconductor 11.11.1.14 spi transmitter empty (spte)?bit 0 this read-only flag is set each time the sp data transmit register (spdtr) transfers a full data length into the shift register. spte generates an interrupt request if the sptie bit in the spi sta- tus and control register (spscr) is set also. this bit may be cleared using the proper software sequence. ? 0 = data transmit register not empty ? 1 = data transmit register empty note: do not write to the spi data register unless the spte bit is high. 11.11.2 spi data size and control register (spdscr) this read/write register determines the data length for each transmission. the master and slave must transfer the same size data on each transmission. a new value will only take effect at the time the spi is enabled (spe bit in spscr register set from zero to one). in order to have a new value take effect, disable then re-enable the spi with the new value in the register. the spdscr: ? enables spi dma mode for the transmitter and receiver ? enables wired or mode on miso and mosi ? configures the size of the transmission figure 11-15. spi data size and control register (spdscr) see programmer?s sheets on appendix page b-65 11.11.2.1 wired or mode ( wom)?bit 15 this control bit is used to select the nature of the spi pins. when enabled, the wom bit is set, the spi pins are configured as open-drain drivers with the pull-ups disabled. however, when disabled, the wom bit is cleared, and the spi pins are configured as push-pull drivers. ? 0 = wired or mode disabled ? 1 = wired or mode enabled 11.11.2.2 transmitter dma enable (tdmaen)?bit 14 in the dma mode, normal interrupts (not error) are suppressed and a dma request is generated instead. the requirement for clearing sprf/spte changes to read/write the spdrr/spdtr, thereby eliminating the read of spscr. base +$1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read wom tdmaen rdmaen 0 0 0 0 0 0 0 0 0 tds write reset 0 0 0 0000000001111 spi register descriptions (spi_base = $1fffe8) serial peripheral interface (spi), rev. 4 freescale semiconductor 11-27 ? 0 = transmitter dma mode disabled ? 1 = transmitter dma mode enabled 11.11.2.3 receiver dma enable (rdmaen)?bit 13 in the dma mode, normal interrupts (not error) are suppressed and a dma request is generated instead. the requirement for clearing sprf/spte changes to read/write the spdrr/spdtr, thereby eliminating the read of spscr. ? 0 = receiver dma mode disabled ? 1 = receiver dma mode enabled 11.11.2.4 reserved?bits 12?4 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. 11.11.2.5 transmission data size (t ds)?bits 3?0 please see table 11-5 for detailed transmission data. table 11-5. transmission data size ds3 - ds0 size of transmission 0not allowed 12 bits 23 bits 34 bits 45 bits 56 bits 67 bits 78 bits 89 bits 9 10 bits 10 11 bits 11 12 bits 12 13 bits 13 14 bits 14 15 bits 15 16 bits resets 5685x digital signal controller user manual, rev. 4 11-28 freescale semiconductor 11.11.3 spi data receive register (spdrr) this read-only register will show the last full data received after a complete transmission while the sprf bit will set when new data has been transferred to this register. figure 11-16. spi data receive register (spdrr) see programmer?s sheets on appendix page b-66 11.11.3.1 data receive?bits 15?0 11.11.4 spi data transmit register (spdtr) this write-only register modifies the data to the transmit data buffer. when the spte bit is set, new data should be written to this register. if new data is not written while in the master mode, a new transaction will not be initiated until this register is written. when in slave mode, the old data will be re-transmitted. all data should be written with the lsb at bit zero. figure 11-17. spi data transmit register (spdtr) see programmer?s sheets on appendix page b-67 11.11.4.1 data transmit?bits 15?0 11.12 resets any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following will occur: ? the spte flag is set. ? any slave mode transmission currently in progress is aborted. ? any master mode transmission currently in progress is continued to completion. ? the spi state counter is cleared, making it ready for a new complete transmission. ? all the spi port logic is disabled. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 write reset 0000000000000000 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 write t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 reset 0000000000000000 interrupts serial peripheral interface (spi), rev. 4 freescale semiconductor 11-29 the following items are reset only by a system reset: ? the spdtr and spdrr registers ? all control bits in the spscr register (modfen, errie, spr1, and spr0) ? the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, it is possible to clear spe between transmissions without having to set all control bits again when spe is set back high for the next transmission. by not resetting the sprf, ovrf, and modf flags, it is possible to service the interrupts after the spi has been disabled. disable spi by writing 0 to the spe bit. spi can also be disabled by a mode fault occurring in a spi configured as a master with modf. 11.13 interrupts four spi status flags can be enabled to generate interrupt requests. the following sources in the spi status and control register can generate interrupt requests: ? the spi transmitter interrupt enable (sptie) bit enables the spte flag to generate transmitter interrupt requests provided the spi is enabled (spe = 1). the clearing mechanism for the spte flag is always just a write to the data transmit register. ? the spi receiver interrupt enable (sprie) bit enables the sprf bit to generate receiver interrupt requests regardless of the state of the spe bit. the clearing mechanism for the sprf flag is always just a read to the data receive register. ? the error interrupt enable (errie) bit enables both the modf and ovrf bits to generate a receiver/error interrupt request. ? the mode fault enable (modfen) bit can prevent the modf flag from being set so only the ovrf bit is enabled by the errie bit to generate receiver/error interrupt requests. table 11-6. spi interrupts flag request spte (transmitter empty) spi transmitter interrupt request (sptie = 1,spe = 1) sprf (receiver full) spi receiver interrupt request (sprie = 1) ovrf (overflow) spi receiver/error interrupt request (errie = 1) modf (mode fault) spi receiver/error interrupt request (errie = 1) interrupts 5685x digital signal controller user manual, rev. 4 11-30 freescale semiconductor figure 11-18. spi interrupt request generation the following sources in the spi status and control register can generate interrupt requests: ? spi receiver full (sprf) bit ? the sprf bit becomes set every time a full data transmission transfers from the shift register to the receive data register. if the spi receiver interrupt enable (sprie) bit is also set, sprf can generate a spi receiver/error interrupt request. ? spi transmitter empty (spte) ? the spte bit becomes set every time a full data transmission transfers from the data transmit register to the shift register. if the spi transmit interrupt enable (sptie) bit is also set, spte can generate a spte interrupt request. spte sptie sprf sprie errie modf ovrf spe spi transmitter interrupt request spi receiver/error interrupt request enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-1 chapter 12 enhanced synchronous serial interface (essi) 5685x digital signal controller user manual, rev. 4 12-2 freescale semiconductor features enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-3 12.1 introduction this chapter describes the enhanced synchronous serial interface (essi), discusses the architecture, the programming model, the operating modes, and the initialization of the essi. the essi is a full-duplex, serial port designed to allow digital signal controllers (dscs) to communicate with a variety of serial devices, including industry-standard codecs, other dscs, and microprocessors. it is typically used to transfer samples in a periodic manner. the essi consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. 12.2 features essi capabilities include: ? independent (asynchronous) or shared (synchronous) transmit and receive sections with separate or shared internal/external clocks and frame syncs ? normal mode operation using frame sync ? network mode operation allowing multiple devices to share the port with as many as 32 time slots ? network mode enhancements ? time slot mask registers (receive and transmit) ? end of frame interrupt ? programmable internal clock divider ? programmable word length (8, 10, 12, or 16 bits) ? program options for frame sync and clock generation ? essi power-down feature ? audio enhancements ? three transmitters per essi (six-channel surround sound possible, but requires two essis) signal descriptions 5685x digital signal controller user manual, rev. 4 12-4 freescale semiconductor 12.3 signal descriptions 12.3.1 signal properties 12.3.2 external signals descriptions three to six signals are required for essi operation, depending on the selected operation mode. the function of the i/o pins for the essi is determined by a number of control bits. table 12-2 lists the controls affecting this and the resulting pin definitions. the serial transmit data (std) signal and serial control (sc0 and sc1) signals are fully synchronized to the clock if they are programmed as transmit data signals. table 12-3 further clarifies the possible configuration of the sc0 and sc1 pins during synchronous modes when they are not being used as transmit data pins. in addition to the functional configuration of the i/o pins, the direction of clocks and frame syncs can be configured. the source of the transmit and receive clocks used by essi is determined by three control bits, illustrated in table 12-1 . the source of the receive and transmit frame syncs is determined by three control bits, illustrated in table 12-3 . table 12-1. signal properties name type function reset state notes sck i/o essi transmit clock input controlled by reset state of sckd bit in scr4 register sc2 i/o essi transmit frame sync input controlled by reset state of scd2 bit in scr4 register sc0 i/o essi receive clock input controlled by reset state of scd0 bit in str4 register sc1 i/o essi receive frame sync input controlled by reset state of scd1 bit in str4 register std output essi transmit data hi-z since essien bit is scr2 register is reset to 0 srd input essi receive data ? ? signal descriptions enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-5 table 12-2. mode and signal definition table control bits essi signal definitions syn te0 te1 te2 re sc0 sc1 sc2 sck std srd 0 0 xx 0u 1rxc fsr u rd 1 0u fst txc td0 u 1rxc fsr rd 1 0 0 0 0u 1 f0/u f1/t0d/u fs xc u rd 1 0 td2 u 1rd 1 0 0 td1 f1/t0d/u u 1rd 1 0 td2 u 1rd 1 0 0 0 f0/u f1/t0d/u td0 u 1rd 1 0 td2 u 1rd 1 0 0 td1 f1/t0d/u u 1rd 1 0 td2 u 1rd f0=flag 0 f1 =flag 1 if ssc1 = 0 fs =transmit / receive frame sync (synchronous operation) fsr = receiver frame sync fst= transmitter frame sync rd = receiver data rxc =receiver clock t0d =transmitter 0 drive enable if ssc1=1 & scd1=1 td0 =transmit data signal 0 td1 =transmit data signal 1 td2 =transmit data signal 2 txc =transmitter clock x =indeterminate xc =transmitter / receiver clock (synchronous operation) u =unused (may be used as gpio signal) signal descriptions 5685x digital signal controller user manual, rev. 4 12-6 freescale semiconductor 12.3.2.1 essi transmit clock (sck) this pin can be configured as either an input or an output pin. this clock signal is used by all the enabled transmitters and the receiver in synchronous modes or by transmitter 0 in asynchronous modes. please see table 12-3 for details about how to configure this pin. note: although an external serial clock can be independent of and asynchronous to the system clock, the external essi clock frequency must not exceed f ipbus_clk /4, and each essi clock phase must exceed the minimum of 1.5 ipbus_clk cycles. 12.3.2.2 essi serial control signal 0 (sc0) the function of this signal is determined by the programmer selecting either synchronous or asynchronous mode, according to data in table 12-4 . in asynchronous mode, this signal is used for the receive clock i/o. in synchronous mode, this signal is used as the transmitter data out table 12-3. essi clock sources controls rx clock tx clock syn sckd scd0 pin source pin direction asynchronous 0 0 0 sc0 external sck external 0 0 1 sc0 internal sck external 0 1 0 sc0 external sck internal 0 1 1 sc0 internal sck internal synchronous 1 0 x sck external sck external 1 1 x sck internal sck internal table 12-4. essi frame sync sources controls rx clock frame sync tx frame sync syn scd2 scd1 pin source pin direction asynchronous 0 0 0 sc1 external sc2 external 0 0 1 sc1 internal sc2 external 0 1 0 sc1 external sc2 internal 0 1 1 sc1 internal sc2 internal synchronous 1 0 x sc2 external sc2 external 1 1 x sc2 internal sc2 internal signal descriptions enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-7 signal for transmit shift register tx1 or for serial flag i/o. a typical application of serial flag i/o would be multiple device selection for addressing in codec systems. if sc0 is configured as a serial flag signal or receive clock signal, its direction is determined by the serial control direction 0 (scd0) bit in the essi control register 4 (scr4). when configured as an output, sc0 may be used either as the serial output flag 0 (of0) or as a receive shift register clock output. if the sc0 is used as the serial of0, its value is determined by the value of the serial of0 bit in the scr4 register. if sc0 is an input, this signal may be used either as serial input flag 0 (if0) or as a receive shift register (rsr) clock input. if sc0 is used as serial input flag 0, it controls the state of the serial input flag 0 bit in the essi status register (essr). when sc0 is configured as a transmit data signal, it is always an output signal regardless of the scd0 bit value. sc0 is fully synchronized with the other transmit data signals, std and sc1. note: the essi can operate with more than one active transmitter only in the synchronous mode. 12.3.2.3 essi receive frame sync (sc1) the function of this signal is determined by the programmer selecting either synchronous or asynchronous modes, according to table 12-4 . in the asynchronous mode, such as a single codec with asynchronous transmit and receive, the sc1is the receiver frame sync i/o. in the synchronous mode, the sc1 is used for the transmitter data out signal of transmit shift register (txsr2), for the transmitter 0 drive-enable signal, or for serial flag i/o. when used as serial flag i/o, sc1operates like sc0. sc0 and sc1 are independent flags, but they may be used together for multiple serial device selection. sc0 and sc1 can be used without being encoded to select up to two codecs. they may also be decoded externally to select up to four codecs. if the sc1 is configured as a serial flag signal, its direction is determined by the scd1 bit in scr4 register. if the sc1 is configured as a serial flag or receive frame sync signal, its direction is determined by the serial control direction 1 (scd1) bit in the scr4 register. when configured as an output, the sc1 signal can be used as a serial output flag, as the transmitter 0 drive-enable signal for the purpose to control an external high-drive buffer, or as the receive frame sync signal output. if sc1 is used as serial output flag 1, its value is determined by the value of the serial output flag 1 (of1) bit in the scr4 register. when configured as an input, this signal can be used to receive frame sync signals from an external source, or it can be used as a serial input flag. when sc1 is a serial input flag, it controls status bit if1 in the ssr. essi block diagram 5685x digital signal controller user manual, rev. 4 12-8 freescale semiconductor when this signal is configured as a transmit data signal, it is always an output signal regardless of the scd1 bit value. as an output, it is fully synchronized with the other essi transmit data signals (std and sc0). note: the source of the transmitter 0 drive-enable signal is the std_oen signal. 12.3.2.4 essi serial control signal 2 (sc2) this pin is used for frame sync i/o and can be configured as either an input or an output pin. the direction of this signal is determined by the scd2 bit of the scr4 register. the frame sync is used by the transmitter to synchronize the transfer of data in asynchronous mode. it is used by both the receiver and transmitter in synchronous mode. the frame sync signal can be one-bit, or one-word in length. the start of the frame sync can occur one-bit before the transfer of data, or right at the start of the data transfer. 12.3.2.5 essi transmit data (std) the std signal is used for transmitting data from the txsr0 serial transmit shift register. std is an output pin when data is being transmitted from the txsr0 shift register. the std pin is tri-stated after transmitting the last data bit when another data word does not follow immediately. if a data word follows immediately within a full clock cycle, the std pin is not tri-stated. 12.3.2.6 essi receive data (srd) the srd signal receives serial data, then transfers the data to the essi receive data shift register (rxsr). 12.4 essi block diagram the following figure illustrates the essi block diagram. it consists of five control registers to set-up the port, one status register, separate transmit and receive circuits with fifo registers, and separate serial clock and frame sync generation for the transmit and receive sections. essi block diagram enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-9 figure 12-1. essi block diagram transmit control reg receive control reg status reg control reg 2 control reg 3 control reg 4 16-bit stxcr srxcr ssr scr2 scr3 scr4 txfifo2 txsr0 ipbus rxfifo srx rxsr sck sc2 sc0 time slot reg transmit shift reg receive shift reg fifo control status reg sfcsr rx clock generator tx clock generator transmit data reg tx sync generator rx sync generator stx2 stx1 txfifo0 txsr1 transmit mask reg receive mask reg transmit data reg transmit data reg stx0 txfifo2 txsr2 stsr tsma & tsmb rsma & rsmb tx control and state machines rx control and state machines sc1 transmit shift reg transmit shift reg receive data reg std srd functional description 5685x digital signal controller user manual, rev. 4 12-10 freescale semiconductor 12.5 functional description the essi has two basic operating modes. table 12-5 lists these operating modes and some of the typical applications. these distinctions result in the basic operating modes allowing the essi to communicate with a wide variety of devices. these modes can be programmed by several bits in the essi control registers. for additional information, please see section 12.8 . the essi supports both normal and network modes, and these can be selected independently of whether the transmitter and receiver are synchronous or asynchronous. typically these protocols are used in a periodic manner, where data is transferred at regular intervals, such as at the sampling rate of an external codec. both modes use the concept of a frame. the beginning of the frame is marked with a frame sync. the frame sync occurs at a periodic interval. the length of the frame is determined by the dc and wl field bits in either the srxcr or stxcr register, depending on whether data is being transmitted or received. the number of words transferred per frame depends on the mode of the essi. 12.5.1 normal mode normal mode is the simplest mode of the essi. it is used to transfer one word per frame. a frame sync occurs at the beginning of each frame. the length of the frame is determined by the following factors: ? the period of the serial bit clock (psr, pm bits for internal clock or the frequency of the external clock on the sck or sc0 pin) ? the number of bits per sample (wl) bits ? the number of time slots per frame (dc) bits table 12-5. essi operating modes tx, rx sections 1 1. in the synchronous mode, the transmitter and receiver use a common clock and frame sychronization signal. in the asynchronous mode the transmitter and receiver operate independently on their own clocks and frame syncs. serial clock mode 2 2. in the normal mode, the essi only transmits during the first time-slot of each i/o frame. in the network mode, any number from 2 to 32 data words of i/o per frame can be used. the network mode is typically used in star or ring time division multiplex networks with other processors or codecs, allowing interface to tdm networks without additional logic. typical application asynchronous continuous normal multiple asynchronous codecs asynchronous continuous network tdm codec or dsc networks synchronous continuous normal multiple synchronous codecs synchronous continuous network tdm codec or dsc network functional description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-11 if the normal mode is configured to provide more than one time slot per frame, data is transmitted only in the first time slot. no data is transmitted in subsequent time slots. figure 12-2 and figure 12-3 show sample timing of normal mode transfers. 12.5.1.1 normal mode transmit conditions for data transmission from the essi in the normal mode: 1. set the stxcr, scr2, scr3, and scr4 registers to select normal mode operation. 2. define the transmit clock, transmit frame sync and frame structure required for proper system operation. 3. essi enabled (essien = 1) 4. enable txfifo (tfen = 1) and configure the transmit watermark (tfwm = n) if this txfifo is used. 5. write data to the transmit data (stx) register. 6. enable transmit interrupts. 7. set the te bit (te = 1) to enable the transmitter on the next frame sync boundary. figure 12-2 and table 12-6 describe the functions performed during transmit operation in this mode. figure 12-2. normal mode transmit timing (wl=8 bit words, dc = 1) valid indefinite transition depends on sw interrupt processing invalid sck sc2 stx register tde status bit / interrupt txsr register std 2 4 6 7 1 functional description 5685x digital signal controller user manual, rev. 4 12-12 freescale semiconductor 12.5.1.2 normal mode receive the conditions for data reception from the essi are as follows: 1. set the srxcr, scr2, scr3, and scr4 registers to select normal mode operation. 2. define the receive clock. 3. receive frame sync and frame structure required for proper system operation. 4. essi enabled (essien = 1) 5. enable rxfifo (rfen=1) and configure receive watermark (rfwm = n) if rxfifo is used. 6. enable receive interrupts. 7. set the re bit (re = 1) to enable the receiver operation on the next frame sync boundary. table 12-6. normal mode transmit operations step txfifo disabled 1 txfifo enabled 1 rising edge of sc2. note a word length frame sync is shown. this only works if dc>0. ? ? 2 data transferred to txsr. from stx from txfifo 3 std output pin is enabled 2 and the first bit of the txsr register appears on the output. ?? 4 flag status update. the tde bit is set the tfe bit is set if the level of data in the txfifo falls below the watermark level. 5 if the tie bit is set, enabling transmit interrupts, then: open options for processing the data transfer is either polling or dma transfers. transmit interrupt occurs when tde is set. transmit interrupt occurs when tfe set. 6 the txsr is shifted on the next rising edge of the sck and the next bit appears on the std pin. ?? 7 when wl bits (section 11.8.14) have been sent the std is tri-stated. ?? 8 transmit underrun (setting the tue bit of the ssr register) is prevented by 3 : new data is written to the stx before the txsr tries to obtain new transmit data at the next frame sync. new data is written to the stx before the txsr tries to obtain data from an empty txfifo (this can be several frame times). 9 repeat at step 1 on the next frame sync 4 . ?? 1. see figure 12-2 . 2. the std output signal is disabled except during the data transmission period. 3. section 12.8.9 describes what happens when the tue bit is set. 4. the frame sync must not occur earlier than it is configured in the stxcr as documented in section 12.8.11 . functional description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-13 figure 12-3 and table 12-7 describes the functions performed during receive operation in this mode. figure 12-3. normal mode receive timing (wl=8 bit words, dc=1) table 12-7. normal mode receive operations step txfifo disabled 1 1. see figure 12-2 . txfifo enabled 1 leading edge of frame sync occurs on the sc1 pin. ?? 2 falling edge of receive clock occurs on the sc0 pin and the next bit of data is shifted into the rxsr register. ?? 3 when wl bits 2 have been received. rxsr contents are transferred to the srx register on the next falling edge of the receive clock. the srx register is actually loaded during the middle of the last receive bit. 2. see section 12.8.11 . ?? 4 flag status update the rdr bit is set the rff bit is set if the level of data in the rsfifo rises above the watermark level. 5 if the rie bit is set, enabling receive interrupts, then: other options for processing the data transfer is either polling or dma transfers. ? receive interrupt occurs when rff is set. 6 receive overrun (setting the roe bit of the ssr register) is prevented by 3 3. section 12.8.11 describes what happens when the roe bit is set. ? data is read from the srx before the rxsr tries to provide more data to a full rsfifo. it can take several frame times to fill the rxfifo. 7 repeat at set 1 on the next frame sync. 4 4. the frame sync must not occur earlier than it is configured in the stxcr as documented in section 12.8.11 . ?? sc0 sc1 srd rxsr register srx register rdr status bit / interrupt valid indefinite transition depends on sw interrupt processing invalid 1 2 3 4 functional description 5685x digital signal controller user manual, rev. 4 12-14 freescale semiconductor 12.5.2 network mode network mode is used for creating a time division multiplexed (tdm) network, such as a tdm codec network or a network of dscs. this mode only operates with continuous clock mode. a frame sync occurs at the beginning of each frame. in this mode, the frame is divided into more than one time slot. during each time slot, one data word can be transferred. each time slot is then assigned to an appropriate codec or dsc on the network. the dsc can be a master device controlling its own private network, or a slave device connected to an existing tdm network, occupying a few time slots. the frame sync signal indicates the beginning of a new data frame. each data frame is divided into time slots and transmission and/or reception of one data word can occur in each time slot (rather than in just the frame sync time slot as in the normal mode). the frame rate dividers, controlled by the dc bit field, select two to thirty-two time slots per frame. the length of the frame is determined by these factors: ? the period of the serial bit clock (psr, pm[7:0] bits for internal clock, or the frequency of the external clock on the sck and/or sc0 pins) ? the number of bits per sample (wl) bits ? the number of time slots per frame (dc) bit fields data can be transmitted in any time slot while in the network mode. the distinction of the network mode is each time slot is identified with respect to the frame sync (data word time). this time slot identification allows the option of transmitting data during the time slot by writing to the stx register or ignoring the time slot by writing to stsr. the receiver is treated in the same manner, except data is always being shifted into the rxsr and transferred to the srx register. the core reads the srx register, either using the data or discarding it. figure 12-4 and figure 12-5 provide sample timing of network mode transfers. the figures illustrate receive and transmit frames of five time-slots for each. the numbered circles and arrows in the figure identify discussion notes contained in table 12-8 and table 12-9 . 12.5.2.1 network mode transmit the transmit portion of the essi is enabled when the essien and the te bits in the scr2 are both set. however, when the te bit is set, the transmitter is enabled only after detection of a new frame boundary. software has to find the start of the next frame by checking the tfs bit of the ssr. a normal start-up sequence for transmission is to do the following: 1. set the stxcr, scr2, scr3, and scr4 registers to select the network mode operation. 2. define the transmit clock. 3. transmit frame sync and frame structure required for proper system operation. functional description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-15 4. essi enabled (essien = 1) 5. enable txfifo (tfen = 1) and configure the transmit watermark (tfwm = n) if this txfifo is used. 6. write data to transmit data register (stx). 7. enable transmit interrupts. 8. set the te bit (te = 1) to enable the transmitter on the next frame sync boundary. the transmitter timing for an 8-bit word with continuous clock, fifo disabled, five words per frame sync, in the network mode is shown in figure 12-4 . the explanatory notes for the transmit portion of the figure are provided in table 12-8 . figure 12-4. network mode transmit timing ts 0 ts 1 ts 2 ts 3 ts 4 ts 0 time slot sck internal word clock sc2 tfs bit of ssr register tde status bit / interrupt stx register stsr register txsr register std 2 4 5 1 3 4 valid indefinite transition depends on sw interrupt processing invalid functional description 5685x digital signal controller user manual, rev. 4 12-16 freescale semiconductor the operation of clearing the te bit disables the transmitter after completion of transmission of the current data word. setting the te bit again enables transmission of the next word. during the time te = 0, the std signal is tri-stated. the te bit should be cleared after the tde bit is set, ensuring all pending data is transmitted. note: in case of normal mode with external frame sync, te bit should be cleared after the first bit of transmission only. the network mode transmitter generates interrupts every time slot (unless the tsm registers are utilized) and requires the dsc program to respond to each time slot. these responses may be one of the following: ? write the data register with data to enable transmission in the next time slot. ? write the time slot register to disable transmission in the next time slot. ? do nothing?transmit underrun occurs at the beginning of the next time slot and the previous data is re-transmitted. table 12-8. notes for transmit timing in figure 12-5 note source signal destination signal description 1 ? ? example of a five time-slot frame, transmitting in time-slots 0 and 3. 2sc2 ? example with word-length frame sync and standard timing (tfsi=0, tfsl=0, and tefs=0). frame timing begins with the rising edge of sc2. 3? tde status flag and interrupt this flag is set at the beginning of each word to indicate that another data word should be supplied by the software. when the transmit interrupt is enabled, the processor is interrupted to request the data. the flag and interrupt are cleared when data is written to either the stx or stsr registers. 1 4 stx / stsr register txsr register on each word clock boundary a decision is made concerning what to transmit on the next time-slot. if the stsr register was written during the previous time-slot the std pin is tri-stated. if the stsr register was not written during the previous time-slot the contents of the stx register is transferred to the txsr register and this data is shifted out. if the stx register has not been written in the previous time-slot the previous data is reused. if neither of these registers were written in the previous time-slot the tue status bit will be set and the hardware will operate as if the stx register had been written. the std pin will be enabled and the contents of the stx will be transmitted again. this may lead to drive conflicts on the transmit data line. 5 txsr register std pin on active time-slots, the txsr register contents are shifted out on the std pin, one bit per rising edge of sck. on inactive time-slots, the std pin is tri-stated so it can be driven by another device. 1. section 12.13 provides a complete description of interrupt processing. functional description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-17 12.5.2.2 network mode receive the receiver portion of the essi is enabled when both the essien and the re bits in the scr2 are set. however, when the re bit is set, the receiver is enabled only after detection of a new frame boundary. software has to find the start of the next frame by checking the rfs bit in the ssr. a normal start-up sequence for receive operation is to do the following: 1. set the srxcr, scr2, scr3, and scr4 registers to select network mode operation, define the receive clock, receive frame sync and frame structure required for proper system operation. 2. essi enabled (essien = 1) 3. enable rxfifo (rfen=1) and configure receive watermark (rfwm = n) if rxfifo is used. 4. enable receive interrupts. 5. set the re bit (re = 1) to enable the receiver operation on the next frame sync boundary. the receiver timing for an 8-bit word with continuous clock, fifo disabled, five words per frame sync, in network mode is shown in figure 12-5 . the explanatory notes for the receive portion of the figure are shown in table 12-9 . figure 12-5. network mode receive timing ts 0 ts 1 ts 2 ts 3 ts 4 ts 0 time slot sc0 internal word clock sc1 rfs bit of ssr register srd rxsr register srx register rdr status bit / interrupt valid indefinite transition depends on sw interrupt processing invalid 6 8 9 10 11 functional description 5685x digital signal controller user manual, rev. 4 12-18 freescale semiconductor an interrupt can occur after the reception of each data word or the programmer can poll the rdr flag. the essi program response can be one of the following: ? read srx and use the data ? read srx and ignore the data ? do nothing?the receiver overrun exception occurs at the end of the current time slot. 12.5.3 synchronous/asynchronous operating modes the transmit and receive sections of the essi may be synchronous or asynchronous. during asynchronous operation the transmitter and receiver have their own separate clock and sync signals. when operating in the synchronous mode the transmitter and receiver use common clock and synchronization signals, specified by the transmitter configuration. the syn bit in scr2 selects synchronous or asynchronous operation. since the essi is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided. during the synchronous operation, the receiver and transmitter operate in lock step with each other. overhead may be reduced by eliminating either the receive or transmit interrupts, driving both channels from the same set of interrupts. if this decision is made, it is necessary to be aware of the specific timing of the receive and transmit interrupts, because the interrupts are not generated at the same exact point in the frame timing, table 12-9. notes for receive timing in figure 12-6 note source signal destination signal description 6? ? example of a five time slot frame, receiving data from time slots 0 and 2. the receive hardware will obtain data on the srd pin every bit time. the software must determine which data belongs to each time slot and discard the unwanted time slot data. 7 sc0 ? receive clock timing from which it is derived. 8sc1 ? example with bit length frame sync and standard timing (rfsi=0, rfsl=1, and refs=0). frame timing begins with the rising edge of sc1. 9srd rxsr register data on the srd pin is sampled on the falling edge of sc0 and shifted into the rxsr register. 10 rxsr register srx register at the word clock, the data in the rxsr register is transferred to the srx register. 11 rdr status flag and receive interrupt ? this flag is set for each word clock (time slot) indicating data is available to be processed. the software must keep track of the time slots as they occur so it knows which data to keep. if the receive interrupts are enabled (rie=1) an interrupt will be generated when this status flag is set. the software reads the srx register to clear the interrupt. 1 1. section 12.13 provides a complete description of the interrupt process. functional description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-19 shown in figure 12-6 . if it is desired to run off a single set of interrupts, the tx interrupts should be used. if rx interrupts are used, there may be timing problems with the transmit data because this interrupt occurs a half-bit time before the transmit data is used by the hardware. figure 12-6. synchronous mode interrupt timing 12.5.4 network mode with mask registers implemented in order to reduce interrupt overhead, a number of enhancements were made to the essi module. the enhancements incorporate the mask registers (tsm and rsm). together, figure 12-8 and figure 12-33 illustrate sample timing of network mode transfers using the mask registers. these figures duplicate the frame structure of figure 12-5 to illustrate the reduced amount of interrupt processing required. the numbered circles and arrows in the figures identify discussion notes contained in table 12-10 and table 12-11 . 12.5.4.1 operation using tsm register when the tsm register is included in the design interrupt overhead can be reduced. if all bits of the tsm register are set, the essi transmitter will continue to operate as previously described. the tsm register is used to disable the std pin on specific time-slots. this is accomplished by writing the tsm with 0 in the time-slot bit location. disabling a time- slot in this manner causes the time-slot to be ignored by the essi. this means no data is transferred to the transmit shift register (txsr), therefore interrupts are not generated for this time-slot. the transmitter timing, using tsm registers for an 8-bit word, continuous clock with disabled fifo five words per frame sync in the network mode is illustrated in figure 12-7 . explanatory notes for the transmit portion of the figure are provided in table 12-10 . sck sc2 stx register tde status bit / interrupt rdr status bit / interrupt valid indefinite transition depends on sw interrupt processing invalid tx interrupt rx interrupt tx interrupt rx interrupt functional description 5685x digital signal controller user manual, rev. 4 12-20 freescale semiconductor note: in this example there are only two transmit interrupts per frame instead of five as in the previous example where the tsm register is not used. figure 12-7. network mode transmit timing with mask register ts 0 ts 1 ts 2 ts 3 ts 4 ts 0 tsm[0] tsm[1] tsm[2] tsm[3] tsm[4] tsm[0] time slot sck internal word clock sc2 tsmn bits usage tde status bit / interrupt stx register txsr register std 2 5 1 4 valid indefinite transition depends on sw interrupt processing invalid 3 4 functional description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-21 12.5.4.2 operation using rsm register when the rsm register is included in the design, interrupt overhead can be reduced. if all bits of the rsm register are set, the essi receiver will continue to operate as previously described. the rsm register is used to automatically discard data from selected time slots. this is accomplished by writing the rsm with 0 in the selected time-slot bit location. this means no data is transferred from the receive data shift register (rxsr) on the zero time-slots, no status flags change, and no interrupts are generated. receiver timing in the network mode, and using rsm registers for an 8-bit word with a continuous clock, results in the disabled fifo five words per frame sync. in this example there are only two receive interrupts per frame instead of five as in the previous example where the rsm register is not used. this process is illustrated in figure 12-8 and explained in table 12-11 . table 12-10. notes for transmit timing with mask register in figure 12-8 note source signal destination signal description 1 ? ? example of a five time slot frame, transmitting in time slots 0 and 3. 2sc2 ? example of a word length frame sync and standard timing (tfsi=0, tfsl=0, and tefs=0). frame timing begins with the rising edge of sc2. 3? tde status flag and interrupt for enabled time slots, this flag is set at the beginning of each word to indicate the stx data has been used and another data word should be supplied by the software. if the transmit interrupt is enabled the processor is interrupted to request the data. the flag and interrupt are cleared when data is written to either the stx or stsr registers. 1 4 stx / stsr register txsr register on each word clock boundary a decision is made concerning what to transmit on the next time slot. if the tsmn register bit is zero for the next time slot, the std pin is tri-stated and the time slot is ignored. when the tsmn bit is one for the next time slot, the contents or the stx register are transferred to the txsr register and this data is shifted out. if the stx register has not been written in the previous time slot, the previous data is reused. note: if the stsr is written instead of the stx, the std pin is tri-stated as stated in section 12.5.2.1 . when neither of these registers were written in the previous time slot (where tsmn=1), the tue status bit will be set and the hardware will operate as if the stx register had been written. the std pin will be enabled and the contents of the stx will be transmitted again. this may lead to drive conflicts on the transmit data line, in another device is transmitting data during this time slot. 5 txsr register std pin on active time slots, the txsr register contents are shifted out on the stc pin, one bit per rising edge of sck. on inactive time slots, the std pin is tri-stated so it can be driven by another device. 1. section 12.13 provides a complete description of the interrupt process. functional description 5685x digital signal controller user manual, rev. 4 12-22 freescale semiconductor figure 12-8. network mode receive timing with mask register table 12-11. notes for receive timing with mask register in figure 12-33 note source signal destination signal description 6? ? example of a five time slot frame, receive data from time slots 0 and 2. the receive hardware will only obtain data on the srd pin when the rsmn bit is set to one. 7sc1 ? example with bit length frame sync and standard timing (rfsi=0, rfsl=1, and refs=0). frame timing begins with the rising edge of sc1. 8srd rxsr register data on the srd pin is sampled on the falling edge of sc0 and shifted into the rxsr register. 9 rxsr register srx register at the word clock, the data in the rxsr register is transferred to the srx register, for enabled time slots. 10 rdr status flag and receive interrupt ? this flag is set for each word clock, or time slot, where the rsmn bit is set, indicating data is available to be processed. the software must keep track of the time slots as they occur so it knows which data it is processing. when the receive interrupts are enabled (rie=1) an interrupt will be generated when this status flag is set. the software reads the srx register to clear the interrupt. 1 1. section 12.13 provides a complete description of the interrupt process. ts 0 ts 1 ts 2 ts 3 ts 4 ts 0 rsm[0] rsm[1] rsm[2] rsm[3] rsm[4] rsm[0] 01 2 3 4 0 time slot sc0 internal word clock sc1 rsmn bits usage rtscnt field of sfsr register srd rxsr register srx register rdr status bit / interrupt valid indefinite transition depends on sw interrupt processing invalid 6 7 8 9 10 essi configurations enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-23 12.6 essi configurations figure 12-9 and figure 12-10 illustrate the main essi configurations. these pins support all transmit and receive functions shown. section 12.5 describes the clock, frame sync, and data timing relationships in each of the modes available. some modes do not require the use of all six pins. in this case, these pins can be used as mpio pins, if desired. note: the mpio is a separate module alternatively controlling the function and state of the i/o pins. see the mpio module definition for alternate functions of the i/o pins defined here. figure 12-9. asynchronous (syn=0) essi configurations std srd sck sc2 sc0 sc1 essi+gpio essi internal asynchronous clock (scd0=1,sckd=1,scd1=1,scd2=1,syn=0) std srd sck sc2 sc0 sc1 essi+gpio essi external asynchronous clock (scd0=0,sckd=0,scd1=0,scd2=0,syn=0) std srd sck sc2 sc0 sc1 essi+gpio essi asynchronous clock (scd0=1, sckd=0, scd1=1,scd2=0, syn=0) std srd sck sc2 sc0 sc1 essi+gpio essi asynchronous clock (scd0=0, sckd=1, scd1=0, scd2=1, syn=0) essi configurations 5685x digital signal controller user manual, rev. 4 12-24 freescale semiconductor figure 12-10. synchronous essi configurations essi internal synchronous clock (scd0=x, sckd=1, scd1=x, scd2=1, syn=1) essi external synchronous clock (scd0=0, sckd=0, scd1=x, scd2=0,syn=1) essi + gpio essi internal synchronous clock, triple transmit (scd0=1, sckd=1, scd1=1, scd2=1, syn=1, te1=te2=1) std srd sck sc2 sc0 sc1 essi + gpio std srd sck sc2 essi + gpio std srd sck sc2 essi + gpio essi external synchronous clock, triple transmit (scd0=1, sckd =0, scd1=1, scd2=0, syn=1, te1=te2=1) std srd sck sc2 sc0 sc1 module memory map enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-25 12.7 module memory map nine registers make up the essi peripheral and are summarized in table 12-12 and figure 12-11 . table 12-12. essi module memory map (essi0_base = $1ffe20, essi1_base = $1ffe00) address offset register acronym register name access type chapter location base + $0 stx0 transmit data register 0 write-only section 12.8.1 base + $1 stx1 transmit data register 1 write-only section 12.8.2 base + $2 stx2 transmit data register 2 write-only section 12.8.3 base + $3 srx receive data register read-only section 12.8.4 base + $4 ssr status register read-only section 12.8.7 base + $5 scr2 control register 2 read/write section 12.8.8 base + $6 scr3 control register 3 read/write section 12.8.9 base + $7 scr4 control register 4 read/write section 12.8.10 base + $8 stxcr transmit control register read/write section 12.8.11 base + $9 srxcr receive control register read/write base + $a stsr time slot register write-only section 12.8.12 base + $b sfcsr fifo control/status register read-only section 12.8.13 base + $c tsma transmit slot mask register read/write section 12.8.14 base + $d tsmb transmit slot mask register read/write base + $e rsma receive slot mask register read/write section 12.8.15 base + $f rsmb receive slot mask register read/write add. offset register name 151413121110987654321 0 $0 stx0 r wdata $1 stx1 r wdata $2 stx2 r wdata $3 srx r high byte low byte w $4 ssr rif1 if0 tff tls rls tf1err tf2err rdr tde roe tue tfs rfs rff tfe w $5 scr2 r rie tie re te0 te1 te2 syn tshfd tsckp essien net tfsi tfsl tefs w $6 scr3 r div4dis rshfd rsckp rd mae td mae rfsi rfsl refs rfen tfen init synrst rlie tlie w $7 scr4 r txsf0 txsf1 txsf2 ssc1 sckd scd2 scd1 scd0 of1 of0 w figure 12-11. essi register map summary register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-26 freescale semiconductor 12.8 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) all registers are addressed by word. byte accesses to the registers are not supported. eight registers are not accessible. registers associated with the enhanced ssi (essi) are delineated in the memory chapter, table 3-16 and table 3-17 . 12.8.1 essi transmit registers (stx0, stx1, stx2) the essi transmit data (stx02) are write-only 16-bit registers. data to be transmitted is written to these registers. if the transmit fifo registers are utilized, data is transferred from the stx02 registers to the transmit fifo register as the fifos have available space. otherwise, data written to these registers is transferred to the transmit shift register (stx02) whenever the transmit fifo feature is enabled. when the feature is enabled, the transmit shift registers (txsr02) receive their values from these fifo registers. transmitted data is first-in-first-out. if the transmit fifo feature is not enabled, this register is bypassed and the contents of the transmit data registers (stx02) is transferred into the transmit shift registers (txsr02). when the transmit interrupt enable (tie) bit in scr2 register is set the dsc is interrupted when the level of data in an enabled transmit fifo falls below the selected threshold and the transmit data register empty (tde) bit in the essi status register (ssr) is set. when both transmit fifo and transmit data registers are full, any further write will overwrite the content of the transmit data registers (stx02). add. offset register name 151413121110987654321 0 $8 stxcr r psr wl dc pm w $9 srxcr r psr wl dc pm w $a stsr r w dummy register written during inactive time slots (network mode) $b sfcsr r rfcnt tfcnt rfwm tfwm w $c tsma r tsma [15:0] w $d tsmb r tsmb [31:16] w $e rsma r rsma [15:0] w $f rsma r rsmb [31:16] w r 0 read as 0 w reserved figure 12-11. essi register map summary (continued) register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-27 note: enable essi (essien = 1), before writing to transmit data register and transmit fifo. figure 12-12. essi transmit data register 0 (stx0) see programmer?s sheet on appendix page b - 68 figure 12-13. essi transmit data register 1 (stx1) see programmer?s sheet on appendix page b - 68 figure 12-14. essi transmit data register 2 (stx2) see programmer?s sheet on appendix page b - 68 12.8.2 essi transmit fifo registers (txfifo0, txfifo1, txfifo2) the 8 16-bit txfifo registers are used to buffer samples written to the transmit data registers (stx0-2). they are written by the contents of the transmit data registers (stx0-2) whenever the transmit fifo feature is enabled. if enabled, the transmit shift registers (txsr0-2) receive their values from the fifo registers. if the transmit fifo feature is not enabled, this register is bypassed and the contents of stx0-2 registers are transferred into the transmit shift registers (txsr0-2). when the transmit interrupt enable (tie) bit in the scr2 and transmit data register empty (tde) bit in the ssr are set, the transmit interrupt is asserted whenever stx0-2 are empty and the data level in the essi transmit fifo falls below the selected threshold. base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write data reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write data reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write data reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-28 freescale semiconductor when both txfifo and stx are full, any further write will overwrite the content of txfifo and stx. note: enable essi before writing to txfifo and stx. 12.8.3 essi transmit shift registers (txsr0, txsr1, txsr2) the txsr0-2 are 16-bit shift registers containing transmitted data. data is shifted out to the serial transmit data (std, sc0, and sc1) pins by the selected internal/external bit clock when the associated internal/external frame sync is asserted. the word length (wl) control bits in the essi transmit control register (stxcr) determine the number of bits to be shifted out of the txsr0-2 registers before it is considered empty and can receive further writing. please refer to section 12.8.11 for more information. this word length can be 8, 10, 12, or 16 bits. the data to be transmitted occupies the most significant portion of the shift register. the unused portion of the register is ignored. data is always shifted out of this register with the most significant bit (msb) first when the tshfd bit of the scr2 is cleared, illustrated in figure 12-15 . if this bit is set, the least significant bit (lsb) is shifted out first, diagramed in figure 12-16 . figure 12-15. transmit data path (tshfd = 0) stx 16 bits 8 bits 12 bits 10 bits 15 0 8 7 6 5 4 15 0 87 txsr std register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-29 figure 12-16. transmit data path (tshfd = 1) 12.8.4 essi receive register (srx) the srx is a 16-bit, read-only register. it always accepts data from the receive shift register (rxsr) as it becomes full. the data read occupies the most significant portion of the srx register. the unused bits (least significant portion) are read as 0s. if the receive data full interrupt is enabled, the interrupt is asserted whenever the srx register becomes full. when the receive fifo is also enabled, the receive fifo must be above its watermark before the interrupt is asserted. figure 12-17. essi receive data register (srx) see programmer?s sheet on appendix page b - 69 12.8.5 essi receive fifo register (rxfifo) the rxfifo is a 8 16-bit fifo register used to buffer samples received in the essi receive data shift register (rxsr). the receive fifo is enabled by setting the rfen bit of the scr3 control register. received data is then held in the fifo if the data in the srx has not yet been read. base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read high byte low byte write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 stx 15 0 essi 87 15 0 txsr 8 7 6 5 4 8 bits 10 bits 12 bits 16 bits 16 bits 8 bits 12 bits 10 bits register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-30 freescale semiconductor if the receive interrupt is enabled, it is asserted whenever the srx is full and the data level in the essi receive fifo reaches the selected threshold. if the receive fifo feature is not enabled, this register is bypassed and the receive shift register (rxsr) data is automatically transferred into the srx. 12.8.6 essi receive shift register (rxsr) this is a 16-bit shift register receiving incoming data from the serial receive data srd pin. data is shifted in by the selected internal/external bit clock when the associated internal/external frame sync is asserted. data is assumed to be received msb first if the rshfd bit of the scr3 is cleared, illustrated in figure 12-18 . if this bit is set, the data is received lsb first, as diagramed in figure 12-19 . data is transferred to the essi receive data register (srx) or receive fifo, if the receive fifo is enabled and srx is full, after 8, 10, 12, or 16 bits have been shifted in depending on the wl control bits. when receiving 8, 10, or 12 bits data, lsb bits are set to 0. figure 12-18. receive data path (rshfd = 0) figure 12-19. receive data path (rshfd = 1) srx 15 0 16 bits rxd 87 8 bits 12 bits 10 bits 15 0 rxsr srx 15 0 16 bits srd 87 15 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-31 12.8.7 essi status register (ssr) this is a 16-bit, read-only register except for the rls and tls bits described in the following third note. it is used to monitor the essi. the register is used to interrogate the status and serial input flags of the essi. the status bits are described in the following paragraphs. figure 12-20. essi status register (ssr) see programmer?s sheet on appendix page b - 70 note: essi status flag is updated when the essi is enabled. note: all flags in the status portion of the ssr are updated after the first bit of the next essi word has completed transmission or reception. the roe and tue status bits are cleared by reading the ssr followed by a read/write to either the srx or stx0-2 register, respectively. note: the rls and tls status bits are cleared by reading the ssr, then writing 1 to the appropriate bit of the ssr. 12.8.7.1 input flag 1 (if1)?bit 15 the if1 bit is enabled only when sc1 is configured as an input flag and the synchronous mode is selected. for example, when the syn bit is set and the te2 and scd1 bits are cleared. please refer to table 12-15 . the essi latches any data present on the sc1 signal during reception of the first received bit after the frame sync is detected. the if1 bit is updated with this data when the data in the receive shift register is transferred into the receive data register if it is not enabled, the if1 bit is cleared. 12.8.7.2 input flag 0 (if0)?bit 14 the if0 bit is enabled only when sc0 is configured as an input flag and the synchronous mode is selected; that is to say, when the syn bit is set and the te1 and scd0 bits are cleared. please see table 12-16 for more information. the essi latches any data present on the sc0 signal during reception of the first received bit after the frame sync is detected. the if0 bit is updated with this data when the data in the receive base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read if1 if0 tff tls rls tf1err tf2err rdr tde roe tue tfs rfs rff tfe write reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-32 freescale semiconductor shift register is transferred into the receive data register. if it is not enabled, the if0 bit is cleared. 12.8.7.3 reserved?bit 13 this bit is reserved or not implemented. it cannot be read nor modified by writing. 12.8.7.4 transmit fifo full (tff)?bit 12 this status bit allows monitoring when the transmit fifo is full. the state of this bit reflects the status of the transmitter(s) selected by the txsf0-2 control bits. ? 0 = transmit fifo can accept more data ? 1 = transmit fifo is full 12.8.7.5 transmit last slot (tls)?bit 11 this is a status bit indicating the timing of the last transmit slot during the network mode operation. when this bit is set, the transmit last slot interrupt is asserted. the interrupt service routine for this interrupt should read the status register, then write 1 to this bit to clear the interrupt. if the transmit last slot interrupt is not enabled, this bit can be read by the software to determine the timing of the last slot. when the tlie bit in the scr3 register is disabled the status bit will only be asserted during the last slot timing. ? 0 = not currently transmitting the last time slot of the transmit frame ? 1 = last slot of the transmit frame is currently being transmitted 12.8.7.6 receive last slot (rls)?bit 10 this is a status bit indicating the timing of the last receive slot during the network mode operation. when this bit is set, the receive last slot (rls) interrupt bit is asserted. the interrupt service routine for this interrupt should read the status register and then write 1 to this bit to clear the interrupt. if the rls interrupt is not enabled, this bit can be read by the software to determine the timing of the last slot. when the rlie bit in the scr3 register is disabled the status bit will only be asserted during the last slot timing. ? 0 = not currently receiving the last time slot of the receive frame ? 1 = last slot of the receive frame is currently being received register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-33 12.8.7.7 transmit fifo 1 error (tf1err)?bit 9 when the transmitter status control txsf1 is set and fifos are in use, this status bit will indicate the state of fifo 1 is not the same as fifo 0. if transmitter 0 (txsf0 = 0) is not in use this flag can never be set. ? 0 = state of txfifo0 and txfifo1 are the same (contain the same amount of data) ? 1 = state of txfifo0 is different than the state of txfifo1 12.8.7.8 transmit fifo 2 error (tf2err)?bit 8 when the transmitter status control txsf2 is set and fifos are in use, this status bit indicates the state of fifo2 is not the same as fifo0. if transmitter 0 (txsf0 = 0) is not in use, this status bit will indicate the state of fifo2 is not the same as fifo1. if transmitter 1 is also not operating (txsf0 = txsf1 = 0), this flag can never be set. ? 0 = status of txfifo2 matches the other enabled txfifos ? 1 = status (data content level) of txfifo2 is different than the other enabled txfifos 12.8.7.9 receive data ready flag (rdr)?bit 7 this flag bit is set when receive data register (srx) or receive fifo (rxfifo) is loaded with a new value. rdr is cleared when the cpu reads the srx register. if rxfifo is enabled, rdr is cleared when receive fifo is empty. if the rie bit is set, a receive data interrupt request is issued when the rdr bit is set. the interrupt request vector depends on the state of the receiver overrun error (roe) bit on the ssr. the rdr bit is cleared by power-on reset (por) and essi reset (essien = 0). 12.8.7.10 transmit data register empty (tde)?bit 6 this flag bit is set when there is no data waiting to be transferred to the txsr register. a transmit fifo (txfifo) is enabled when there is at least one empty slot in stx or txfifo. when the txfifo is not enabled, the stx is empty. for example, when the contents of the stx register are transferred into the transmit shift register (txsr). when set, the tde bit indicates data should be written to the stx register or to the stsr before the transmit shift register becomes empty, or an underrun error will occur. the tde bit is cleared when data is written to the stx register or to the stsr to disable trans- mission of the next time slot. if the tie bit is set, an essi transmit data interrupt request is issued when the tde bit is set. the vector of the interrupt depends on the state of the tue bit in the ssr. the tde bit is set by power-on reset (por) and essi reset (essien = 0). register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-34 freescale semiconductor 12.8.7.11 receive overrun error (roe)?bit 5 this flag bit is set when the receive shift register (rxsr) is enabled, filled, ready to transfer to the srx, or the rxfifo registers, and when these registers are already full. if the receive fifo is enabled, it is indicated by the receive fifo full (rff) bit otherwise this is indicated by the receive data ready (rdr) bit being set. the rxsr is not transferred in this case. note: when using the rxfifo with a watermark other than eight, the roe bit does not mean data has been lost. the rxcnt field of the sfcsr should be checked to determine the likelihood of actual data loss. a receive overrun error (roe) does not cause interrupts. however, when the roe bit is set, it causes a change in the interrupt vector used, allowing the use of a different interrupt handler for a receive overrun condition. if a receive interrupt occurs with the roe bit set, the receive data with exception status interrupt is generated. if a receive interrupt occurs with the roe bit cleared, the receive data interrupt is generated. the roe bit is cleared by power-on reset (por) or essi reset (essien = 0) and by reading the ssr with the roe bit set followed by reading the srx register. clearing the re bit does not affect the roe bit. 12.8.7.12 transmitter underrun error (tue)?bit 4 this flag bit is set when the txsr is empty, or when there is no data to be transmitted, indicated by the tde bit being set and a transmit time slot occurs. when a transmit underrun error occurs, the previously sent data is retransmitted. a transmit time-slot in the normal mode occurs when the frame sync is asserted. each time-slot requires data transmission in the network mode, it may cause a tue error. the tue bit does not cause interrupts. however, the tue bit will cause a change in the interrupt vector used for transmit interrupts. consequently, a different interrupt handler can be used for a transmit underrun condition. if a transmit interrupt occurs with the tue bit set, the transmit data with exception status interrupt is generated. if a transmit interrupt occurs with the tue bit cleared, the transmit data interrupt is generated. the tue bit is cleared by power-on reset (por) or essi reset (essien = 0). the tue bit is also cleared by reading the ssr with the tue bit set, followed by writing to the stx register or to the stsr. the state of this bit reflects the status of the transmitter(s) selected by the txsf0-2 control bits in the scr4 register. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-35 12.8.7.13 transmit frame sync (tfs)?bit 3 the middle section of figure 12-21 exhibits data written to the stx register in the network mode during the time slot when the tfs bit is set. this is transmitted during either of the following: ? second time slot (in the network mode) ? in the following first time slot (in the normal mode) while in network mode, the tfs bit is set during transmission of the first slot of the frame. the bit is then cleared when starting transmission of the next slot. the tfs bit is cleared by power-on reset (por) or essi reset (essien = 0). 12.8.7.14 receive frame sync (rfs)?bit 2 when set, this flag bit indicates a frame sync occurred during receiving of the next word into the srx register. the process is illustrated in the lower portion of figure 12-21 . in the network mode, the rfs bit is set while the first slot of the frame is being received. it is cleared when the next slot of the frame begins to be received. the rfs bit is cleared by power-on reset (por) or essi reset (essien = 0). register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-36 freescale semiconductor figure 12-21. frame sync timing options 12.8.7.15 receive fifo full (rff)?bit 1 this flag bit is set when the receive section is programmed with the enabled receive fifo. the data level in the rxfifo must reach the selected receive fifo watermark (rfwm) threshold. when set, the rff indicates data can be read using the srx register. note: an interrupt is generated only if both rff and rie bits are set and if the rxfifo is enabled. the rff bit is cleared in normal operation by reading the srx register. the rff is cleared by power-on reset (por) or disabling the essi (essien = 0). when the rxfifo is completely full, all further received data is ignored until current data is read. ts 0 ts 1 ts n a) frame sync timing options b) tfs status flag operation c) rfs status flag operation sck, sc0 bit-length fs early bit-length fs word-length fs early word-length fs time slots stx register tfs std pin srd pin rfs srx register indefinite transition depends on sw interrupt processing invalid valid register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-37 12.8.7.16 transmit fifo empty (tfe)?bit 0 this flag bit is set when the transmit section is programmed with an enabled txfifo and the data level in the txfifo falls below the selected transmit fifo watermark (tfwm) threshold. when set, the tfe bit indicates data can be written to the txfifo register. the tfe bit is cleared by writing data to the stx register until the txfifo data content level reaches the water- mark level. note: an interrupt is generated only if both tfe and the tie bits are set if a transmit fifo is enabled. the tfe bit is set by power-on reset (por) and when essi is disabled (essien = 0). 12.8.8 essi control register 2 (scr2) the essi control register 2 (scr2) is one of five 16-bit, read/write control registers used to direct the operation of the essi. the essi reset is controlled by a bit in scr2. interrupt enable bits for the receive and transmit sections are provided in this control register. essi operating modes are also selected in this register. the power-on reset (por) clears all scr2 bits. the essi reset (essien = 0) does not affect the scr2 bits. the scr2 bits are described in the following paragraphs. note: as with all on-chip peripheral interrupts, the interrupt controller must be configured to allow essi maskable interrupts and determine their interrupt priority level, before enabling them in this register. figure 12-22. essi control register 2 (scr2) see programmer?s sheet on appendix page b - 72 base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rie tie re te0 te1 te2 syn tshfd tsckp essien net tfsi tfsl tefs write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-38 freescale semiconductor 12.8.8.1 receive interrupt enable (rie)?bit 15 this control bit allows interrupting the program controller. when the rie and re bits are set, the program controller is interrupted when the essi receives data. as provided in table 12-13 , the interrupt trigger depends on whether the receive fifo is enabled. if the receive fifo is disabled: ? 0 = no interrupt is generated. ? 1 = an interrupt is generated when the rdr flag in the ssr is set. one value can be read from the srx register. reading the srx register clears the rdr bit, thus clearing the interrupt. if the receive fifo is enabled: ? 0 = no interrupt is generated. ? 1 = an interrupt is generated when the rff flag in the ssr is set. a maximum of eight values are available to be read from the srx register. to clear the rff bit interrupt, read the srx register, removing data from the receive fifo, thereby dropping the data level below the watermark. two receive data interrupts with separate interrupt vectors are available: 1. receive data with exception status. 2. receive data without exception. generated interrupt vectors and their conditions are listed in table 12-13 . 12.8.8.2 transmit interrupt enable (tie)?bit 14 this control bit provides program controller interruption. when the tie and te0-2 bits are set the program controller is interrupted when the essi needs more transmit data lists. the interrupt trigger depends whether the transmit fifos are enabled, shown in table 12-14 . table 12-13. essi receive data interrupts 1 1. table 12-27 provides a complete list of interrupts. interrupt rie selection control roe rfen = 0 rfen = 1 receive data with exception status 1 rdr = 1 rff = 1 1 transmit date without exception status 1 rdr = 1 rff = 1 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-39 if the transmit fifo is disabled: ? 0 = no interrupt is generated. ? 1 = an interrupt is generated when the tde flag in the ssr is set. one value can be written to each of the enabled stx0-2 registers when this interrupt occurs. if the transmit fifo is enabled: ? 0 = no interrupt is generated. ? 1 = an interrupt is generated when the tfe flag in the ssr is set. when this interrupt occurs, up to eight values can be written to each of the enabled stx0-2 registers, depending on the level of the txfifo watermark. the tde bit always indicates the stx register empty condition even when the transmitter is disabled by the transmit enable (te) bits in the scr2. writing data to the stx register or stsr clears the tde bit, thus clearing the interrupt. two transmit data interrupts with separate interrupt vectors are available: 1. transmit data with exception status 2. transmit data without exceptions 12.8.8.3 table 12-14 lists the conditions these interrupts are generated. 12.8.8.4 receive enable (re)?bit 13 this control bit enables the receive portion of the essi. ? 0 = receiver is disabled by inhibiting data transfer into the srx. if data is being received when this bit is cleared, the rest of the word is not shifted in, or is it transferred to the srx register. ? 1 = receive portion of the essi is enabled and received data will be processed starting with the next receive frame sync. if the re bit is re-enabled during a time slot before the second to last bit, then the word will be received. it is recommended to clear this bit when clearing essien. table 12-14. essi transmit data interrupts 1 1. table 12-27 provides a complete list of interrupts. interrupt tie selection control tue tfen = 0 tfen = 1 transmit data with exception status 1 tde = 1 tfe = 1 1 transmit date without exception status 1 tde = 1 tfe = 1 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-40 freescale semiconductor 12.8.8.5 transmit enable 0 (te0)?bit 12 this control bit enables the transfer of the contents of the stx0 register to its transmit data shift register 0 (txsr0). te0 is functional when the essi is in either synchronous or asynchronous modes. ? 0 = the transmitter continues to send the data currently in txsr0, then disables the transmitter. ? 1 = on the next frame boundary, the transmit 0 portion of the essi is enabled. with internally generated clocks, the frame boundary will occur within a word time. if the te0 bit is cleared, then set again during the same transmitted word, the data continues to be transmitted. if the te0 bit is set again during a different time slot, data is not transmitted until the next frame boundary. the serial output is tri-stated and any data present in the stx0 register is not transmitted. for example, data can be written to the stx0 register with the te0 bit cleared and the tde bit is cleared, but data is not transferred to the txsr0. the normal transmit enable sequence is to write data to the stx0 register or to the stsr before setting the te0 bit. the normal transmit disable sequence is to clear both the te0 and tie bits after the tde bit is set. this bit should be cleared when clearing essien. 12.8.8.6 transmit enable 1 (te1)?bit 11 this control bit enables the transfer of the contents of the stx1 register to its transmit data shift register 1 (txsr1). te1 is functional when the essi is in the synchronous mode. it is ignored when the essi is in the asynchronous mode. ? 0 = the transmitter continues to send the data currently in txsr1, then disables the transmitter. the serial output is tri-stated and any data present in the stx1 register is not transmitted. in other words, data can be written to the stx1 register with the te1 bit cleared and the tde bit is cleared but data is not transferred to the txsr1. ? 1 = on the next frame boundary, the transmit 1 portion of the essi is enabled for that frame. with internally generated clocks, the frame boundary will occur within a word time. if the te1 bit is cleared and then set again during the same transmitted word, the data continues to be transmitted. if the te1 bit is set again during a different time slot, data is not transmitted until the next frame boundary. when the te1 bit remains clear until the beginning of the next frame, it causes the sc0 signal to act as a serial i/o flag from the start of the frame in both normal and network modes. the normal transmit enable sequence is to write data to the stx1 register or to the stsr before setting the te1 bit. the normal transmit disable sequence is to clear the te1 and tie bits after the tde bit is set. this bit should be cleared when clearing essien. note: setting the te1 bit does not affect the generation of frame sync or output flags. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-41 12.8.8.7 transmit enable 2 (te2)?bit 10 this control bit enables the transfer of the contents of the stx2 register to its transmit data shift register 2 (txsr2). the te2 bit is functional when the essi is in the synchronous mode. it is ignored when the essi is in the asynchronous mode. ? 0 = the transmitter continues to send the data currently in txsr2, then disables the transmitter. the serial output is tri-stated and any data present in the stx2 register is not transmitted; that is to say, data can be written to the stx2 register with the te2 and tde bits cleared, but data is not transferred to the txsr2. ? 1 = on the next frame boundary, the transmit 2 portion of the essi is enabled for that frame. with internally generated clocks, the frame boundary will occur within a word time. if the te2 bit is cleared, then set again during the same transmitted word, the data continues to be transmitted. if the te2 bit is set again during a different time slot, data is not transmitted until the next frame boundary. when the te2 bit remains clear until the start of the next frame, it causes the sc1 signal to act as a serial i/o flag from the start of the frame in both normal and network modes. the normal transmit enable sequence is to write data to the stx2 register or to the stsr before setting the te2 bit. the normal transmit disable sequence is to clear the te2 bit and the tie bit after the tde bit is set. this bit should be cleared when clearing essien. note: setting the te2 bit does not affect the generation of frame sync or output flags. 12.8.8.8 reserved?bits 9?8 these bits are reserved or not implemented. they cannot be read nor modified by writing. 12.8.8.9 synchronous mode (syn)?bit 7 this control bit enables the synchronous mode of operation. in this mode, the transmit and receive sections share a common clock pin (sck) and frame sync pin (sc2). table 12-3 illustrates the clock configuration options. table 12-4 illustrates the frame sync options. note: synchronous mode operation with all transmitters disabled and the receiver enabled requires an externally generated frame sync. 12.8.8.10 transmit shift direction (tshfd)?bit 6 this bit controls whether the msb or lsb is transmitted first for the transmit section. ? 0 = msb is transmitted first. ? 1 = lsb is transmitted first. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-42 freescale semiconductor note: the codec device labels the msb as bit 0, whereas the essi labels the lsb as bit 0. therefore, when using a standard codec, the essi msb (or codec bit 0) is shifted out first, and the tshfd bit should be cleared. 12.8.8.11 transmit clock polarity (tsckp)?bit 5 this control bit determines which bit clock edge is used to clock out data in the transmit section. ? 0 = data is clocked out on the rising edge of the bit clock. ? 1 = the falling edge of the bit clock is used to clock the data out. 12.8.8.12 essi enable (essien)?bit 4 this control bit enables and disables the essi. ? 0 = the essi is disabled and held in a reset condition. when disabled, all output pins are tri-stated, the status register bits are preset to the same state produced by the power-on reset (por) and the control register bits are unaffected. the contents of the stx, txfifo and rxfifo are cleared when this bit is reset. when essi is disabled, all internal clocks are disabled except clocks required for register access. when clearing essien, it is recommended to also clear re and te0-2. ? 1 = the essi is enabled, causing an output frame sync to be generated when set up for internal frame sync, or it causes the essi to wait for the input frame sync when set up for external frame sync. 12.8.8.13 network mode (net)?bit 3 this control bit selects the operational mode of the essi. ? 0 = normal mode is selected. ? 1 = network mode is selected. 12.8.8.14 transmit frame sync invert (tfsi)?bit 2 this control bit selects the logic of frame sync i/o. ? 0 = frame sync is active high ? 1 = frame sync is active low register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-43 12.8.8.15 transmit frame sync length (tfsl)?bit 1 this control bit selects the length of the frame sync signal to be generated or recognized. see the upper portion of figure 12-21 for an example timing diagram of the frame sync options. ? 0 = a one-word long frame sync is selected. the length of this word-long frame sync is the same as the length of the data word selected by wl. ? 1 = a one-bit long frame sync is selected the frame sync is deasserted after one bit-for-bit length frame sync and after one word- for-word length frame sync. 12.8.8.16 transmit early frame sync (tefs)?bit 0 this bit controls when the frame sync is initiated for the transmit and receive sections. please refer to the upper portion of figure 12-21 for a timing diagram example of the frame sync options. ? 0 = frame sync is initiated as the first bit of data is transmitted. ? 1 = frame sync is initiated one-bit before the data is transmitted. the frame sync is disabled after one bit-for-bit length frame sync and after one word-for-word length frame sync. 12.8.9 essi control register 3 (scr3) the essi control register 3 (scr3) is one of five 16-bit, read/write control registers used to direct the operation of the essi. scr3 controls enabling of the last slot interrupts for network mode transmit and receive operations. the power-on reset (por) clears all scr3 bits. the essi reset (essien = 0) does not affect the scr3 bits. figure 12-23. essi control register 3 (scr3) see programmer?s sheet on appendix page b - 75 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read div4dis rshfd rsckp rdmae tdmae rfsi rfsl refs rfen tfen init synrst rlie tlie write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-44 freescale semiconductor 12.8.9.1 divider 4 disable (div4dis)?bit 15 ? 0 = fix_clk = ip_clk/4 for both transmitter and receiver clock generator circuits ? 1 = fix_clk is equal to ip_clk 12.8.9.2 receive shift direction (rshfd)?bit 14 this bit controls whether the msb or lsb is received first for the receive section. ? 0 = data is received msb first ? 1 = data is received lsb first note: the codec device labels the msb as bit 0, whereas the essi labels the lsb as bit 0. therefore, when using a standard codec, the essi msb (or codec bit 0) is shifted in first. the rshfd bit should be cleared. 12.8.9.3 receive clock polarity (rsckp)?bit 13 this bit controls which bit clock edge is used to capture data for the receive section. ? 0 = captured data during clock falling edge ? 1 = capture data input during rising edge of the clock 12.8.9.4 receive dma enable (rdmae)?bit 12 this bit allows the essi to request a direct memory access (dma) module transfer of received data. if the receive fifo is disabled : ? 0 = no dma transfer is requested. ? 1 = a dma request is generated when the essi receive data ready (rdr) bit is set. if the receive fifo is enabled : ? 0 = no dma transfer is requested. ? 1 = a dma request is generated when the essi receive fifo full (rff) bit in the ssr is set. the receive fifo full watermark should be set to rfwm = 01 because any other setting of rfwm can leave data in the fifo not transferred by the dma. receive interrupt enable (rie) has higher priority than receive dma enable (rdmae). that is to say, if rie is set, an interrupt is generated to the cpu instead of dma. note: if dam is not supported on the chip, this bit has no meaning and should always be cleared. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-45 12.8.9.5 transmit dma enable (tdmae)?bit 11 this bit allows the essi to request a dma transfer for the next data to transmit. if the transmit fifo is disabled : ? 0 = no dma transfer is requested. ? 1 = a dma request is generated when the essi transmit data empty (tde) bit is set. if the transmit fifo is enabled : ? 0 = no dma transfer is requested. ? 1 = a dma request is generated when the essi transmit fifo empty (tfe) bit in the ssr is set. the transmit fifo empty watermark bit can be set to any level. the fifo is then filled to the indicated level by the dma controller so data is readily available in the essi. transmit interrupt enable (tie) has higher priority than transmit dma enable (tdmae). for example, if tie is set, an interrupt is generated to the cpu instead of dma. note: if more than one transmit channel is enabled, a dma channel is required for each transmitter. note: if dma is not supported on the chip, this bit has no meaning and should always be cleared. 12.8.9.6 receive frame sync invert (rfsi)?bit 10 this bit selects the logic of frame sync i/o for the receive section. ? 0 = frame sync is active high. ? 1 = frame sync is active low. 12.8.9.7 receive frame sync length (rfsl)?bit 9 this bit selects the length of the frame sync signal to be generated or recognized for the receive section. please note the first portion of figure 12-21 for an example timing diagram of the frame sync options. ? 0 = a one-word long frame sync is selected. the length of a word-long frame sync is the same as the length of the data word selected by wl. ? 1 = a one-bit long frame sync is selected. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-46 freescale semiconductor 12.8.9.8 receive early frame sync (refs)?bit 8 this bit controls when the frame sync is initiated for the receive section. please note the first portion of figure 12-21 for an example timing diagram of the frame sync options. ? 0 = when the refs bit is cleared, the frame sync is initiated as the first bit of data is received. ? 1 = the frame sync is initiated one-bit before the data is received. the frame sync is disabled after one bit-for-bit length frame sync and after one word-for-word length frame sync. 12.8.9.9 receive fifo enable (rfen)?bit 7 this control bit enables the fifo register for the receive section. ? 0 = the fifo register is not used, and an interrupt request is generated (assuming interrupts are enabled) when a single sample is received by the essi and rdr is set. ? 1 = allows eight samples, depending on the receive watermark set in the sfcsr, to be received by the essi. a ninth sample can be shifting in before the rff bit is set and an interrupt request generated when enabled by the rie bit. 12.8.9.10 transmit fifo enable (tfen)?bit 6 this control bit enables the fifo registers for the transmit section. ? 0 = the fifo register is not used. ? 1 = a maximum of eight samples can be written to the stx register. a ninth sample can be shifting out. 12.8.9.11 initialize state machine (init)?bit 5 this bit is used to initialize the state machine to reset state. ? 0 = the state machine is allowed to operate. ? 1 = reset the tx and rx state machines. setting this bit must be followed by a write of 0 before the state machine will operate. 12.8.9.12 reserved?bit 4?3 these bits are reserved or not implemented. they cannot be read or modified by writing. 12.8.9.13 frame sync reset (synrst)?bit 2 ? 0 = data must be read to be cleared from the registers. ? 1 = resets the accumulation of data in the srx register and rxfifo bit in frame synchronization. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-47 12.8.9.14 receive last slot interrupt enable (rlie)?bit 1 ? 0 = the receive last slot interrupt is disabled. ? 1 = an interrupt is generated after the last slot of a receive frame ends when the essi is in the network mode. the interrupt occurs regardless of the receive mask register setting. note: the rlie bit is disabled when dc = 00. 12.8.9.15 transmit last slot interrupt enable (tlie)?bit 0 ? 0 = the transmit last slot interrupt is disabled. ? 1 = an interrupt is generated at the beginning of the last slot of a transmit frame when the essi is in the network mode. the interrupt occurs regardless of the transmit mask register setting. note: the tlie bit is disabled when dc = 00. 12.8.10 essi control register 4 (scr4) the essi control register 4 (scr4) is one of five, 16-bit, read/write control registers used to direct the operation of the essi. the scr4 controls the configuration of the essi i/o pins and specifies the values of the output flag controls. the power-on reset (por) clears all of the scr4 bits. the essi reset (essien = 0) does not affect the scr4 bits. the scr4 bits are discussed in the following paragraphs. figure 12-24. essi control register 4 (scr4) see programmer?s sheet on appendix page b - 76 12.8.10.1 reserved?bits 15?11 these bits are reserved or not implemented. they cannot be read nor modified by writing. 12.8.10.2 transmit status flag control 0 (txsf0)?bit 10 ? 0 = the indicated transmitter does not affect the status bits. ? 1 = the indicated transmitter status will affect the tff, tde, tue, and tfe status bits. the status from all selected transmitters is ored to create the register status bit. these bits should be set to match the intended operation of the te0, te1, and te2 control bits. base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read txsf0 txsf1 txsf2 0 ssc1 sckd scd2 scd1 scd0 of1 of0 write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-48 freescale semiconductor 12.8.10.3 transmit status flag control 1 (txsf1)?bit 9 ? 0 = the indicated transmitter does not affect the status bits. ? 1 = the indicated transmitter status will affect the tff, tde, tue, and tfe status bits. the status from all selected transmitters is ored to create the register status bit. these bits should be set to match the intended operation of the te0, te1, and te2 control bits. 12.8.10.4 transmit status flag control 2 (txsf2)?bit 8 ? 0 = the indicated transmitter does not affect the status bits. ? 1 = the indicated transmitter status will affect the tff, tde, tue, and tfe status bits. the status from all selected transmitters is ored to create the register status bit. these bits should be set to match the intended operation of the te0, te1, and te2 control bits. 12.8.10.5 reserved?bit 7 this bit is reserved or not implemented. it is read as, and written with a 0. 12.8.10.6 select sc1 (ssc1)?bit 6 this bit controls the functionality of the sc1 signal. this control bit is used only if syn = 1 and te2 = 0. ? 0 = the sc1 acts as the serial i/o flag (if1/of1). ? 1 = when configured as an output (scd1 = 1), the sc1 signal acts as the transmitter 0 driver-enable, enabling an external buffer for the transmitter 0 output. note: if ssc1 = 1 and scd1 = 0, the configuration is invalid. 12.8.10.7 clock source direction (sckd)?bit 5 this bit configures the source of the clock signal used to clock the transmit shift register in asynchronous mode and both transmit and receive shift registers are in synchronous mode. ? 0 = sck pin is configured as an input. this pin is used as the clock source. ? 1 = internal transmit clock generator is selected. this clock is output on the sck pin. 12.8.10.8 serial control direction 2 (scd2)?bit 4 this bit controls the direction of the sc2 pin. ? 0 = sc2 is an input. ? 1 = sc2 is an output. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-49 12.8.10.9 serial control direction 1 (scd1)?bit 3 this bit controls the direction of the sc1 pin depending on the state of other controls as shown in table 12-15 . ? 0 = sc1 is an input ? 1 = sc1 is an output 12.8.10.10 serial control direction 0 (scd0)?bit 2 this bit controls the direction of the sc0 pin depending on the state of other controls as shown in table 12-16 . ? 0 = sc0 is an input ? 1 = sc0 is an output 12.8.10.11 serial output flag 1 (of1)?bit 1 when sc1 is configured for output flag functionality, data provided in table 12-15 , this control bit determines the state of the output pin. changes in the of1 bit will appear on the sc1 pin at the beginning of the next frame in the normal mode, or at the beginning of the next time slot in the network mode. table 12-15. control modes where scd1 is used syn te2 functional state 0 x scd1 control direction of sc1 1 0 sc1 is used as flag 1 where scd1 determines whether it is an output flag or an output flag 1 1 sc1 is an output table 12-16. control modes where scd0 is used syn te2 functional state 0 x scd0 control direction of sci0 1 0 sc0 is used as flag 0 where scd0 determines whether it is an output flag or an output flag 1 1 sc0 is an output register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-50 freescale semiconductor 12.8.10.12 serial output flag 0 (of0)?bit 0 when sc0 is configured for output flag functionality, provided in table 12-16 , this control bit determines the state of the output pin. changes in the of0 bit will appear on the sc0 pin at the beginning of the next frame in the normal mode, or at the beginning of the next time slot in the network mode. 12.8.11 essi transmit and receive control registers (stxcr, srxcr) the stxcr and srxcr are 16-bit, read/write control registers used to direct the operation of the essi. these registers control the essi clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. please refer to figure 12-35 to better understand how these fields are used in the clock generators. the stxcr register is dedicated to the transmit section. the srxcr register is dedicated to the receive section, except in the synchronous mode where the stxcr register controls both the receive and transmit sections. power-on reset (por) clears all stxcr and srxcr bits. the essi reset (essien = 0) does not affect the stxcr and srxcr bits. the control bits are described in the essi transmit control register (stxcr). figure 12-25. essi transmit control register (stxcr) see programmer?s sheet on appendix page b - 78 figure 12-26. essi receive control register (srxcr) see programmer?s sheet on appendix page b - 78 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read psr wl dc pm write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read psr wl dc pm write reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-51 12.8.11.1 prescaler range (psr)?bit 15 this bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. it extends the range of the prescaler for those cases where a slower bit clock is desired. ? 0 = when the psr bit is cleared, the fixed prescaler is by-passed. ? 1 = when the psr bit is set, the fixed divide-by eight prescaler is operational. this allows a 128khz master clock to be generated for mc1440x series codecs. the maximum internally generated bit clock frequency is f ip_clk /(2 2) and the minimum internally generated bit clock frequency is f ip_clk /(4 2 8 256 2) . 12.8.11.2 word length control (wl)?bits 14?13 these bits are used to select the length of the data words being transferred by the essi. word lengths of 8, 10, 12, or 16 bits can be selected. table 12-17 denotes the wl two-bit field encoding. these bits control the word length divider shown in the essi clock generator. the wl control bit also controls the frame sync pulse length when the tfsl (or rfsl) bit is cleared. 12.8.11.3 frame rate divider control (dc)?bits 12?8 this bit field controls the divide ratio for the programmable frame rate dividers. the divide ratio operates on the word clock. in the normal mode, this ratio determines the word transfer rate. the divide ratio ranges from 1 to 32 (dc[4:0] = 00000 to 11111) in the normal mode. a divide ratio of one (dc = 00000) provides continuous periodic data word transfer. a bit-length sync must be used in this case. in the network mode, this ratio sets the number of words per frame. the divide ratio ranges from 2 to 32 (dc[4:0] = 00001 to 11111) in the network mode. a divide ratio of one (dc = 00000) in the network mode is a special case (on demand mode) not supported. table 12-17. wl encoding wl number of bits/word 00 8 01 10 10 12 11 16 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-52 freescale semiconductor 12.8.11.4 prescaler modulus select (pm)?bits 7?0 this bit field specifies the divide ratio of the prescale divider in the essi clock generator. this prescaler is used only in internal clock mode to divide the internal peripheral clock. a divide ratio from 1 to 256 (pm = $00 to $ff) can be selected. the bit clock output is available at the sck or sc0 clock pins. the bit clock on the essi can be calculated from the peripheral clock value using the following equation: f fix_clk = f ipbus_clk/4 if div4dis = 0 f fix_clk = f ipbus_clk if div4dis = 1 f int_bit_clk = f fix_clk /[4 x (7 x psr + 1) x (pm + 1)] f frame_syn_clk = (f int_bit_clk )/[(dc + 1) x wl] where dc = dc and wl = 8, 10, 12, or 16 for example if an 8khz sampling rate is desired, with 8-bit words operating in the normal mode, the following parameters can be used: f ipbus_clk = f system_clk /2 = 120mhz / = 60mhz f fix_clk = f ipbus_clk = 60mhz div4dis = 1 f int_bit_clk = f fix_clk /[4 x(7 x psr + 1)x(pm + 1)] = 60 mhz /[4 x 1 x 117] = 128.2khz ps = 0, pm = 116 f frame_syn_clk = (f int_bit_clk) /[(dc + 1) x wl] dc = 1 = 128khz/[2 x 8] = 8.012khz the bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers. careful choice of the crystal oscillator frequency and the prescaler modulus provides the telecommunication industry standard codec master clock frequencies of 2.048mhz and 1.536mhz to be generated; however, such applications will typically use external clocks and frame syncs. table 12-18 provides examples of pm, psr, and div4dis values available to be used to generate different bit clocks. register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-53 12.8.12 time slot register (stsr) this register is used when data is not to be transmitted in an available transmit time slot, determined by the tsm registers. for the purposes of timing, the time slot register is a write-only register behaving like an alternate transmit data register, except instead of transmitting data, the std pin signal is tri-stated. using this register is important in avoiding overflow/underflow during inactive time slots. figure 12-27. essi time slot register (stsr) see programmer?s sheet on appendix page b - 79 table 12-18. chip clock rates as a function of essi bit clock frequency and prescale modulus frame rate words/frame (dc+1) bits/ word bit clock rate (hz) pm psr fix_clk rate div4dis ip_clk rate 1 1. shaded cells denote configuration where the required clock rate is higher than the chip specification can support. sys_clk rate 2 2. ip_clk is 1/2 the sys_clk rate. 8000 32 8 2,048,000 6 0 57,344,000 1 57,344,000 114,688,000 8000 32 8 2,048,000 7 0 65,536,000 1 65,536,000 131,072,000 8000 24 8 1,536,000 8 0 55,296,000 1 55,296,000 110,592,000 8000 24 8 1,536,000 9 0 61,440,000 1 61,440,000 125,880,000 8000 2 10 160,000 10 1 56,320,000 1 56,320,000 112,640,000 8000 2 10 160,000 11 1 61,440,000 1 61,440,000 122,880,000 8000 2 10 160,000 22 0 14,720,000 0 58,880,000 117,760,000 8000 2 10 160,000 92 0 59,520,000 1 59,520,000 119,040,000 8000 2 10 160,000 93 0 60,160,000 1 60,160,000 120,320,000 8000 2 12 192,000 8 1 55,296,000 1 55,296,000 110,592,000 8000 2 12 192,000 9 1 61,440,000 1 61,440,000 122,880,000 8000 2 12 192,000 18 0 14,593,000 0 58,368,000 116,736,000 8000 2 12 192,000 77 0 59,904,000 1 59,904,000 119,808,000 8000 2 12 192,000 78 0 60,672,000 1 60,672,000 120,344,000 8000 2 16 256,000 6 1 57,344,000 1 57,344,000 114,688,000 8000 2 16 256,000 7 1 65,536,000 1 65,536,000 131,072,000 8000 2 16 256,000 13 0 14,336,000 0 57,344,000 116,736,000 8000 2 16 256,000 57 0 59,904,000 1 59,904,000 118,784,000 8000 2 16 256,000 58 0 60,416,000 1 60,416,000 120,832,000 base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write dummy register written during inactive time slots (network mode) reset x x x x x x x x x x x x x x x x register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-54 freescale semiconductor 12.8.13 essi fifo control/status register (sfcsr) this register allows configuration of the transmit and receive fifo registers, and allows reporting of the amount of data contained in each fifo . figure 12-28. essi fifo control/status register (sfcsr) see programmer?s sheet on appendix page b - 80 12.8.13.1 receive fifo counter (rfcnt)?bits 15?12 this read-only bit field indicates the number of data words in the rxfifo. table 12-19 demonstrates the rfcnt bit field encoding. 12.8.13.2 transmit fifo counter (tfcnt)?bits 11?8 this read-only bit field indicates the number of data words in the txfifo. table 12-20 illustrates the tfcnt bit field encoding. the specific fifo reported on is determined by the first txsfn control bit enabled; that is to say, if txsf0 is set, the number of data words in txfifo0 is reported. when more than one transmitter is enabled, the tf1err and tf2err status bits will indicate any counter mismatches, described in section 12.8.7 . base +$b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rfcnt tfcnt rfwm tfwm write reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 table 12-19. rfcnt encoding bits description 0000 0 data words in rxfifo 0001 1 data words in rxfifo 0010 2 data words in rxfifo 0011 3 data words in rxfifo 0100 4 data words in rxfifo 0101 5 data words in rxfifo 0110 6 data words in rxfifo 0111 7 data words in rxfifo 1000 8 data words in rxfifo register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-55 note: while loading the transmit data registers the fifo counts may temporarily not match so the count status bits should only be checked after a complete set of writes to the transmit data registers. 12.8.13.3 receive fifo full watermark (rfwm)?bits 7?4 this bit field controls the threshold the receive fifo full (rff) flag will be set. rff is set whenever the data level in the rxfifo reaches the selected threshold. for example, if rfwm = 1, rff will be set after the essi receives 2 data words (one in srx and the other in rxfifo). table 12-22 shows the status of rff for all data levels of the rxfifo table 12-20. tfcnt encoding bits description 0000 0 data words in txfifo 0001 1 data words in txfifo 0010 2 data words in txfifo 0011 3 data words in txfifo 0100 4 data words in txfifo 0101 5 data words in txfifo 0110 6 data words in txfifo 0111 7 data words in txfifo 1000 8 data words in txfifo table 12-21. rfwm encoding bits description 0000 reserved 0001 rff set when at least 1data word has been written to the rxfifo. set when rxfifo = 1, 2, 3, 4, 5, 6, 7, or 8 data words 0010 rff set when 2 or more data words have been written to the rxfifo. set when rxfifo = 2, 3, 4, 5, 6, 7, or 8 data words 0011 rff set when 3 or more data words have been written to the rxfifo. set when rxfifo = 3, 4, 5, 6, 7, or 8 data words 0100 rff set when 4 or more data words have been written to the rxfifo. set when rxfifo = 4, 5, 6, 7, or 8 data words 0101 rff set when 5 or more data words have been written to the rxfifo. set when rxfifo = 5, 6, 7, or 8 data words 0110 rff set when 6 or more data words have been written to the rxfifo. set when rxfifo = 6, 7, or 8 data words 0111 rff set when 7 or more data words have been written to the rxfifo. set when rxfifo = 7, or 8 data words 1000 rff set when 8 or more data words have been written to the rxfifo. set when rxfifo = 8 data words register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-56 freescale semiconductor 12.8.13.4 transmit fifo empty watermark (tfwm)?bits 3?0 this bit field controls the threshold where the transmit fifo empty (tfe) flag is set. tfe is set whenever the data level in the txfifo falls below the selected threshold. table 12-23 shows the status of tfe for all data levels of the txfifo. table 12-22. status of receive fifo full flag receive fifo watermark (rfwm) number of data in rxfifo 012345678 1 011111111 2 001111111 3 000111111 4 000011111 5 000001111 6 000000111 7 000000011 8 000000001 table 12-23. tfwm encoding bits description 0000 reserved 0001 tfe set when there is 1empty slot in txfifo. (default) transmit fifo empty is set when txfifo <= 7 data 0010 tfe set when there are 2 or more empty slots in txfifo. transmit fifo empty is set when txfifo <= 6 data 0011 tfe set when there are 3 or more empty slots in txfifo. transmit fifo empty is set when txfifo <= 5 data 0100 tfe set when there are 4 or more empty slots in txfifo. transmit fifo empty is set when txfifo <= 4 data 0101 tfe set when there are 5 or more empty slots in txfifo. transmit fifo empty is set when txfifo <= 3 data 0110 tfe set when there are 6 or more empty slots in txfifo. transmit fifo empty is set when txfifo <= 2 data 0111 tfe set when there are 7 or more empty slots in txfifo. transmit fifo empty is set when txfifo <= 1 data 1000 tfe set when there are 8 or more empty slots in txfifo. transmit fifo empty is set when txfifo <= 0 data register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-57 12.8.14 transmit slot mask registers (tsma, tsmb) the transmit slot mask registers are two 16-bit read/write registers. in the network mode, these registers are used by the transmitter to determine which action to take in the current transmission slot. depending on the setting of the bits, the transmitter either tri-states the transmitter data signal or transmits a data word and generates the appropriate transmit status. tsma and tsmb can be viewed as a single 32-bit register named tsm. bit n in tsm (tsmn) is an enable/disable control bit for transmission in slot n . figure 12-29. transmit sl ot mask register (tsma) see programmer?s sheet on appendix page b - 82 figure 12-30. transmit sl ot mask register (tsmb) see programmer?s sheet on appendix page b - 82 ? 0 = the transmit data signal of the transmitter is tri-stated during transmit time slot n . data is not transferred to the txsr, therefore transmit status flags are not changed. table 12-24. status of tr ansmit fifo empty flag transmit fifo watermark (tfwm) number of data in txfifo 012345678 1 111111111 2 111111100 3 111111000 4 111110000 5 111100000 6 111000000 7 110000000 8 100000000 base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tsma [15:0] write reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tsmb [31:16] write reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 register descriptions (essi0_base = $1ffe20, essi1_base = $1ffe00) 5685x digital signal controller user manual, rev. 4 12-58 freescale semiconductor ? 1 = the transmit sequence proceeds normally. data is transferred from the stx register (or txfifo, if enabled) to the shift register during slot n . appropriate flags are set. the dsc is interrupted only for enabled slots. data written to the stx register when the transmitter empty (or transmit fifo empty) interrupt request is being serviced is transmitted in the next enabled transmit time slot. the tsm slot mask does not conflict with the stsr. even if a slot is enabled in the tsm register, the user may choose to write to the stsr to tri-state the signals of the enabled transmitters during the next transmission slot. setting the bits in the tsm register affects the next frame transmission. the frame currently being transmitted is not affected by the new tsm setting. if the tsm is read, it shows the current setting. an essi reset (essien = 0) does not affect the contents of the tsm registers. after a hardware reset signal, or executing a software reset instruction, the tsm register is reset to $ffffffff; that value enables all 32 slots for data transmission. the transmit dc setting determines how many of these control bits is actually used. 12.8.15 receive slot mask registers (rsma, rsmb) the receive slot mask registers are two 16-bit read/write registers. in the network mode, these registers are used by the receiver to determine which action to take in the current time slot. depending on the setting of the bits, the receiver either ignores the receiver data signal(s), or receives a data word, generating the appropriate receive status. rsma and rsmb can be viewed as one 32-bit register, rsm. bit n in rsm (rsmn) is an enable/disable control bit for time slot n . figure 12-31. receive slot mask register (rsma) see programmer?s sheet on appendix page b - 83 figure 12-32. receive slot mask register (rsmb) see programmer?s sheet on appendix page b - 83 base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rsma [15:0] write reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 base + $f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rsmb [31:16] write reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 clocks enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-59 ? 0 = data is not transferred from the receive shift register (rxsr) to the receive data (srx) register, therefore the rdr and roe flags are not set. ? 1 = the receive sequence proceeds normally. data is received during slot n , and the rdr flag is set. during a disabled slot, no receiver full interrupt is generated. the dsc is interrupted only for enabled slots. when the bits in the rsm are changed, their settings affect the next frame reception. the frame currently being received is not affected by the new rsm setting. if the rsm is read, it shows the current setting. an essi reset (essien = 0) does not affect the contents of the tsm registers. after a hardware reset signal or executing a software reset instruction, the rsm register is reset to $ffffffff; that value enables all 32-time slots for data reception. the receive dc setting determines how many of these control bits are actually used. 12.9 clocks the essi uses the following three clocks, illustrated in figure 12-33 and figure 12-34 : ? bit clock?used to serially clock the data bits in and out of the essi port ? word clock?used to count the number of data bits per word (8, 10, 12, or 16 bits) ? frame clock?used to count the number of words in a frame the bit clock is used to serially clock the data. the clock is visible on the sck, for asynchronous transmit or synchronous modes and sc0, for asynchronous receive clock operation pins. the word clock is an internal clock used to determine when transmission of an 8, 10, 12, or 16 bit word has completed. the word clock in turn then clocks the frame clock, which marks the beginning of each frame. the frame clock can be viewed on the sc2 and sc1 pins. the bit clock can be received from an essi clock pin or can be generated from the peripheral clock passed through a divider, illustrated in figure 12-35 . figure 12-33. essi clocking (8-bit words, 3 time slots / frame) ts0 ts1 ts2 ts0 ts1 ts2 frame n frame n+1 word_clock data (sck, sc0) (sc2, sc1) clock operation description 5685x digital signal controller user manual, rev. 4 12-60 freescale semiconductor figure 12-34. essi clock generation 12.10 clock operation description 12.10.1 essi clock and frame sync generation data clock and frame sync signals can be generated internally by the essi or can be obtained from external sources. if internally generated, the essi clock generator is used to derive bit clock and frame sync signals from the peripheral clock. the essi clock generator consists of a selectable, fixed prescaler and a programmable prescaler for bit rate clock generation. a programmable frame rate divider and a word length divider are used for frame rate sync signal generation. table 12-25. clock summary clock source characteristics sck internal/ external transmit data is changed on the rising edge of this clock. the rsckp bit of the scr2 register can invert the clock if required. sc0 internal/ external receive data is captured on the falling edge of this clock. the rsckp bit of the scr3 register can invert the clock if required. sc2 internal/ external transmit frames begin with the rising edge of this signal. see the definition of the tefs bit of the scr2 register for timing options. the tfsi bit can invert this signal if required. sc1 internal/ external receive frames begin with the rising edge of this signal. see the definition of the refs bit of the scr3 register for timing options. (sc2, sc1) serial bit clock word divider (/8, /10, /12, /16) word clock frame divider (/1 to /32) frame clock (sck, sc0) clock operation description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-61 figure 12-35. essi transmit clock generator block diagram figure 12-36 demonstrates the frame sync generator block for the transmit section. when internally generated, both receive and transmit frame sync are generated from the word clock and are defined by the frame rate divider (dc) field bits and the word length (wl) field bits of the essi transmit data control register (stxcr). the receive section contains an equivalent circuit for its frame sync generator. figure 12-36. essi transmit frame sync generator block diagram /2 ip_clk prescaler (/1 or /8) divider (/1 to /256) /2 sckd (1=output) sckd (0=input) serial bit clock sckd (1=output) word length divider word clock wl[1:0] psr pm[7:0] /4 div4dis fix_clk sck frame rate dc[4:0] frame sync tfsl tx control tfsi tfsi tx frame sync out tx frame sync in word clock sc2 resets 5685x digital signal controller user manual, rev. 4 12-62 freescale semiconductor 12.11 resets the essi is affected by power-on reset (por) and essi reset. por is generated by asserting either the reset pin or the (cop) timer reset. the por initializes all control registers and clears the essien bit in scr2 and disables the essi. the essi reset is generated when the essien bit in the scr2 is cleared. the essi status bits are preset to the same state produced by the por. the essi control bits are unaffected. the essi reset is useful for selective reset of the essi without changing the present essi control bits and without affecting the other peripherals. the correct sequence to initialize the essi is as follows: 1. issue a power-on or essi reset. 2. program the essi control registers. 3. set the essien bit in scr2. 4. write data to the stx register(s). 5. enable transmit and receive operations. this procedure ensures proper operation of the essi by using the power-on reset (por) or essi reset before changing any of the control bits listed in table 12-26 . these control bits should not be changed during essi operation. note: the essi bit clock must go low for at least one complete period to ensure proper essi reset. table 12-26. essi control bits requiring reset before change control register bit srxcr stxcr psr wl[1:0] dc[4:0] pm[7:0] scr2 tefs tfsl tfsi net tsckp tshfd syn interrupt operation description enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-63 12.12 interrupts the essi can generate up to six interrupt vectors, listed in table 12-27 . 12.13 interrupt operation description 12.13.1 receive data with exception this interrupt can occur when receive interrupts are enabled via the rie bit of the scr2 register. when a data word is ready to transfer from the rxsr register to the srx register and the previous srx register data has not yet been read, the roe bit is set and the exception interrupt will occur instead of the normal receive data interrupt. when the receive fifo is enabled this interrupt will not occur until the rff bit has been set, indicating the fifo is full. the roe bit is cleared when the ssr is read verifying the roe bit is set before reading the srx register data. scr3 tfen rfen refs rfsl rfsi rsckp rshfd div4dis scr4 scd0 scd1 scd2 sdkd ssc1 table 12-27. interrupt summary interrupt source description intr + $0 receiver receive data with exception intr + $2 receiver receive data intr + $4 receiver receive last slot interrupt. this interrupt may not be present in all implementations of the essi. intr + $6 transmitter transmit data with exception intr + $8 transmitter transmit data intr + $10 transmitter transmit last slot interrupt. this interrupt may not be present in all implementations of the essi. table 12-26. essi control bits requiring reset before change (continued) control register bit interrupt operation description 5685x digital signal controller user manual, rev. 4 12-64 freescale semiconductor 12.13.2 receive data (rx) this interrupt can occur when receive interrupts are enabled via the rie bit of the scr2 register. when a data word is ready to transfer from the rxsr register to the srx register, and the roe bit is not set, an interrupt will occur indicating received data is available for processing. when the receive fifo is enabled, this interrupt will not occur until the receive watermark level of the fifo is reached. if the fifo is not enabled, an interrupt will occur for each data word received. this interrupt is cleared by reading the ssr, verifying the rdr bit is set before reading the srx register data. 12.13.3 receive last slot (rls) this interrupt occurs when the essi: ? is in the network mode ? has been enabled via the rlie bit of the scr3 register ? the last slot of the frame has ended the rls bit is also set at this time. this interrupt is generated regardless of the receive mask register setting. this interrupt and the rls bit are cleared by writing 1 to the rls bit of the essi status register (ssr). 12.13.4 transmit data with exception this interrupt can occur when transmit interrupts are enabled via the tie bit of the scr2 register. when it is time to transfer data to the txsr and data is not available in enabled stx or txfifo, the tue status bit is set and the transmit data exception interrupt occurs. the tue bit, and its interrupt, is cleared when the ssr is read then written to all the transmit data registers of the enabled transmitters or when written to the stsr. 12.13.5 transmit data (tx) this interrupt can occur when transmit interrupts are enabled via the tie bit of the scr2 register. when data is transferred to the txsr this interrupt will occur if more data is needed by any enabled transmitter. if the transmit fifo is not enabled this interrupt will occur for each data word transmitted. however, when the transmit fifo is enabled, the interrupt will not occur until the transmit watermark level is reached. this interrupt is cleared by reading the ssr and writing data to the enabled stx registers. the interrupt may also be cleared by writing to the stsr. user notes enhanced synchronous serial interface (essi), rev. 4 freescale semiconductor 12-65 12.13.6 transmit last slot (tls) this interrupt occurs when the essi is in the network mode at the beginning of the last slot of the transmit frame. the tls bit is also set at this time. this exception occurs regardless of the transmit mask register setting. this interrupt and the tls bit are cleared by writing 1 to the tls bit of the ssr. 12.14 user notes 12.14.1 external frame sync setup when using external frame syncs, there must be at least four clocks after enabling the transmitter/receiver and before the first frame sync. 12.14.2 maximum external clock rate the maximum allowable rate for an external clock source is one fourth of the peripheral clock. user notes 5685x digital signal controller user manual, rev. 4 12-66 freescale semiconductor quad timer (tmr), rev. 4 freescale semiconductor 13-1 chapter 13 quad timer (tmr) 5685x digital signal controller user manual, rev. 4 13-2 freescale semiconductor features quad timer (tmr), rev. 4 freescale semiconductor 13-3 13.1 introduction the quad timer (tmr) module contains four identical counter/timer groups. each 16-bit counter/timer group contains a ? prescaler ? counter ? load register ? hold register ? capture register ? two compare registers ? two status and control registers all except the prescaler are read/write registers. note: this document uses the terms timer and counter interchangeably because the counter/timers may perform either or both tasks. the load register provides the initialization value to the counter when the counter?s terminal value has been reached. hold registers capture the counter?s value the instant any counter register is read. this feature supports the reading of cascaded counters. the capture register enables an external signal to take a snapshot of the counter?s current value. the tmr_cmp1 and tmr_cmp2 registers provide the values to which the counter is compared. if a match occurs, the oflag signal can be set, cleared, or toggled. at match time, an interrupt is generated if enabled. the prescaler provides different ipbus clock time bases useful for clocking the counter. the counter provides the ability to count internal or external events. input pins are shared within a timer module. 13.2 features the quad tmr module design includes these distinctive capabilities: ? four, 16-bit counters/timers ? count up/down ? counters are cascadable ? count modulo can be programmed ? maximum count rate equals peripheral clock for external clocks ? maximum count rate equals peripheral clock for internal clocks ? count once or repeatedly ? counters can be preloaded operatng modes 5685x digital signal controller user manual, rev. 4 13-4 freescale semiconductor ? counters can share available input pins ? separate prescaler for each counter ? each counter has capture and compare capability 13.3 operatng modes the tmr module design operates in only the functional mode. various counting modes are detailed in functional description , section 13.6 . 13.4 block diagram block diagram of the quad tmr module is illustrated in figure 13-1 . figure 13-1. tmr module block diagram 13.5 signal description the tmr module has four external signals tio[3:0] with the capability to be used as either inputs or outputs. 13.6 functional description the counter/timer has two basic modes of operation: 1. count internal or external events 2. count an internal clock source while an external input signal is asserted, thus timing the width of the external input signal prescaler mux counter status & control counter load hold capture cmp1 cmp2 comparator mux oflag output data bus inputs other counters comparator counting modes definitions quad timer (tmr), rev. 4 freescale semiconductor 13-5 the counter can count the rising, falling, or both edges of the selected input pin. the counter can decode and count quadrature encoded input signals. the counter can count up and down using dual inputs in a count with direction format. the counter?s terminal count value (modulo) is programmable. the value loaded into the counter after reaching its terminal count is programmable. the counter can count repeatedly, or it can stop after completing one count cycle. the counter can be programmed to count to a programmed value and then immediately reinitialize, or it can count through the compare value until the count rolls over to zero. the external inputs to each counter/timer can be shared among each of the four counter/timers within the module. the external inputs can be used as: ? count commands ? timer commands ? trigger current counter value to be captured ? generate interrupt requests the polarity of the external inputs can be selected. for this implementation of the timer (tmr), there are four input pins. the primary output of each timer/counter is the output signal, oflag. the oflag output signal can be set, cleared, or toggled when the counter reaches the programmed value. the oflag output signal may be output to an external pin shared with an external input signal (tiox). the oflag output signal enables each counter to generate square waves (pwm) or pulse stream outputs. the polarity of the oflag output signal is selectable. any counter/timer can be assigned as a master (mstr). a master?s compare signal can be broadcasted to the other counter/timers within the module. the other counters can be configured to reinitialize their counters and/or force their oflag output signals to predetermined values when a master?s counter/timer compare event occurs. 13.7 counting modes definitions the selected external count signals are sampled at the tmr?s base clock rate (60mhz) and then run through a transition detector. the maximum count rate is one-half of the base peripheral clock rate. internal clock sources can be used to clock the counters at the peripheral clock rate. if a counter is programmed to count to a specific value and then stop, the count mode in the tmr_ctrl register is cleared when the count terminates. 13.7.1 stop mode if the count mode field is set to 000, the counter is inert. no counting will occur. counting modes definitions 5685x digital signal controller user manual, rev. 4 13-6 freescale semiconductor 13.7.2 count mode if the count mode field is set to 001, the counter will count the rising edges of the selected clock source. this mode is useful for generating periodic interrupts for timing purposes, or counting external events such as widgets on a conveyor belt passing a sensor. if the selected input is inverted by setting the input polarity select (ips) bit, the negative edge of the selected external input signal is counted. 13.7.3 edge count mode if the count mode field is set to 010, the counter will count both edges of the selected external clock source. this mode is useful for counting the changes in the external environment such as a simple encoder wheel. 13.7.4 gated count mode if the count mode field is set to 011, the counter will count while the selected secondary input signal is high. this mode is used to time the duration of external events. if the selected input is inverted by setting the input polarity select (ips) bit, the counter will count while the selected secondary input is low. 13.7.5 quadrature count mode when the count mode field is set to 100, the counter will decode the primary and secondary external inputs as quadrature encoded signals. quadrature signals are usually generated by rotary or linear sensors used to monitor movement of motor shafts or mechanical equipment. the quadrature signals are square waves, 90 degrees out-of-phase. the decoding of quadrature signal provides both count and direction information. a timing diagram illustrating the basic operation of a quadrature incremental position encoder is provided in figure 13-2 . figure 13-2. quadrature incremental position encoder -1 -1 -1 -1 -1 -1 -1 phasea count phaseb up/dn +1 +1 +1 +1 +1 +1 +1 +1 counting modes definitions quad timer (tmr), rev. 4 freescale semiconductor 13-7 13.7.6 signed count mode if the count mode field is set to 101, the counter counts the primary clock source while the selected secondary source provides the selected count direction (up/down). 13.7.7 triggered count mode if the count mode field is set to 110, the counter will begin counting the primary clock source after a positive transition (negative edge if ips = 1) of the secondary input occurs. the counting will continue until a compare event occurs, or another positive input transition is detected. if a second input transition occurs before a terminal count was reached, counting will stop. subsequent odd numbered edges of the secondary input will restart counting, while even numbered edges will stop counting. this will continue until a compare event occurs. 13.7.8 one-shot mode this is a sub mode of triggered event count mode if the count mode field is set to 110 while: ? count length (length) is set ? oflag output mode is set to 101 ? once bit of the control (ctrl) register is set to 1 in the above setting, the counter works in a one-shot mode. an external event causes the counter to count. when terminal count is reached, the oflag output is asserted. this delayed output assertion can be used to provide timing delays. 13.7.9 cascade count mode if the count mode field is set to 111, the counter?s input is connected to the output of another selected counter. the counter will count up and down as compare events occur in the selected source counter. this cascade or daisy chained mode enables multiple counters to be cascaded in order to yield longer counter lengths. when operating in the cascade mode, a special high speed signal path is used not using the oflag output signal. if the selected source counter is counting up, and it experiences a compare event, the counter will be incremented. if the selected source counter is counting down and it experiences a compare event, the counter will be decremented. up to four counters may be cascaded to create a 64-bit wide synchronous counter. whenever any counter is read within a counter module, all of the counters? values within the module are captured in their respective hold registers. this action supports the reading of a cascaded counter chain. first read any counter of a cascaded counter chain, then read the hold registers of the other counters in the chain. the cascaded counter mode is synchronous. note: it is possible to connect counters together by using the other (non-cascade) counter modes and selecting the outputs of other counters as a clock source. in this case, the counting modes definitions 5685x digital signal controller user manual, rev. 4 13-8 freescale semiconductor counters are operating in a ripple mode, where higher order counters will transition a clock later than a purely synchronous design. 13.7.10 pulse output mode the counter will output a pulse stream of pulses with the same frequency of the selected clock source (can not be ipbus clock divided by one) if the counter is setup for: ? count mode (mode = 001) ? the oflag output mode is set to 111 (gated clock output) ? the count once bit is set the number of output pulses is equal to the compare value minus the initial value. this mode is useful for driving step motor systems. note: primary count source must be set to one of the counter outputs for gated clock output mode. 13.7.11 fixed frequency pwm mode the counter output yields a pulse width modulated (pwm) signal with a frequency equal to the count clock frequency divided by 65,536. it has a pulse width duty cycle equal to the compare value divided by 65,536 if the counter is setup for: ? count mode (mode = 001) ? count through roll-over (count length = 0) ? continuous count (count once = 0) ? oflag output mode is 110 (set on compare, cleared on counter rollover) this mode of operation is often used to drive pwm amplifiers used to power motors and inverters. 13.7.12 variable frequency pwm mode if the counter is setup for: ? count mode (mode = 001) ? count till compare (count length = 1) ? continuous count (count once = 0) ? oflag output mode is 100 (toggle oflag and alternate compare registers) the counter output yields a pulse width modulated (pwm) signal whose frequency and pulse width is determined by the values programmed into the tmr_cmp1 and tmr_cmp2 registers, counting modes definitions quad timer (tmr), rev. 4 freescale semiconductor 13-9 and the input clock frequency. this method of pwm generation has the advantage of allowing almost any desired pwm frequency and/or constant on or off periods. this mode of operation is often used to drive pwm amplifiers used to power motors and inverters. 13.7.13 compare registers use the dual compare registers (tmr_cmp1 and tmr_cmp2) provide a bidirectional modulo count capability. the cmp1 register is used when the counter is counting up , and the cmp2 register is used when the counter is counting down . the only exception is when the counter is operating with alternating compare registers. the cmp1 register should be set to the desired maximum count value or $ffff to indicate the maximum unsigned value prior to roll-over, and the cmp2 register should be set to the maximum negative count value or $0000 indicating the maximum unsigned value prior to roll-under. if the output mode is set to 100, the oflag will toggle while using alternating compare registers. in this variable frequency pwm mode, the cmp2 value defines the desired pulse width of the on-time , and the cmp1 register defines the off-time . the variable frequency pwm mode is defined for positive counting only. one must be careful when changing cmp1 and cmp2 while the counter is active. if the counter has already passed the new value, it will count to $ffff or $0000, roll over/under, and then begin counting toward the new value. (the check is for count = cmpx, not count> = cmp1 or count < = cmp2). 13.7.14 capture register use the capture register stores a copy of the counter?s value when an input edge (positive, negative, or both) is detected. once a capture event occurs, no further updating of the capture register will occur until the input edge flag (ief) is cleared by writing 0 to the ief. module memory map 5685x digital signal controller user manual, rev. 4 13-10 freescale semiconductor 13.8 module memory map there are eight registers on the tmr peripheral described in table 13-1 . table 13-1. tmr module memory map (tmr_base = $1ffe80) address offset register acronym register name access type chapter location base + $0, $8, $10, $18 cmp1 timer channel compare register 1 read/write section 13.9.3 base + $1, $9, $11, $19 cmp2 timer channel compare register 2 read/write section 13.9.4 base + $2, $a, $12, $1a cap timer channel capture register read/write section 13.9.5 base + $3, $b, $13, $1b load timer channel load register read/write section 13.9.6 base + $4, $c, $14, $1c hold timer channel hold register read/write section 13.9.7 base + $5, $d, $15, $1d cntr timer channel counter register read/write section 13.9.8 base + $6, $e, $16, $1e ctrl timer channel control register read/write section 13.9.1 base + $7, $f, $17, $f scr timer channel status/control reg. read/write section 13.9.2 add. offset register name 151413121110987654321 0 $0, $8, $10, $18 cmp1 r comparison value w $1, $9, $11, $19 cmp2 r comparison value w $2, $a, $12, $1a cap r capture value w $3, $b, $13, $1b load r load value w $4, $c, $14, $1c hold r hold value w $5, $d, $15, $1d cntr r counter w $6, $e, $16, $1e ctl r cm pcs scs once length dir ext init om (oflag) w $7, $f, $17, $1f scr r tcf tcfie tof tofie ief iefie ips input capture mode mstr eeof val ops oen force r 0 read as 0 w reserved figure 13-3. tmr register map summary register descriptions (tmr_base = $1ffe80) quad timer (tmr), rev. 4 freescale semiconductor 13-11 13.9 register descriptions (tmr_base = $1ffe80) 13.9.1 timer control registers (ctl) there are four timer control registers in this occurrence. their addresses are: tmra0_ctrl (timer a, channel 0 control)?address: tmra_base + $6 tmra1_ctrl (timer a, channel 1 control)?address: tmra_base + $e tmra2_ctrl (timer a, channel 2 control)?address: tmra_base + $16 tmra3_ctrl (timer a, channel 3 control)?address: tmra_base + $1e figure 13-4. tmr control register (ctl) see programmer?s sheet on appendix page b - 90 13.9.1.1 count mode (cm)?bits 15?13 these bits control the basic counting behavior of the counter. ? 000 = no operation ? 001 = count rising edges of primary source 1 ? 010 = count rising and falling edges of primary source ? 011 = count rising edges of primary source while secondary input high active 1 ? 100 = quadrature count mode, uses primary and secondary sources ? 101 = count rising edges of primary source; secondary source specifies direction (1 = minus) 1 ? 110 = edge of secondary source triggers primary count until compare ? 111 = cascaded counter mode (up/down) 2 13.9.1.2 primary count source (pcs)?bits 12?9 these bits select the primary count source. ? 0000 = counter 0 input pin (tio0) ? 0001 = counter 1 input pin (tio1) ? 0010 = counter 2 input pin (tio2) base + $6, $e, $16, $1e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read cm pcs scs once length dir ext init om (oflag) write reset 0000000000 0 00000 1. rising edges counted only when ips = 0. falling edges counted when ips = 1. 2. primary count source must be set to one of the counter outputs. register descriptions (tmr_base = $1ffe80) 5685x digital signal controller user manual, rev. 4 13-12 freescale semiconductor ? 0011 = counter 3 input pin (tio3) ? 0100 = counter 0 output pin (oflag0) ? 0101 = counter 1 output pin (oflag1) ? 0110 = counter 2 output pin (oflag2) ? 0111 = counter 3 output pin (oflag3) ? 1000 = prescaler (ipbus clock divide-by 1) ? 1001 = prescaler (ipbus clock divide-by 2) ? 1010 = prescaler (ipbus clock divide-by 4) ? 1011 = prescaler (ipbus clock divide-by 8) ? 1100 = prescaler (ipbus clock divide-by 16) ? 1101 = prescaler (ipbus clock divide-by 32) ? 1110 = prescaler (ipbus clock divide-by 64) ? 1111 = prescaler (ipbus clock divide-by 128) note: a timer selecting its own output for input is not a legal choice. the result is no counting. 13.9.1.3 secondary count source (scs)?bits 8?7 these bits provide additional information, such as direction used for counting. they also define the source used by both the capture mode bits and the input edge flag in the channel status and control register. ? 00 = counter 0 input pin (tio0) ? 01 = counter 1 input pin (tio1) ? 10 = counter 2 input pin (tio2) ? 11 = counter 3 input pin (tio3) 13.9.1.4 count once (once)?bit 6 this bit select continuous or one-shot counting mode. ? 0 = count repeatedly ? 1 = count till compare and then stop. if counting up, successful compare occurs when counter reaches cmp1 value. if counting down, successful compare occurs when counter reaches cmp2 value. register descriptions (tmr_base = $1ffe80) quad timer (tmr), rev. 4 freescale semiconductor 13-13 13.9.1.5 count length (length)?bit 5 this bit determines whether the counter counts to the compare value and then reinitializes itself, or the counter continues counting past the compare value (binary roll-over). ? 0 = roll-over ? 1 = count till compare, then reinstalled. if counting up, successful compare occurs when counter reaches cmp1 value. if counting down, successful compare occurs when counter reaches cmp2 value. 1 13.9.1.6 count direction (dir)?bit 4 this bit selects either the normal count-up direction, or the reverse down direction. ? 0 = count up ? 1 = count down 13.9.1.7 external initialization (ext init)?bit 3 this bit enables another counter/timer within the same module to force the re-initialization of this counter/timer when the other counter has an active compare event. ? 0 = external counter/timers can not force a re-initialization of this counter/timer. ? 1 = external counter/timers may force a re-initialization of this counter/timer. 13.9.1.8 output mode (om)?bits 2?0 these bits determine the mode of operation for the oflag output signal. ? 000 = asserted while counter is active ? 001 = clear oflag output on successful compare ? 010 = set oflag output on successful compare ? 011 = toggle oflag output on successful compare ? 100 = toggle oflag output using alternating compare registers ? 101 = set on compare, cleared on secondary source input edge ? 110 = set on compare, cleared on counter rollover ? 111 = enable gated clock output while counter is active 2 note: unexpected results may occur if the output mode field is set to use alternating compare registers (mode 100) and the count once bit is set. 1. when the output mode 0 4 is used, alternating values of cmp1 and cmp2 are used to generate successful compares. for example, when the output mode is 0 4, the counter counts until cmp1 value is reached, reinitializes, then counts until cmp2 value is reached, reinitialize s, then counts until cmp1 value is reached, and so on. 2. primary count source must be set to one of the counter outputs. register descriptions (tmr_base = $1ffe80) 5685x digital signal controller user manual, rev. 4 13-14 freescale semiconductor 13.9.2 timer channel status and control registers (scr) there are four timer status and control registers in this occurrence. their addresses are: tmra0_scr (timer a, channel 0 status and control)?address: tmra_base + $7 tmra1_scr (timer a, channel 1 status and control)?address: tmra_base + $f tmra2_scr (timer a, channel 2 status and control)?address: tmra_base + $17 tmra3_scr (timer a, channel 3 status and control)?address: tmra_base + $1f figure 13-5. tmr status and control register (scr) see programmer?s sheet on appendix page b - 93 13.9.2.1 timer compare flag (tcf)?bit 15 this bit is set when a successful compare occurs. clear the bit by writing 0 to it. 13.9.2.2 timer compare flag interrupt enable (tcfie)?bit 14 when set, this bit enables interrupts when the tcf bit is set. 13.9.2.3 timer overflow flag (tof)?bit 13 this bit is set when the counter rolls over its maximum value $ffff or $0000, depending on count direction. clear the bit by writing 0 to it. 13.9.2.4 timer overflow flag interrupt enable (tofie)?bit 12 when set, this bit enables interrupts when the tof bit is set. 13.9.2.5 input edge flag (ief)?bit 11 this bit is set when a positive input transition occurs while the counter is enabled. clear the bit by writing 0 to it. note: setting the input polarity select (ips) bit enables the detection of negative input edge transitions detection. also, the control register?s secondary count source determines which external input pin is monitored by the detection circuitry. 13.9.2.6 input edge flag interrupt enable (iefie)?bit 10 when set, this bit enables interrupts when the ief bit is set base + $7, $f, $17, $1f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tcf tcfie tof tofie ief iefie ips input capture mode mstr eeof val 0 ops oen write force reset 00000000 00000000 register descriptions (tmr_base = $1ffe80) quad timer (tmr), rev. 4 freescale semiconductor 13-15 13.9.2.7 input polarity select (ips)?bit 9 when set, this bit inverts the input signal polarity. 13.9.2.8 external input signal (input)?bit 8 this bit reflects the current state of the external input pin selected via the secondary count source after application of the ips bit. this is a read-only bit. 13.9.2.9 input capture mode (capture mode)?bits 7?6 these bits specify the operation of the capture register as well as the operation of the input edge flag. ? 00 = capture function is disabled ? 01 = load capture register on rising edge of input ? 10 = load capture register on falling edge of input ? 11 = load capture register on any edge of input 13.9.2.10 master mode (mstr)?bit 5 when set, this bit enables the compare function?s output to be broadcasted to the other counter/timers in the module. this signal then can be used to reinitialize the other counters and/or force their oflag signal outputs. 13.9.2.11 enable external oflag force (eeof)?bit 4 when set, this bit enables the compare from another counter/timer within the same module to force the state of this counters? oflag output signal. 13.9.2.12 forced oflag value (val)?bit 3 this bit determines the value of the oflag output signal when a software triggered force command occurs. 13.9.2.13 force oflag output (force)?bit 2 this write-only bit forces the current value of the val bit to be written to the oflag output. always read this bit as 0. the val and force bits can be written simultaneously in a single write operation. write to the force bit only if the counter is disabled. ? 0 = no action ? 1 = forces the current value of the val bit to be written to oflag output note: setting this bit while the counter is enabled may yield unpredictable results. register descriptions (tmr_base = $1ffe80) 5685x digital signal controller user manual, rev. 4 13-16 freescale semiconductor 13.9.2.14 output polarity select (ops)?bit 1 this bit determines the polarity of the oflag output signal. ? 0 = true polarity ? 1 = inverted polarity 13.9.2.15 output enable (oen)?bit 0 when set, this bit enables the oflag output signal to be put on the external pin. additionally, setting this bit connects a timer?s output pin to its input. the polarity of the signal will be determined by the ops bit. 13.9.3 timer channel compare register 1 (cmp1) these read/write registers store the value used for comparison with counter value. there are four timer channel compare registers in this occurrence. their addresses are: tmra0_cmp1 (timer a, channel 0 co mpare 1)?address:tmra_base + $0 tmra1_cmp1 (timer a, channel 1 co mpare 1)?address: tmra_base + $8 tmra2_cmp1 (timer a, channel 2 co mpare 1)?address:tmra_base + $10 tmra3_cmp1 (timer a, channel 3 co mpare 1)?address: tmra_base + $18 figure 13-6. tmr compare register 1 (cmp1) see programmer?s sheet on appendix page b - 84 13.9.4 timer channel compare register 2 (cmp2) these read/write registers store the value used for comparison with counter value. there are four timer compare registers in this occurrence. their addresses are: tmra0_cmp2 (timer a, channel 0 co mpare 2)?address: tmra_base + $1 tmra1_cmp2 (timer a, channel 1 co mpare 2)?address: tmra_base + $9 tmra2_cmp2 (timer a, channel 2 com pare 2)?address: tmra_base + $11 tmra3_cmp2 (timer a, channel 3 co mpare 2)?address: tmra_base + $19 figure 13-7. tmr compare register 2 (cmp2) see programmer?s sheet on appendix page b - 85 base + $0. $8, $10, $18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read comparison value 1 write reset 0000000000000000 base + $1, $9, $11, $19 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read comparison value 2 write reset 0000000000000000 register descriptions (tmr_base = $1ffe80) quad timer (tmr), rev. 4 freescale semiconductor 13-17 13.9.5 timer channel capture register (cap) these read/write registers store the values captured from the counters. there are four timer channel hold registers in this occurrence. their addresses are: tmra0_cap (timer a, channel 0 capture)?address: tmra_base + $2 tmra1_cap (timer a, channel 1 capture)?address: tmra_base + $a tmra2_cap (timer a, channel 2 capture)?address: tmra_base + $12 tmra3_cap (timer a, channel 3 capture)?address: tmra_base + $1a figure 13-8. tmr capture register (cap) see programmer?s sheet on appendix page b - 86 13.9.6 timer channel load register (load) these read/write registers store the value used to load the counter. there are four timer channel load registers in this occurrence. their addresses are: tmra0_load (timer a, channel 0 load)?address: tmra_base + $3 tmra1_load (timer a, channel 1 load)?address: tmra_base + $b tmra2_load (timer a, channel 2 load)?address: tmra_base + $13 tmra3_load (timer a, channel 3 load)?address: tmra_base + $1b figure 13-9. tmr load register (load) see programmer?s sheet on appendix page b - 87 13.9.7 timer channel hold register (hold) these read/write registers store the channel?s value whenever any counter is read. there are four timer channel hold registers in this occurrence. their addresses are: tmra0_hold (timer a, channel 0 load)?address: tmra_base + $4 tmra1_hold (timer a, channel 1 load)?address: tmra_base + $c tmra2_hold (timer a, channel 2 load)?address: tmra_base + $14 tmra3_hold (timer a, channel 3 load)?address: tmra_base + $1c base + $2, $a, $12, $1a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read capture value write reset 0000000000000000 base + $3, $b, $13, $1b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read load value write reset 0000000000000000 resets 5685x digital signal controller user manual, rev. 4 13-18 freescale semiconductor figure 13-10. tmr hold register (hold) see programmer?s sheet on appendix page b - 88 13.9.8 timer channel counter register (cntr) there are four read/write timer channel counter registers in this occurrence. their addresses are: tmra0_cntr (timer a, channel 0 counter)?address: tmra_base + $5 tmra1_cntr (timer a, channel 1 counter)?address: tmra_base + $d tmra2_cntr (timer a, channel 2 counter)?address: tmra_base + $15 tmra3_cntr (timer a, channel 3 counter)?address: tmra_base + $1d figure 13-11. tmr counter register (cntr) see programmer?s sheet on appendix page b - 89 13.10 resets the tmr module can only be reset by the rst signal. this forces all registers to their reset state and clears the oflag signal if it is asserted. the counter will be turned off until the settings in the control register are changed. 13.11 interrupts the tmr module can generate 12 interrupts, three for each of the four counters/channels. 13.11.1 timer compare interrupts these interrupts are generated when a successful compare occurs between a counter and it?s compare registers while the timer compare flag interrupt enable (tcfie) is set in the tmr_scr. these interrupts are cleared by writing 0 to the tcf bit in the appropriate tmr_scr. base + $4, $c, $14, $1c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read hold value write reset 0000000000000000 base + $5. $d, $15, $1d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read counter write reset 0000000000000000 interrupts quad timer (tmr), rev. 4 freescale semiconductor 13-19 13.11.2 timer overflow interrupts these interrupts are generated when a counter rolls over its maximum value while the tcfie bit is set in the tmr_scr. these interrupts are cleared by writing 0 to the timer overflow flag (tof) bit of the appropriate tmr_scr. 13.11.3 timer input edge interrupts these interrupts are generated by a transition of the input signal (either positive or negative depending on ips setting) while the input edge flag interrupt enable (iefie) bit is set in the tmr_scr. these interrupts are cleared by writing 0 to the ief bit of the appropriate tmr_scr. interrupts 5685x digital signal controller user manual, rev. 4 13-20 freescale semiconductor time-of-day (tod), rev. 4 freescale semiconductor 14-1 chapter 14 time-of-day (tod) 5685x digital signal controller user manual, rev. 4 14-2 freescale semiconductor introduction time-of-day (tod), rev. 4 freescale semiconductor 14-3 14.1 introduction the 5685x devices in this manual have a time-of-day (tod) feature implemented as a sequence of counters to track elapsed time. the hardware is capable of tracking time up to 179.5 years, or 65,535 days. tod is comprised of a series of counters tracking elapsed seconds, minutes, hours, and days. the module requires an input clock ranging from 1-65536hz integer values only. the clock is further scaled down to generate a 1hz clock driving all of the time counters. all of the time counters are loaded with the time-of-day upon enabling tod. time counters subsequently track the elapsed time. if required, the tod feature can issue an alarm whenever selected current time registers match the time programmed into the enabled tod alarm registers. the tod can also provide an interrupt every second. an appropriate external clock frequency must be provided and the cgm module must be configured so tod clock input in integer hz from 1-65536hz is provided. once completed, the internal clock prescaler within the tod module can be configured to provide a 1hz time-base clock to the module. the cgm provides a bit to select one of two external clock prescalers. the oscillator tod clock prescaler is a fixed ? 128 divider. the cgm tod clock prescaler is a programmable divider followed by a fixed ? 2 divider. the programmable portion ranges from divide by 1 up to 2 to the 12th power. the oscillator prescaler is provided for use with a low frequency (2 - 4mhz) external clock and it is provided for use in conjunction with the pll. the cgm clock prescaler consumes more power and it is larger for use with direct external clock frequencies from 4mhz up to 240mhz. it is preferable to use the highest frequency tod clock input possible therefore to do as much clock division as possible using the internal prescaler within the tod module. tod clock frequencies below 10hz are not recommended. features 5685x digital signal controller user manual, rev. 4 14-4 freescale semiconductor 14.2 features ? separate counters for seconds, minutes, hours, and days with a 16-bit day capacity ? separate read/write registers for seconds, minutes, hours, and days ? alarm clock registers for seconds, minutes, hours, and days ? alarm interrupt with independent enables for compare of seconds, minutes, hours and days ? 1hz interrupt with enable ? tod reset only at power-on, unaffected by reset pin, software reset, or cop reset ? flexible clock prescaling for use with either external clocking or crystal oscillator ? works with crystal frequency of 2 - 4mhz ? capability to generate interrupt, pulling the part out of sleep ? can be configured to generate an alarm at a designated time 14.3 block diagram figure 14-1. time-of-day counter operation block diagram scaler load clock scaler tod enable 1hz seconds cntr minutes cntr hours cntr days cntr seconds reg minutes reg hours reg days reg ipbus interface toden = 0 allows write 1-65536hz input clock (integer hz) todsec todmin todhr todday seconds alarm seconds alarm seconds alarm seconds alarm tod one-second interrupt tod alarm interrupt tod alarm controls module memory map time-of-day (tod), rev. 4 freescale semiconductor 14-5 14.4 module memory map the base address of the tod module is $1fffc0. table 14-1. tod module memory map (tod_base = $1fffc0) address offset register acronym register name access type chapter location base + $0 todcs control status register read/write section 14.6.2 base + $1 todcsl clock scaler register read-only section 14.6.3 base + $2 todsec seconds register read-only section 14.6.4 base + $3 todsal seonds alarm register read-only section 14.6.5 base + $4 todmin minutes register read-only section 14.6.6 base + $5 todmal minutes alarm register read-only section 14.6.7 base + $6 todhr hours register read-only section 14.6.8 base + $7 todhal hours alarm register read-only section 14.6.9 base + $8 todday days register read-only section 14.6.10 base + $9 toddal hours alarm register read-only section 14.6.11 add. offset register name 151413121110987654321 0 $0 todcs r todsio todal test todda todha todma todsa todsen todaen tod_ lock toden w $1 todcsl r time-of-day clock scaler w $2 todsec r todsec w $3 todsal r todsal w $4 todmin r todmin w $5 todmal r todmal w $6 todhr r todhr w $7 todhal r todhal w $8 todday r todday w $9 toddal r toddal w r 0 read as 0 w reserved figure 14-2. tod register map summary functional description 5685x digital signal controller user manual, rev. 4 14-6 freescale semiconductor 14.5 functional description a sub block of tod implements the scaler, seconds, minutes, hours and days counters. the counters can be initialized with the current time when the tod module is disabled (when toden = 0). 14.5.1 scaler depending upon the frequency of the clock fed to the tod module, the appropriate value should be written to the clock scaler load register to derive a 1hz clock. the scaler counter is a 16-bit up counter, counting from zero while less than the value specified in the clock scaler register. in normal operation, the scaler counter increments with tod_clk input (frequency range from 1-65536 hz) if toden = 1. the base (1hz) clock is generated when the scaler counter wraps and is used to clock the time-of-day counters and 1hz interrupt. 14.5.2 time units time units (seconds, minutes, hours, days) are each implemented as counter/register pairs. 14.5.2.1 time counters the time counters are a set of modulo counters that are clocked by the 1 hz clock to maintain the current time in seconds, minutes, hours and days. they count only when tod en = 1. these counters maintain the time to the accuracy of the 1 hz clock. they initialize to the current value in the time registers at the first 1hz clock (one second) after toden is set to 1 and advance each second thereafter. 14.5.2.2 time registers time registers are provided to set and observe the corresponding counters. when toden is set to 1, the registers capture the counter values two ip_clk cycles after the 1hz clock and are readable but not writeable. when toden is set to 0, they will contain the current value of the time counters and they may be read or written. 14.5.2.3 time-of-day lock bit when set, the tod lock bit disables the continuous transfer of time-of-day counter values to the registers when toden is 1. this permits a read of each of the four time registers without the possibility of an in-process advancement of time values. the tod_lock bit should remain set at 0 except while reading the time registers when toden = 1. functional description time-of-day (tod), rev. 4 freescale semiconductor 14-7 14.5.3 stop mode during stop mode the tod module will continue to operate normally. the tod interrupts will still activate and can wake the processor up for tod related processing. 14.5.4 general information the tod alarms sub block is used to generate tod irq signals. the tod alarm registers todsal, todmal, todhal, and toddal, along with tod control/status register (todcs), are implemented in this sub block. tod generates two interrupt signals: 1. tod alarm interrupt 2. tod second interrupt both interrupt signals can wake up the device from its stop mode. 14.5.5 alarm interrupt flag and outputs the alarm interrupt feature provides a flexible means of detecting events based on time-of-day. the tod module contains alarm registers for seconds, minutes, hours, and days. the control and status register contains individual enables for each of these registers (todsa, todma, todha, todda) as well as an overall alarm interrupt enable (todaen). an alarm interrupt triggers during the time-of-day counting process. this interrupt occurs when at least one of the alarm enables is set and the todaen is set. all alarm registers can be enabled to generate an alarm at a designated time. all enabled alarm registers must match the corresponding time registers before the tod alarm interrupt irq is generated. for example, if the minutes and hour alarms are enabled, then both the minutes and hours registers must match the respective alarm registers before the irq will occur. the alarm interrupt triggers one tod input clock period after the tod_clk edge, advancing the time-of-day counters to their activation value. to minimize latency, it is preferable to generate a faster tod input clock and use a correspondingly higher value in the tod module?s clock scaler register. the alarm interrupt will not trigger until toden is set to one and all enabled alarm registers match the time-of-day counters. the interrupt will function in the stop mode; however, the tod module must be configured and enabled prior to entering the stop mode. every time the alarm interrupt triggers the tod alarm interrupt occurred flag (todal) in the control status register is set. the todal is cleared by writing 0 to it while it contains 1. the interrupt will not be taken unless it is also enabled in the interrupt controller module. register description (tod_base = $1fffc0) 5685x digital signal controller user manual, rev. 4 14-8 freescale semiconductor 14.5.6 1-second interrupt flag and outputs the one-second interrupt feature provides a means of detecting the passage of one-second time intervals. the one-second interrupt is triggered and the tod seconds interrupt (todsid) occurred flag in the status control register is set on the rising edge of the 1hz clock. the 1hz clock is derived out of the scaler counter. this clock only operates while the tod enable (toden) is set. the todsid bit is cleared by writing 0 to it while it contains a one. this interrupt will function in the stop mode; however, the tod module must be configured and enabled prior to entering the stop mode. the one-second interrupt output is used to signal a one-second interrupt to the interrupt controller. the interrupt will not be taken unless it is also enabled in the interrupt controller module. 14.6 register description (tod_base = $1fffc0) the address of a register is the sum of a base address and an address offset. the base address is defined at the mcu level and the address offset is defined at the module level. the base address given for each register will be tod_base. 14.6.1 tod register map table 14-2. tod register map register address register name register function decimal range when write enabled por value $1fffc0 todcs tod control/status n/c always 0 $1fffc1 todcsl clock scaler load 0-65535 toden = 0 0 $1fffc2 todsec seconds 0-59 toden = 0 0 $1fffc3 todsal seconds alarm 0-59 always 0 $1fffc4 todmin minutes 0-59 toden = 0 0 $1fffc5 todmal minutes alarm 0-59 always 0 $1fffc6 todhr hours 0-23 toden = 0 0 $1fffc7 todhal hours alarm 0-23 always 0 $1fffc8 todday days 0-65535 toden = 0 0 $1fffc9 toddal days alarm 0-65535 always 0 register description (tod_base = $1fffc0) time-of-day (tod), rev. 4 freescale semiconductor 14-9 14.6.2 time-of-day control status (todcs) the tod control status register controls tod operation . figure 14-3. tod control status (todcs) see programmer?s sheet on appendix page b - 95 14.6.2.1 time-of-day 1-second interrupt occurred flag (todsio)?bit 15 this bit is set when one-second interrupt occurs. this bit is cleared by writing 0 to the bit position. it must be cleared before exiting the interrupt service routine (isr). 14.6.2.2 time-of-day alarm interrupt occurred flag (todal)?bit 14 this bit is set when tod alarm interrupt occurs. this bit is cleared by writing 0 to the bit position. this bit must be cleared before exiting the interrupt service routine. 14.6.2.3 reserved?bits 13?10 these bits are reserved or not implemented. they cannot be read nor modified by writing. 14.6.2.4 test (test)?bits 8?9 this bit field is reserved as factory test bits and must be written as 0. 14.6.2.5 time-of-day days alarm enable (todda)?bit 7 ? 0 = alarm interrupt ignores days counter ? 1 = alarm interrupt requires match of days alarm register to days counter 14.6.2.6 time-of-day hours alarm enable (todha)?bit 6 ? 0 = alarm interrupt ignores hours counter ? 1 = alarm interrupt requires match of hours alarm register to hours counter base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todsio todal test todda todha todma todsa todsen todaen tod_lock toden write reset 0 0 000000 0 0 0 0 0 0 0 0 register description (tod_base = $1fffc0) 5685x digital signal controller user manual, rev. 4 14-10 freescale semiconductor 14.6.2.7 time-of-day minutes alarm enable (todma)?bit 5 ? 0 = alarm interrupt ignores minutes counter ? 1 = alarm interrupt requires match of minutes alarm register to minutes counter 14.6.2.8 time-of-day seconds alarm enable (todsa)?bit 4 ? 0 = alarm interrupt ignores seconds counter ? 1 = alarm interrupt requires match of seconds alarm register to seconds counter 14.6.2.9 time-of-day seconds interrupt enable (todsen)?bit 3 ? 0 = disables tod seconds interrupt ? 1 = enables tod seconds interrupt 14.6.2.10 time-of-day alarm interrupt enable (todaen)?bit 2 ? 0 = disables tod alarm interrupt ? 1 = enables tod alarm interrupt 14.6.2.11 time-of-day lock (tod_lock)?bit 1 when set, this bit prevents the time registers from automatically updating to the current value of the time counters while the tod module is enabled. it is used to avoid register updates while in the process of reading out the four time registers. it should be set only when in process of reading the current time while the tod module is enabled. ? 0 = tod registers not locked ? 1 = tod registers locked 14.6.2.12 time-of-day enable (toden)?bit 0 writing zero to toden disables the time-of-day counting; the time registers will contain the final value of the time counters and the registers become writable. when this field is written with 1, the seconds, minutes, hours, and days counters are loaded from the corresponding register and proceed to count in a normal time-of-day basis with seconds overflow incrementing minutes, minutes overflow incrementing hours, and so on through days overflow wrapping back to zero. while time-of-day counting is enabled, the seconds, minutes, hours, and day registers update with a two ipbus clock delay to the value of the corresponding counter, so reading the registers returns the current time-of-day. in this mode, writing seconds register, minutes register, hour register and days register, or clock scaler is disabled. register description (tod_base = $1fffc0) time-of-day (tod), rev. 4 freescale semiconductor 14-11 14.6.3 time-of-day clock scaler (todcsl) figure 14-4. tod clock scaler (todcsl) see programmer?s sheet on appendix page b - 96 14.6.3.1 time-of-day clock scaler (todcsl)?bits 15-0 setting this field to x divides the tod input clock frequency by x + 1 to produce the time-base clock used for incrementing the counters. the clock generation system and this scaler must be configured so the time-base clock is precisely 1hz for correct operation of the tod module as the seconds counter increments with each time-base clock. this register is always readable. it accepts writing only when toden = 0. 14.6.4 time-of-day seconds counter (todsec) figure 14-5. tod seconds register (todsec) see programmer?s sheet on appendix page b - 97 14.6.4.1 reserved?bits 15?6 these bits are reserved or not implemented. they cannot be read nor modified by writing. 14.6.4.2 time-of-day seconds (todsec)?bits 5?0 when toden is set, this register is continuously updated to contain the current seconds counter value. the value of the counter can be read through the seconds register, but it cannot be modified. when toden is cleared, tod counting is disabled. this register can then be read or written. when toden is set to one again, the counting resumes from the current register value. base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read time-of-day clock scaler write reset 0 0 00000000000000 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todsec write reset 0 0 00000000000000 register description (tod_base = $1fffc0) 5685x digital signal controller user manual, rev. 4 14-12 freescale semiconductor 14.6.5 time-of-day seconds alarm register (todsal) figure 14-6. tod seconds alarm register (todsal) see programmer?s sheet on appendix page b - 98 14.6.5.1 reserved?bits 15?6 these bits are reserved or not implemented. they cannot be read nor modified by writing. 14.6.5.2 time-of-day seconds alarm (todsal)?bits 5?0 when the value contained in this register matches the value of the seconds counter, the seconds alarm is asserted if the seconds alarm enable (todsa) bit and alarm interrupt enable (todaen) bits are set and all other enabled alarm registers also match. 14.6.6 time-of-day minutes register (todmin) 14.6.6.1 reserved?bits 15?6 these bits are reserved or not implemented. they cannot be read nor modified by writing. 14.6.6.2 time-of-day minutes (todmin)?bits 5?0 when toden is set, this register is continuously updated to contain the current minutes counter value. the value of the counter can be read through the minutes register, but it cannot be modified. when toden is cleared, tod counting is disabled. this register can then be read or written. when toden is set to one again, the counting resumes from the current register value. base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todsal write reset 0 0 00000000000000 base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todmin write reset 0 0 00000000000000 figure 14-7. tod minutes register (todmin) see programmer?s sheet on appendix page b - 99 register description (tod_base = $1fffc0) time-of-day (tod), rev. 4 freescale semiconductor 14-13 14.6.7 time-of-day minutes alarm register (todmal) 14.6.7.1 reserved?bits 15?6 these bits are reserved or not implemented. they cannot be read nor modified by writing. 14.6.7.2 time-of-day minutes alarm (todmal)?bits 5?0 when the value contained in this register matches the value of the minutes counter, the minutes alarm is asserted if the minutes alarm enable (todma) bit and alarm interrupt enable (todaen) bit are both set, and all other enabled alarm registers also match the current time. 14.6.8 time-of-day hours register (todhr) 14.6.8.1 reserved?bits 15?6 these bits are reserved or not implemented. they cannot be read nor modified by writing. 14.6.8.2 time-of-day hours (todhr)?bits 5?0 when toden is set, this register is continuously updated to contain the current hours counter value. the value of the counter can be read through the hours register, but it can not be modified. when toden is cleared, tod counting is disabled. this register can then be read or written. when toden is set to one again, the counting resumes from the current register value. 14.6.9 time-of-day hours alarm register (todhal) figure 14-10. tod hours alarm register (todhal) see programmer?s sheet on appendix page b - 102 base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todmal write reset 0 0 00000000000000 figure 14-8. tod minutes alarm register (todmal) see programmer?s sheet on appendix page b - 100 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todhr write reset 0 0 00000000000000 figure 14-9. tod hours register (todhr) see programmer?s sheet on appendix page b - 101 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todhal write reset 0 0 00000000000000 register description (tod_base = $1fffc0) 5685x digital signal controller user manual, rev. 4 14-14 freescale semiconductor 14.6.9.1 reserved?bits 15?5 these bits are reserved or not implemented. they cannot be read nor modified by writing. 14.6.9.2 time-of-day hours alarm (todhal)?bits 4?0 when the value contained in this register matches the value of the hours counter, the hours alarm is asserted if the hours alarm enable (todha) bit and the alarm interrupt enable (todaen) bit are both set and all other enabled alarm registers also match the current time. 14.6.10 time-of-day days register (todday) figure 14-11. tod days register (todday) see programmer?s sheet on appendix page b - 103 14.6.10.1 time-of-day days (todday)?bits 15?0 when toden is set, this counter is continuously updated to contain the current days counter value. the value of the counter can be read through the days register, but it cannot be modified. when toden is cleared, tod counting is disabled. this counter can then be read or written. when toden is set to one again, counting will resume counting from the current register value. 14.6.11 time-of-day days alarm register (toddal) figure 14-12. tod days alarm register (toddal) see programmer?s sheet on appendix page b - 104 14.6.11.1 time-of-day days alarm (toddal)?bits 15?0 when the value contained in this register matches the value of the days counter, the days alarm interrupt is asserted if the days alarm enable (todda) bit and alarm interrupt enable (todaen) bit are both set and all other enabled alarm registers also match the current time. base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todday write reset 0 0 00000000000000 base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read toddal write reset 0 0 00000000000000 general purpose input/output (gpio), rev. 4 freescale semiconductor 15-1 chapter 15 general purpose input/output (gpio) 5685x digital signal controller user manual, rev. 4 15-2 freescale semiconductor block diagram general purpose input/output (gpio), rev. 4 freescale semiconductor 15-3 15.1 introduction the 5685x general purpose input/output (gpio) is designed to share package pins with other peripheral modules on the chip. if a peripheral normally controls a given pin is not required, that pin then can be programmed to be a gpio with programmable pull-up. 15.2 features the gpio module design includes these distinctive features: ? individual control for each pin to be in either normal or gpio mode ? individual direction control for each pin in gpio mode ? individual pull-up enable control for each pin in either normal or gpio mode except for moda, b, and c pins because pull-ups are always disabled 15.3 block diagram figure 15-1. bit-slice view of gpio logic d_in on-chip peripheral d_out 0 1 peripheral data out pe 0 1 peripheral data in pe 0 1 dd pu peripheral out enable i/o cell data register pe dd gpio pin functional description 5685x digital signal controller user manual, rev. 4 15-4 freescale semiconductor 15.4 functional description each gpio pin can be configured as either an input (with or without pull-up) or an output. pull-ups are configured by writing to the pull-up enable (pue) registers and are automatically disabled when the pin is being used as an output in either the normal mode or the gpio mode. 15.5 modes of operation the gpio module design contains two major modes of operation. 15.5.1 normal mode this can also be thought of as peripheral controlled mode. the peripheral module controls the output enable and any output data to the i/o pad and any input data from the pad is passed to the peripheral. pull-up enables are controlled by a gpio register. 15.5.2 gpio mode in this mode, the gpio module controls the output enable to the pad and supplies any data to be output. also, any input data can be read from a gpio memory mapped register. pull-up enables are controlled by a gpio register. in the gpio mode, the data direction register (ddr) supplies the output enable to the i/o pad to control its direction. the dr supplies the output data if ddr is asserted. the value of the data on the i/o pad can be read by reading data register (dr) when ddr is 0. when in gpio mode the output data from the gpio to the peripheral module will be driven high and the output data and enable from the peripheral are ignored. the pull-up resistor can be enabled by writing to the pue register. the pull-up resistor will be disabled as long as the ddr is set to the output mode. module memory maps general purpose input/output (gpio), rev. 4 freescale semiconductor 15-5 15.6 gpio configurations each gpio port is controlled by the registers listed in table 15-1 . each register bit corresponds to a gpio pin. section 15-1 illustrates the logic associated with one gpio bit. 15.7 module memory maps there are eight gpio mapped modules listed in the following in tables, table 15-2 through table 15-9 and their individual accompanying register maps. the gpio peripherals are summarized in figure 15-2 through figure 15-9 . table 15-1. gpio registers functions register description function per peripheral enable register determines if pin functions as gpio or associated peripheral pin ddr data direction register determines pin direction (input or output) when pin functions as gpio dr data register data interface between the gpio pin and the ipbus puer pull-up enable register enables internal pull-up, qualified by other factors table 15-2. gpio a memory map (gpioa_base = $1ffe60) address offset register acronym register name access type chapter location base + $0 gpio_a_per peripheral enable register read/write section 15.8.1 base + $1 gpio_a_ddr data direction register read/write section 15.8.9 base + $2 gpio_a_dr data register read/write section 15.8.17 base + $3 gpio_a_pur pull-up enable register read/write section 15.8.25 add. offset register name 151413121110987654321 0 $0 per r 1 1 1 1 1 1 1 1 1 1 1 1 pe w $1 ddr r 0 0 0 0 0 0 0 0 0 0 0 0 dd w $2 dr r 0 0 0 0 0 0 0 0 0 0 0 0 data w $3 pur r 1 1 1 1 1 1 1 1 1 1 1 1 pue w r 0 read as 0 w reserved figure 15-2. gpio a register map summary module memory maps 5685x digital signal controller user manual, rev. 4 15-6 freescale semiconductor table 15-3. gpio b memory map (gpiob_base = $1ffe64) address offset register acronym register name access type chapter location base + $0 gpio_b_per peripheral enable register read/write section 15.8.2 base + $1 gpio_b_ddr data direction register read/write section 15.8.10 base + $2 gpio_b_dr data register read/write section 15.8.18 base + $3 gpio_b_pur pull-up enable register read/write section 15.8.26 add. offset register name 151413121110987654321 0 $0 per r pe w $1 ddr r dd w $2 dr r data w $3 pur r pue w r 0 read as 0 w reserved figure 15-3. gpio b register map summary table 15-4. gpio c memory map (gpioc_base = $1ffe68) address offset register acronym register name access type chapter location base + $0 gpio_c_per peripheral enable register read/write section 15.8.3 base + $1 gpio_c_ddr data direction register read/write section 15.8.11 base + $2 gpio_c_dr data register read/write section 15.8.19 base + $3 gpio_c_pur pull-up enable register read/write section 15.8.27 add. offset register name 151413121110987654321 0 $0 per r 1 1 1 1 1 1 1 1 1 1 pe w $1 ddr r 0 0 0 0 0 0 0 0 0 0 dd w $2 dr r 0 0 0 0 0 0 0 0 0 0 data w $3 pur r 1 1 1 1 1 1 1 1 1 1 pue w r 0 read as 0 w reserved figure 15-4. gpio c register map summary module memory maps general purpose input/output (gpio), rev. 4 freescale semiconductor 15-7 table 15-5. gpio d memory map (gpiod_base = $1ffe6c) address offset register acronym register name access type chapter location base + $0 gpio_d_per peripheral enable register read/write section 15.8.4 base + $1 gpio_d_ddr data direction register read/write section 15.8.12 base + $2 gpio_d_dr data register read/write section 15.8.20 base + $3 gpio_d_pur pull-up enable register read/write section 15.8.28 add. offset register name 151413121110987654321 0 $0 per r 1 1 1 1 1 1 1 1 1 1 pe w $1 ddr r 0 0 0 0 0 0 0 0 0 0 dd w $2 dr r 0 0 0 0 0 0 0 0 0 0 data w $3 pur r 1 1 1 1 1 1 1 1 1 1 pue w r 0 read as 0 w reserved figure 15-5. gpio d register map summary table 15-6. gpio e memory map (gpioe_base = $1ffe70) address offset register acronym register name access type chapter location base + $0 gpio_e_per peripheral enable register read/write section 15.8.5 base + $1 gpio_e_ddr data direction register read/write section 15.8.13 base + $2 gpio_e_dr data register read/write section 15.8.21 base + $3 gpio_e_pur pull-up enable register read/write section 15.8.29 add. offset register name 151413121110987654321 0 $0 per r 1 1 1 1 1 1 1 1 1 1 1 1 pe w $1 ddr r 0 0 0 0 0 0 0 0 0 0 0 0 dd w $2 dr r 0 0 0 0 0 0 0 0 0 0 0 0 data w $3 pur r 1 1 1 1 1 1 1 1 1 1 1 1 pue w r 0 read as 0 w reserved figure 15-6. gpio e register map summary module memory maps 5685x digital signal controller user manual, rev. 4 15-8 freescale semiconductor table 15-7. gpio f memory map (gpiof_base = $1ffe74) address offset register acronym register name access type chapter location base + $0 gpio_f_per peripheral enable register read/write section 15.8.7 base + $1 gpio_f_ddr data direction register read/write section 15.8.14 base + $2 gpio_f_dr data register read/write section 15.8.22 base + $3 gpio_f_pur pull-up enable register read/write section 15.8.30 add. offset register name 151413121110987654321 0 $0 per r 1 1 1 1 1 1 1 1 1 1 1 1 pe w $1 ddr r 0 0 0 0 0 0 0 0 0 0 0 0 dd w $2 dr r 0 0 0 0 0 0 0 0 0 0 0 0 data w $3 pur r 1 1 1 1 1 1 1 1 1 1 1 1 pue w r 0 read as 0 w reserved figure 15-7. gpio f register map summary table 15-8. gpio g memory map (gpiog_base = $1ffe78) address offset register acronym register name access type chapter location base + $0 gpio_g_per peripheral enable register read/write section 15.8.7 base + $1 gpio_g_ddr data direction register read/write section 15.8.15 base + $2 gpio_g_dr data register read/write section 15.8.23 base + $3 gpio_g_pur pull-up enable register read/write section 15.8.31 add. offset register name 151413121110987654321 0 $0 per r 1 1 1 1 1 1 1 1 1 1 1 1 pe w $1 ddr r 0 0 0 0 0 0 0 0 0 0 0 0 dd w $2 dr r 0 0 0 0 0 0 0 0 0 0 0 0 data w $3 pur r 1 1 1 1 1 1 1 1 1 1 1 1 pue w r 0 read as 0 w reserved figure 15-8. gpio g register map summary register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-9 15.8 register descriptions base addresses: ? gpioa_base = gpioa_base = $1ffe60 ? gpiob_base = gpiob_base = $1ffe64 ? gpioc_base = gpioc_base = $1ffe68 ? gpiod_base = gpiod_base = $1ffe6c ? gpioe_base = gpioe_base = $1ffe70 ? gpiof_base = gpiof_base = $1ffe74 ? gpiog_base = gpiog_base = $1ffe78 ? gpioh_base = gpioh_base = $1ffe7c table 15-9. gpio h memory map (gpioh_base = $1ffe7c) address offset register acronym register name access type chapter location base + $0 gpio_h_per peripheral enable register read/write section 15.8.8 base + $1 gpio_h_ddr data direction register read/write section 15.8.16 base + $2 gpio_h_dr data register read/write section 15.8.24 base + $3 gpio_h_pur pull-up enable register read/write section 15.8.32 add. offset register name 151413121110987654321 0 $0 per r 1 1 1 1 1 1 1 1 1 1 1 1 1 pe w $1 ddr r 0 0 0 0 0 0 0 0 0 0 0 0 0 dd w $2 dr r 0 0 0 0 0 0 0 0 0 0 0 0 0 data w $3 pur r 1 1 1 1 1 1 1 1 1 1 1 1 1 pue w r 0 read as 0 w reserved figure 15-9. gpio h register map summary register descriptions 5685x digital signal controller user manual, rev. 4 15-10 freescale semiconductor 15.8.1 port a peripheral enable register (gpioa_per) figure 15-10. port a peripheral enable register (gpioa_per) see programmer?s sheet on appendix page b - 105 15.8.1.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.1.2 peripheral enable (pe)?bits 3?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the emi module 15.8.2 port b peripheral enable register (gpiob_per) figure 15-11. port b peripheral enable register (gpiob_per) see programmer?s sheet on appendix page b - 106 15.8.2.1 peripheral enable (pe)?bits 15?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the host interface eight module base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pe write reset 1111111111111111 register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-11 15.8.3 port c peripheral enable register (gpioc_per) figure 15-12. port c peripheral enable register (gpioc_per) see programmer?s sheet on appendix page b - 107 15.8.3.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.3.2 peripheral enable (pe)?bits 5?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the essi0 module 15.8.4 port d peripheral enable register (gpiod_per) figure 15-13. port d peripheral enable register (gpiod_per) see programmer?s sheet on appendix page b - 108 15.8.4.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 1and cannot be modified by writing. 15.8.4.2 peripheral enable (pe)?bits 5?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the essi1 module base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 register descriptions 5685x digital signal controller user manual, rev. 4 15-12 freescale semiconductor 15.8.5 port e peripheral enable register (gpioe_per) figure 15-14. port e peripheral enable register (gpioe_per) see programmer?s sheet on appendix page b - 109 15.8.5.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.5.2 peripheral enable (pe)?bits 3?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the sci module 15.8.6 port f peripheral enables register (gpiof_per) figure 15-15. port f peripheral enables register (gpiof_per) see programmer?s sheet on appendix page b - 110 15.8.6.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.6.2 peripheral enable (pe)?bits 3?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the spi module base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-13 15.8.7 port g peripheral enables register (gpiog_per) figure 15-16. port g peripheral enables register (gpiog_per) see programmer?s sheet on appendix page b - 111 15.8.7.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.7.2 peripheral enable (pe)?bits 3?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the tmr module 15.8.8 port h peripheral enables register (gpioh_per) figure 15-17. port h peripheral enables register (gpioh_per) see programmer?s sheet on appendix page b - 112 15.8.8.1 reserved?bits 15?3 these bits are reserved or not implemented. they are read as 1and cannot be modified by writing. 15.8.8.2 peripheral enable (pe)?bits 2?0 these bits control whether a given pin is in either normal or gpio mode. ? 0 = gpio mode; pin operation is controlled by gpio registers ? 1 = normal mode; pin operation is controlled by the sim module base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 register descriptions 5685x digital signal controller user manual, rev. 4 15-14 freescale semiconductor 15.8.9 port a data direction register (gpioa_ddr) figure 15-18. port a data direction register (gpioa_ddr) see programmer?s sheet on appendix page b - 113 15.8.9.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.9.2 data direction (dd)?bits 3?0 these bits control the pins direction when in gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled 15.8.10 port b data dire ction register (gpiob_ddr) figure 15-19. port b di rection register (gpiob_ddr) see programmer?s sheet on appendix page b - 114 15.8.10.1 data direction (dd)?bits 15?0 these bits control the pins direction when in gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dd write reset 0000000000000000 register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-15 15.8.11 port c data di rection register (gpioc_ddr) figure 15-20. port c direction register (gpioc_ddr) see programmer?s sheet on appendix page b - 115 15.8.11.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.11.2 data direction (dd)?bits 5?0 these bits control the pins direction when in the gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled 15.8.12 port d data di rection register (gpiod_ddr) figure 15-21. port d direction register (gpiod_ddr) see programmer?s sheet on appendix page b - 116 15.8.12.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.12.2 data direction (dd)?bits 5?0 these bits control the pins direction when in the gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 register descriptions 5685x digital signal controller user manual, rev. 4 15-16 freescale semiconductor 15.8.13 port e data direction register (gpioe_ddr) figure 15-22. port e direction register (gipoe_ddr) see programmer?s sheet on appendix page b - 117 15.8.13.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.13.2 data direction (dd)?bits 3?0 these bits control the pins direction when in the gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled 15.8.14 port f data direction register (gpiof_ddr) figure 15-23. port f direction register (gpiof_ddr) see programmer?s sheet on appendix page b - 118 15.8.14.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.14.2 data direction (dd)?bits 3?0 these bits control the pins direction when in the gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-17 15.8.15 port g data di rection register (gpiog_ddr) figure 15-24. port g direction register (gpiog_ddr) see programmer?s sheet on appendix page b - 119 15.8.15.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.15.2 data direction (dd)?bits 3?0 these bits control the pins direction when in the gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled 15.8.16 port h data direction register (gpioh_ddr) figure 15-25. port h direction register (gpioh_ddr) see programmer?s sheet on appendix page b - 120 15.8.16.1 reserved?bits 15?3 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.16.2 data direction (dd)?bits 2?0 these bits control the pins direction when in the gpio mode. these bits have no effect on the output enables or pull-up enables in the normal mode. ? 0 = pin is an input; pull-ups are dependent on value of pue registers (default) ? 1 = pin is an output; pull-ups are disabled base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0 00 000 0000000000 register descriptions 5685x digital signal controller user manual, rev. 4 15-18 freescale semiconductor 15.8.17 port a data register (gpioa_dr) figure 15-26. port a data register (gpioa_dr) see programmer?s sheet on appendix page b - 121 15.8.17.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.17.2 data (data)?bits 3?0 these bits control the output data when in gpio mode. 15.8.18 port b data register (gpiob_dr) figure 15-27. port b data register (gpiob_dr) see programmer?s sheet on appendix page b - 122 15.8.18.1 data (data)?bits 15?0 these bits control the output data when in gpio mode. 15.8.19 port c data register (gpioc_dr) figure 15-28. port c data register (gpioc_dr) see programmer?s sheet on appendix page b - 123 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read data write reset 0000000000000000 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-19 15.8.19.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 0 and cannot be modified writing. 15.8.19.2 data (data)?bits 5?0 these bits control the output data when in gpio mode. 15.8.20 port d data register (gpiod_dr) figure 15-29. port d data register (gpiod_dr) see programmer?s sheet on appendix page b - 124 15.8.20.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.20.2 data (data)?bits 5?0 these bits control the output data when in gpio mode. 15.8.21 port e data register (gpioe_dr) figure 15-30. port e data register (gpioe_dr) see programmer?s sheet on appendix page b - 125 15.8.21.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.21.2 data (data)?bits 3?0 these bits control the output data when in gpio mode. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 register descriptions 5685x digital signal controller user manual, rev. 4 15-20 freescale semiconductor 15.8.22 port f data register (gpiof_dr) figure 15-31. port f data register (gpiof_dr) see programmer?s sheet on appendix page b - 126 15.8.22.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.22.2 data (data)?bits 3?0 these bits control the output data when in gpio mode. 15.8.23 port g data register (gpiog_dr) figure 15-32. port g data register (gpiog_dr) see programmer?s sheet on appendix page b - 127 15.8.23.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.23.2 data (data)?bits 3?0 these bits control the output data when in gpio mode. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-21 15.8.24 port h data register (gpioh_dr) figure 15-33. port h data register (gpioh_dr) see programmer?s sheet on appendix page b - 128 15.8.24.1 reserved?bits 15?3 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.24.2 data (data)?bits 2?0 these bits control the output data when in gpio mode. 15.8.25 port a pull-up enable register (gpioa_puer) figure 15-34. port a pull-up enable register (gpioa_puer) see programmer?s sheet on appendix page b - 129 15.8.25.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 0 and cannot be modified by writing. 15.8.25.2 pull-up enable (pue)?bits 3?0 these bits control whether pull-ups are enabled for inputs in either normal or gpio mode. pull ups are automatically disabled for outputs in both modes. ? 0 = pull ups disabled for inputs ? 1 = pull ups enabled for inputs (default) base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 register descriptions 5685x digital signal controller user manual, rev. 4 15-22 freescale semiconductor 15.8.26 port b pull-up enable register (gpiob_puer) figure 15-35. port b pull-up enable register (gpiob_puer) see programmer?s sheet on appendix page b - 130 15.8.26.1 pull-up enable (pue)?bits 15?0 these bits control whether pull-ups are enabled for inputs in either normal or gpio mode. pull ups are automatically disabled for outputs in both modes. ? 0 = pull ups disabled for inputs ? 1 = pull ups enabled for inputs (default) 15.8.27 port c pull-up enable register (gpioc_puer) figure 15-36. port c pull-up enable register (gpioc_puer) see programmer?s sheet on appendix page b - 131 15.8.27.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.27.2 pull-up enable (pue)?bits 5?0 these bits control whether pull-ups are enabled for inputs in either normal or gpio mode. pull ups are automatically disabled for outputs in both modes. ? 0 = pull ups disabled for inputs ? 1 = pull ups enabled for inputs (default) base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pue write reset 1111111111111111 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 register descriptions general purpose input/output (gpio), rev. 4 freescale semiconductor 15-23 15.8.28 port d pull-up enable register (gpiod_puer) figure 15-37. port d pull-up enable register (gpiod_puer) see programmer?s sheet on appendix page b - 132 15.8.28.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.28.2 pull-up enable (pue)?bits 5?0 these bits control whether pull-ups are enabled for inputs in either normal or gpio mode. pull ups are automatically disabled for outputs in both modes. ? 0 = pull ups disabled for inputs ? 1 = pull ups enabled for inputs (default) 15.8.29 port e pull-up enable register (gpioe_puer) figure 15-38. port e pull-up enable register (gpioe_puer) see programmer?s sheet on appendix page b - 133 15.8.29.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.29.2 pull-up enable (pue)?bits 3?0 these bits control whether pull-ups are enabled for inputs in either normal or gpio mode. pull ups are automatically disabled for outputs in both modes. ? 0 = pull ups disabled for inputs ? 1 = pull ups enabled for inputs (default) base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 register descriptions 5685x digital signal controller user manual, rev. 4 15-24 freescale semiconductor 15.8.30 port f pull-up enable register (gpiof_puer) figure 15-39. port f pull-up enable register (gpiof_puer) see programmer?s sheet on appendix page b - 134 15.8.30.1 reserved?bits 15?4 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.30.2 pull-up enable (pue)?bits 3?0 these bits control whether pull-ups are enabled for inputs in either normal or gpio mode. pull ups are automatically disabled for outputs in both modes. ? 0 = pull ups disabled for inputs ? 1 = pull ups enabled for inputs (default) 15.8.31 port g pull-up enable register (gpiog_puer) figure 15-40. port g pull-up enable register (gpiog_puer) see programmer?s sheet on appendix page b - 135 15.8.31.1 reserved?bits 15?4 these bits are reserved or not implemented.they are read as 1 and cannot be modified by writing. 15.8.31.2 pull-up enable (pue)?bits 3?0 these bits control whether pull-ups are enabled for inputs in either normal or gpio mode. pull ups are automatically disabled for outputs in both modes. ? 0 = pull ups disabled for inputs ? 1 = pull ups enabled for inputs (default) base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 data register access general purpose input/output (gpio), rev. 4 freescale semiconductor 15-25 15.8.32 port h pull-up enable register (gpioh_puer) figure 15-41. port h pull-up enable register (gpioh_puer) see programmer?s sheet on appendix page b - 136 15.8.32.1 reserved?bits 15?3 these bits are reserved or not implemented. they are read as 1 and cannot be modified by writing. 15.8.32.2 pull-up enable (pue)?bits 2?0 this register is not used because pull-ups are always disabled for the moda, b, and c pins. 15.9 data register access care must be taken when accessing the data registers. table 15-10 summarizes the results of various data register accesses in different conditions. table 15-10. data register access base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 output enable from peripheral per ddr pad state access type data access result x 0 0 input write to dr data is written into dr by ipbus. no effect on the pad value. x 0 1 output write to dr data is written into the dr by the ipbus. dr value seen at pad. x 0 0 input read from dr pad state is read by the ipbus. no effect on dr value. x 0 1 output read from dr dr value is read by the ipbus. dr value seen at pad. 1 1 x input write to dr data is written into the dr by the ipbus. no effect on pad value. 0 1 x output write to dr data is written into the dr by the ipbus. peripheral output data is seen at pad. 1 1 x input read from dr dr value is read by the ipbus. no effect on the pad or dr value 0 1 x output read from dr dr value is read by the ipbus. peripheral output data is seen at the pad. resets 5685x digital signal controller user manual, rev. 4 15-26 freescale semiconductor 15.10 resets the gpio module can only be reset by the rst signal. this forces all registers to their reset state and sets the chip pads to be peripheral controlled with pull-ups enabled. 15.11 interrupts the gpio module does not generate interrupts. host interface eight (hi8), rev. 4 freescale semiconductor 16-1 chapter 16 host interface eight (hi8) 5685x digital signal controller user manual, rev. 4 16-2 freescale semiconductor features host interface eight (hi8), rev. 4 freescale semiconductor 16-3 16.1 introduction the host interface eight (hi8) is a byte-wide, full-duplex, double-buffered, parallel port able to be connected directly to the data bus of a host processor. the hi8 supports a variety of buses, and provides connection with a number of industry standard dscs, microcomputers, and microprocessors. because the host bus can operate asynchronously to the core clock, the hi8 registers are divided into two banks: 1. the host side bank is accessible to the external host 2. the dsc side bank is accessible to the core the hi8 supports two classes of interfaces: 1. host processor/mcu connection interface 2. general purpose input/output (gpio) port hi8 port pins not configured for peripheral use can be configured as gpio pins. 16.2 features 16.2.1 dgital signal controller (dsc) side ? four internal data i/o-mapped locations ? sixteen-bit data word ? transfer modes ?dsc-to-host ? host-to-dsc ? host command ? handshaking protocols ? software polled ? interrupt driven ? dma accesses. ? instructions ? memory mapped registers allow the standard move instruction to be used. ? bit addressing instructions (i.e., bfchg, bfclr, bfset, bftsth, bftstl, brclr, brset) simplify i/o service routines. features 5685x digital signal controller user manual, rev. 4 16-4 freescale semiconductor 16.2.2 host side ? signals (16 pins) ? hd7?hd0 data bus ? ha2-ha0 host address bus ?hrw / hrd - host read write select (hrw) or host read (hrd ) strobe ? hds / hwr - host data strobe (hds ) or host write (hwr ) strobe ?hcs host chip select ?hreq / htrq - host request (hreq ) or host transmit request (htrq ) ? hack / hrrq - host acknowledge (hack ) or host receive request (hrrq ) ? mapping ? consecutive byte locations ? memory or i/o-mapped peripheral for microprocessors, microcontrollers, etc. ? eight-bit data word ? transfer modes ? mixed 8- and 16-bit data transfers ?dsc-to-host ?host-to-dsc ? host command ? handshaking protocols ? software polled ? interrupt driven ? dedicated interrupts ? separate interrupt lines for each interrupt source ? special host commands force core interrupts under host processor control, useful for: ? real-time production diagnostics ? debugging window for program development ? host control protocols hi8 host port host interface eight (hi8), rev. 4 freescale semiconductor 16-5 16.3 signal descriptions 16.4 hi8 host port this section?s table details the hi8 pins and their functions. additionally, the hi8 block diagram is located as figure 16-1 following the hi8 pins details in table 16-1 . table 16-1. host interface 8 signals hi8 port pin signal name signal type state during reset of stop signal description hd[0:7] hd0 - hd7 or (pb0 - pb7) input /output input or output disconnected internally host data bus? this bidirectional data bus is used to transfer data between the host processor and the dsc, (hd0-hd7). port b 0-7? these are gpio pins when not configured for host port use. ha[0:2] ha0 - ha2 or (pb8 - pb10) input input/output disconnected internally host address? these inputs provide the address selection for the hi8 registers, (ha0-ha2). port b 8-10? these are gpio pins when not configured for host port use. hrw / hrd hrw or hrd or (pb11) input input or output disconnected internally host read/write? when the hi8 is programmed to interface to a single data strobe host bus, this signal is the read/write input (hrw). when set low, the host writes data to dsc. when set high, the host reads data from dsc. host read data strobe? when the hi8 is programmed to interface to a double data strobe host bus, this signal is the read data strobe input (hrd ), active low. port b 11? this is a gpio pin when not configured for host port use. hds / hwr hds or hwr or (pb12) input input input/output disconnected internally host data strobe? when the hi8 is programmed to interface to a single-data strobe host bus, this input enables a data transfer on the hi8 when hcs is set to low. host write data strobe? when the hi8 is programmed to interface to a double data strobe host bus and the hi8 function is selected, this active low signal is the write data strobe input (hwr ). port b 12? this is a gpio pin when not configured for host port use. hi8 host port 5685x digital signal controller user manual, rev. 4 16-6 freescale semiconductor hcs hcs or (pb13) input input/output disconnected internally host chip select? this is the chip select input for the hi8. port b 13? this is a gpio pin when not configured for host port use. hreq / htrq hreq or htrq or (pb14) open drain output open drain output input /output disconnected internally host request? when the hi8 is programmed for hrms = 0 functionality (typically used on a single data strobe bus), this output is used by the hi8 to request service from the host processor. the hreq may be connected to an interrupt request pin of a host processor, a transfer request of a dma controller, or a control input of external circuitry. transmit host request? when the hi8 is programmed for hrms = 1 functionality (typically used on a double data strobe bus), this signal is the transmit host request output (htrq ). the htrq may be connected to an interrupt request pin of a host processor. port b 14? this is a gpio pin when not configured for host port use. hack / hrrq hack or hrrq or (pb15) input open drain output input /output disconnected internally host acknowledge? when the hi8 is programmed for hrms = 0 functionality (typically used on a single data strobe bus), this input has two functions: 1) provide a host acknowledge signal for dma transfers, or 2) to control handshaking and provide a host interrupt acknowledge compatible with the mc68000 family processors. receive host request? when the hi8 is programmed for hrma = 1 functionality (typically used on a double data strobe bus), this signal is the receive host request output (hrrq ). port b 15? this is a gpio pin when not configured for host port use. table 16-1. host interface 8 signals (continued) hi8 port pin signal name signal type state during reset of stop signal description hi8 block diagram host interface eight (hi8), rev. 4 freescale semiconductor 16-7 16.5 hi8 block diagram figure 16-1. hi8 block diagram hcr hsr htx hrx txl 8 txh 8 rxl rxh ivr cvr icr isr 16 16 host bus ha0-ha2 hd0 - hd7 hrw / hrd hds / hwr hcs hreq / htrq hack / hrrq host interface control logic interrupts hcr?host control register hsr?host status register htx?host transmit register hrx?host receive register isr?interface status register icr?interface control register cvr?command vector register ivr?interrupt vector register rxh?receive register high rxl?receive register low txh?transmit register high txl?transmit register low 8 8 8 8 8 8 dsc side register descriptions (hi8_base = $1fffd8) 5685x digital signal controller user manual, rev. 4 16-8 freescale semiconductor 16.6 dsc side register descriptions (hi8_base = $1fffd8) hi8 contains four dsc side interface registers outlined in table 16-2 . table 16-2. dsc side host registers (hi_base =$1fffd8) address offset register acronym register name access type chapter location base + $0 hcr control register read/write section 16.8.1 base + $1 hsr status register read/write section 16.8.2 base + $2 htx transmit data register write-only section 16.8.3 base + $2 hrx receive data register read-only section 16.8.4 add. offset register name 151413121110987654321 0 $0 hcr r 0 0 0 0 0 0 0 hrms hdds tdmaen rdmaen hf3 hf2 hcie htie hrie w 0 0 0 0 0 0 0 $1 hsr r 0 0 0 0 0 0 0 0 0 0 hdma hf1 hf0 hcp htde hrdf w 0 0 0 0 0 0 0 0 0 0 $2 htx r w high byte (from hrx) low byte (from lrx) $2 hrx r high byte (from htx) low byte (from ltx) w r 0 read as 0 w reserved figure 16-2. dsc host side register map summary host side register descriptions host interface eight (hi8), rev. 4 freescale semiconductor 16-9 16.7 host side register descriptions hi8 contains eight host side interface registers outlined in table 16-3 . table 16-3. hi8 host side register map (hi8 host side_base = $1fffd8) address offset register acronym register name access type chapter location hlend = 0 (big endian) hlend = 1 (little endian) base + $0 icr icr interface control read/write section 16.9.1 base + $1 cvr cvr command vector read/write section 16.9.2 base + $2 isr isr interface status read only section 16.10.1 base + $3 ivr ivr interrupt vector read/write section 16.10.2 base + $4 ? ? unused read as 00 ? base + $5 ? ? unused read as 00 ? base + $6 rxh/txh rxl/txl receive/transmit bytes read/write section 16.10.3 base + $7 rxl/txl rxh/txh transmit/receive bytes read/write section 16.10.4 add. offset register name 7654321 0 $0 icr r init hm1 hm0 hf1 hf0 hlend treq rreq w $1 cvr r hc hv6 hv5 hv4 hv3 hv2 hv1 hv0 w $2 isr r hreq dma 0 hf3 hf2 trdy txde rxdf w $3 ivr r iv7 iv6 iv5 iv4 iv3 iv2 iv1 iv0 w r 0 read as 0 w reserved figure 16-3. dsc host side register map summary dsc side registers 5685x digital signal controller user manual, rev. 4 16-10 freescale semiconductor 16.8 dsc side registers the dsc core views the hi8 as a memory mapped peripheral occupying four 16-bit words in data memory space. the dsc can use the hi8 as a normal memory mapped peripheral, using either standard polled or interrupt programming techniques. separate transmit and receive data registers are double-buffered to allow the dsc and host processor to efficiently transfer data at high speed. memory mapping allows dsc core communication with the hi8 registers to be accomplished using standard instructions and addressing modes. in addition, the move instruction allows hi8-to-memory and memory-to-hi8 data transfers without going through an intermediate register. both hardware and software reset disable the hi8. these registers can be accessed by the dsc core, or by the external host. 16.8.1 hi8 control register (hcr) the hi8 control register (hcr) is 16-bit read/write control register used by the dsc core to control the hi8 operating mode. reserved bits are read and written as 0, ensuring future compatibility. figure 16-4 illustrates the programming model of the hcr. the initialization values for the hcr bits are described in table 16-6 . the hcr bits are described in the following paragraphs. figure 16-4. host control register (hcr) see programmer?s sheet on appendix page b - 137 16.8.1.1 reserved bits?bits 15?9 these bits are reserved or not implemented. they are read as, and written with 0s. 16.8.1.2 host request mode select (hrms)?bit 8 the host mode select (hrms) bit controls the host request pins. table 16-4 shows the functionality of the i/o pins controlled by this bit. note: the direction of the hack / hrrq pin changes based on the hrms setting. hack is an input, while hrrq is an output. base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 hrms hdds tdmaen rdmaen hf3 hf2 hcie htie hrie write 0 0 0 0 0 0 0 reset 000 0000 0 0 0 0 0 0 0 0 0 dsc side registers host interface eight (hi8), rev. 4 freescale semiconductor 16-11 16.8.1.3 host dual data strobe (hdds)?bit 7 when the host dual data strobe (hdds) bit is set, the hi8 operates in the dual data strobe bus mode; a host bus with separated read and write data strobes. when the hdds bit is cleared, the hi8 operates in the single strobe bus mode, i.e. a host bus with a single data strobe signal. please see figure 16-5 for a description of the two types of buses. the hdds bit is cleared on hardware reset. figure 16-5. single and du al data strobe bus modes table 16-4. hrms configuration of hreq and hack pins pin hrms = 0 hrms = 1 hreq / htrq hreq htrq hack / hrrq hack hrrq single data strobe mode (hdds = 0) hrw hds in single strobe bus mode, a ds (data-strobe) signal qualifies the access, while a r/w (read-write) signal specifies the direction of it. host data dual data strobe mode (hdds = 1) hwr hrd write cycle read cycle in dual strobe bus mode, there are special rd and wr signals that both qualify the access as being a read or a write access, respectively. hcs hcs dsc side registers 5685x digital signal controller user manual, rev. 4 16-12 freescale semiconductor 16.8.1.4 dsc side transmit dma enable (tdmaen)?bit 6 the tdmaen bit is used to enable dsc side transmit dma operations. when this bit is set, the on-chip dma controller handles transferring data between the htx register and dsc memory. the on-chip dma controller must be appropriately configured to implement the desired data transfer. 16.8.1.5 dsc side receive dma enable (rdmaen)?bit 5 the rdmaen bit is used to enable dsc side receive dma operations. when this bit is set, the on-chip dma controller handles transferring data between the hrx register and dsc memory. the on-chip dma controller must be appropriately configured to implement the desired data transfer. 16.8.1.6 host flags 2 and 3 (hf2?hf3)?bits 4?3 the host flag 2 and host flag 3 (hf2 and hf3) bits are used as general purpose flags for dsc-to-host communication. hf2 and hf3 may be set or cleared by the core. hf2 and hf3 are reflected in the interrupt status register (isr) on the host side if they are modified by the dsc software, the host processor can read the modified values by reading the isr. these two flags are not designated for any specific purpose but are general purpose flags. they can be used individually or as encoded pairs in a simple dsc-to-host communication protocol, implemented in both the dsc and the host processor software. 16.8.1.7 host command interrupt enable (hcie)?bit 2 the host command interrupt enable (hcie) bit is used to enable a dsc core interrupt when the hcp status bit in the hsr is set. when the hcie bit is cleared, hcp interrupts are disabled. when the hcie bit is set, a host command interrupt request occurs if hcp is set. the interrupt address is determined by the host command vector register (cvr). the hcie is cleared on hardware reset. note: host interrupt request priorities: if more than one interrupt request source is asserted and enabled (i.e., hrdf = 1, hcp = 1, hrie = 1, and hcie = 1) the hi8 generates interrupt requests according to table 16-5 . table 16-5. hi8 interrupt request order priority interrupt source highest host command (hcp = 1) ? transmit data (htde = 1) lowest receive data (hrdf = 1) dsc side registers host interface eight (hi8), rev. 4 freescale semiconductor 16-13 16.8.1.8 host transmit interrupt enable (htie)?bit 1 the host transmit interrupt enable (htie) bit is used to enable a dsc core interrupt when the host transmit data empty (htde) status bit in the hsr is set. when the htie bit is cleared, htde interrupts are disabled. when the htie bit is set, a host transmit data interrupt request occurs when the htde bit is set. the htie bit is cleared on hardware reset. 16.8.1.9 host receive interrupt enable (hrie)?bit 0 the host receive interrupt enable (hrie) bit is used to enable a dsc core interrupt when the host receive data full (hrdf) status bit in the host status register (hsr) is set. when the hrie bit is cleared, hrdf interrupts are disabled. when the hrie bit is set, a host receive data interrupt request occurs if the hrdf bit is also set. the hrie bit is cleared on hardware reset. 16.8.2 hi8 status register (hsr) the 16-bit read-only hi8 status register (hsr) is used by the dsc to read the status and flags of the hi8 interface. it cannot be directly accessed by the host processor. reserved bits are read as 0s. the value of the hsr after reset is $0002. all bits are cleared, except for the host transmit data empty (htde) bit. it is set. the hsr bits are described in the following paragraphs. figure 16-6. host status register (hsr) see programmer?s sheet on appendix page b - 138 16.8.2.1 reserved?bits 15?6 these bits are reserved or not implemented. they are read as, and written with 0s. 16.8.2.2 host dma status (hdma)?bit 5 the host dma status (hdma) bit indicates the host processor has enabled the host dma mode of the hi8 by setting hm1 or hm0 to 1. when the hdma status bit is set at 0, it indicates the host dma mode is disabled by the host mode bits hm0 and hm1, both having been cleared, in the interface control register icr and no host dma operations are pending. when the hdma status bit is set, the host dma mode is enabled by the host mode bits hm0 and hm1. the transmit or receive channel not in use can be used by the host for polled or interrupt operation by the dsc. hdma is cleared by a dsc reset. base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 hdma hf1 hf0 hcp htde hrdf write 0 0 0 0 0 0 0 0 0 0 reset 000 0000000000010 dsc side registers 5685x digital signal controller user manual, rev. 4 16-14 freescale semiconductor note: this bit is always 0 if hrms = 1 since the hreq and hack function is disabled and host dma operations are disabled. 16.8.2.3 host flags 0 and 1 (hf0?hf1)?bits 4?3 the host flag 0-1 (hf0 and hf1) bits are used as a general purpose flags for host-to-dsc communication. the hf0 and hf1 bits can be set or cleared by the host. these bits reflect the status of host flags hf0 and hf1 in the interface control register (icr) on the host side. these two flags are not designated for any specific purpose, but are considered general purpose flags. they can be used individually or as encoded pairs in a simple host-to-dsc communication protocol, implemented in both the dsc and the host processor software. the hf0 and hf1 bits are cleared on hardware reset. 16.8.2.4 host command pending (hcp)?bit 2 the host command pending (hcp) flag bit reflects the status of the hc bit in the command vector register (cvr), indicating a host command interrupt is pending. the hcp bit is set when the hc bit is set, and both bits are cleared by the hi8 hardware when the interrupt request is serviced by the dsc core. the host can also clear the hc bit, thereby clearing the hcp bit as well. the hcp bit is cleared on hardware reset. 16.8.2.5 host transmit data empty (htde)?bit 1 the host transmit data empty (htde) flag bit indicates the host transmit data (htx) register is empty and can be written by the dsc core. the htde bit is set when the htx register is transferred to the rxh/rxl registers, and cleared when host transfer date (htx) is written by the dsc core. when the htde bit is set, the hi8 generates a transmit data full dma request. htde can also be set by the host processor using the initialize function. the htde bit is set on hardware reset. 16.8.2.6 host receive data full (hrdf)?bit 0 the host receive data full (hrdf) flag bit indicates the host receive data (hrx) register contains data from the host processor. the hrdf bit is set when data is transferred from the txh/txl registers to the host receive data (hrx) register. the hrdf bit is cleared when the hrx register is read by the dsc core. when the hrdf bit is set, the hi8 generates a receive data full dma request. the hrdf bit can also be cleared by the host processor using the initialize function. the hrdf bit is cleared on hardware reset. dsc side registers host interface eight (hi8), rev. 4 freescale semiconductor 16-15 16.8.3 hi8 transmit data register (htx) the hi8 transmit data (htx) register is used for dsc-to-host data transfers. the htx register is viewed as a 16-bit write-only register by the dsc core. writing to the htx register clears the htde bit in the hsr. the dsc can program the htie bit causing a host transmit data inter- rupt when the htde bit is set. the htx register is transferred as 16-bit data to the receive byte registers rxh/rxl when both the htde bit on the dsc side and the rxdf status bits on the host side are cleared. this transfer operation sets both rxdf and htde bits. data should not be written to the htx register until the htde bit is set to prevent the previous data from being overwritten. figure 16-7. hi8 transmit data register (htx) see programmer?s sheet on appendix page b - 139 16.8.4 hi8 receive data register (hrx) the hi8 receive data (hrx) register is used for host-to-dsc data transfers. the hrx register is viewed as a 16-bit read-only register by the dsc core. the hrx register is loaded with 16-bit data from the transmit data registers txh/txl on the host side when both the transmit data registers empty txde on the host side, and dsc host receive data full (hrdf) bits are cleared. this transfer operation sets txde and hrdf bits. the hrx register contains valid data when the hrdf bit is set. reading hrx clears hrdf. the dsc may program the hrie bit to cause a host receive data interrupt when hrdf is set. figure 16-8. hi8 receive data register (hrx) see programmer?s sheet on appendix page b - 139 16.8.5 dsc side registers after reset table 16-6 shows the results of the three reset types on the bits in each of the hi8 registers accessible by the dsc core. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write high byte (from hrx) low byte (from lrx) reset 000 0000000000000 base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read high byte (from htx) low byte (from ltx) write reset 000 0000000000000 dsc side registers 5685x digital signal controller user manual, rev. 4 16-16 freescale semiconductor 16.8.6 hi8 dsc core interrupts the hi8 may request interrupt service from either the dsc core or the host processor. the dsc core interrupts are internal and do not require the use of an external interrupt pin. please refer to figure 16-9 . when the appropriate interrupt enable bit in the host control register (hcr) is set, an interrupt condition caused by the host processor sets the appropriate bit in the host status register (hsr), thereby generating an interrupt request to the dsc core. the dsc core acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine. the three possible interrupts are: ? receive data register full ? transmit data register empty ? host command the host command can access any interrupt vector in the interrupt vector table, although it has a set of vectors reserved for host command use. the dsc interrupt service routine must read or write the appropriate hi8 register. for example, clear the hrdf or htde bit to clear the interrupt. in the case of host command interrupts, the interrupt acknowledge from the dsc core program controller unit (pcu) clears the pending interrupt condition. table 16-6. dsc side registers after reset register name register data reset type hardware rest 1 software reset 2 stop reset 3 hsr hdma 0 0 ? hf1-hf0 0 0 ? hcp 0 0 0 htde 1 1 1 hrdf 0 0 0 hrx hrx[15:0] empty empty empty htx htx[15:0] empty empty empty 1. caused by reset signal 2. caused by executing the reset instruction 3. caused by executing the stop instruction host side registers host interface eight (hi8), rev. 4 freescale semiconductor 16-17 figure 16-9. hsr?hcr operation 16.9 host side registers the hi8 appears to the host processor as 8-byte-wide registers. the host can access the hi8 asynchronously by using polling techniques or interrupt-based techniques. separate transmit and receive data registers are double buffered to allow the dsc core and host processor to transfer data efficiently at high speed. the hi8 appears to the host processor as a memory mapped peripheral occupying eight bytes in the host processor address space, detailed in figure 16-7 . these registers can be viewed as: ? interface control register (icr) ? interface status register (isr) ? two data registers ? receive data high/low (rxh/rxl) ? transmit data high/low (txh/txl) ? two vector registers ? interface vector receive (ivr) ? command vector register (cvr) the cvr is a special command register used by the host processor to issue commands to the dsc. each of these registers can be accessed only by the host processor. hcr status enable dsc core interrupts receive data full transmit data empty host command hrie htie hcie hf2 hf3 43210 4321 hsr 0 hf1 hf0 hcp htde hrdf host side registers 5685x digital signal controller user manual, rev. 4 16-18 freescale semiconductor standard host processor instructions such as byte move and addressing modes are used to communicate with the hi8 registers. the hi8 registers are addressed allowing 8-bit host processors to use 8/16-bit load and store instructions for data transfers. the hreq / htrq and hack / hrrq handshake flags are provided for polled or interrupt driven data transfers with the host processor. because the dsc interrupt response is sufficiently rapid, most host microprocessors can load or store data at their maximum programmed i/o instruction rate without testing the handshake flags for each transfer. if full handshake is not required, the host processor can treat the dsc as a fast device, allowing data to be transferred between the host processor and the dsc at the fastest host processor data rate. one of the most innovative features of the hi8 is the host command feature. with this feature, the host processor can issue vectored interrupt requests to the dsc core. the host can select any of 128 dsc interrupt routines to be executed by writing a vector address register in the hi8. this flexibility allows the host programmer to execute as many as 128 pre-programmed functions inside the dsc core. for example, host interrupts permits the host processor to read or write dsc registers (data or program memory locations), force interrupt handlers (i.e., essi, sci, irqa and irqb interrupt routines) to perform control and debugging operations when interrupt routines are implemented in the dsc to perform these tasks. note: please be aware when the dsc core enters the stop mode, the hi8 pins are electrically disconnected internally, thus disabling the hi8 until the core leaves stop mode. while the hi8 configuration remains unchanged in stop mode, the core cannot be restarted via the hi8 interface. do not issue a stop command to the dsc via the hi8 unless some other mechanism for exiting stop mode is provided. 16.9.1 interface control register (icr) the interface control register (icr) is an 8-bit read/write control register used by the host processor to control the hi8 interrupts and flags. the icr cannot be accessed by the dsc core, but it allows the use of bit manipulation instructions on the control register. the control bits are described in the following paragraphs. figure 16-10 illustrates the programming model of the icr. figure 16-10. interface control register (icr) see programmer?s sheet on appendix page b - 141 base + $0 7 6 5 4 3 2 1 0 read init hm1 hm0 hf1 hf0 hlend treq rreq write reset 00000 0 00 host side registers host interface eight (hi8), rev. 4 freescale semiconductor 16-19 16.9.1.1 initialize (init)?bit 7 the initialize (init) bit is used by the host processor to force initialization of the hi8 hardware. initialization consists of configuring the hi8 transmit and receive control bits. using the init bit to initialize the hi8 hardware may or may not be necessary, depending upon the software design of the interface. the type of initialization performed when the init bit is set depends on the state of treq and rreq bits located in the interface control register. the init command, local to the hi8, is designed to conveniently configure the hi8 into the desired data transfer mode. those commands are described in figure 16-7 . the host processor sets the init bit, causing the hi8 to execute the init command. the interface hardware clears the init bit when the command has been executed. 16.9.1.2 host mode control (hm1, hm0)?bits 6?5 the host mode control bits hm0 and hm1 select the transfer mode of the hi8. hm1 and hm0 enable the dma mode of operation, or they interrupt a no-host dma mode of operation when hreq bit in the host control register (hcr) is set. when the host dma mode is enabled, the hreq pin is used as a dma transfer request output to a host dma controller and the hack pin is used as a dma transfer acknowledge input from a table 16-7. init execution definition?interrupt mode treq rreq after init execution transfer direction initialized 0 0 init = 0 none 0 1 init = 0; rxdf = 0; htde = 1 dsc-to-host 1 0 init = 0; txde = 1; hrdf = 0 host-to-dsc 1 1 init = 0; rxdf = 0; htde = 1;txde = 1; hrdf = 0 host-to/from-dsc table 16-8. init execution definition?hdma mode (hm1 = 1) treq rreq after init execution transfer direction initialized 0 0 init = 0; address counter = hm1, hm0 none 01 init = 0; rxdf = 0; htde = 1; address counter = hm1, hm0 dsc-to-host 10 init = 0; txde = 1; hrdf = 0; address counter = hm1, hm0 host -to-dsc 1 1 undefined (illegal) host-to/from-dsc host side registers 5685x digital signal controller user manual, rev. 4 16-20 freescale semiconductor host dma controller. the dma control bits hm0 and hm1 select the size of the dma word to be transferred as shown in table 16-9 . the direction of the dma transfer is selected by the treq and rreq bits. when both hm1 and hm0 are cleared, the host dma mode is disabled and the treq and rreq control bits are used for the host processor interrupting via the external host request hreq output pin when the hrms bit is also cleared. in the interrupt mode, the host acknowledge hack input pin is used for the mc68000 family vectored interrupt acknowledge input. when hm1 is set, the host dma mode is enabled and the host request (hreq ) pin is not available for host processor interrupts. when the host dma mode is enabled, the treq and rreq bits select the direction of host dma transfers; the host acknowledge (hack ) input pin is used as a host dma transfer acknowledge input. when the host dma direction is from dsc-to-host, the contents of the selected register, rxh or rxl, are enabled onto the host data bus when the hack pin is asserted. if the host dma direction is from host-to-dsc, the contents of the selected register are enabled onto the host data bus when the hack pin is asserted. if the host dma direction is from host-to-dsc, the selected register is written to txh or txl from the host data bus when the hack pin is asserted. the size of the host dma word to be transferred is determined by the host mode 0 (hm0) bit. the hi8 register selected during a host dma transfer is determined by a 2-bit address counter, preloaded with the value in hm1 and hm0. the address counter substitutes for the host address inputs, ha1 and ha0 during a host dma transfer. the host address input ha2 is forced to 1 during each host dma transfer. the address counter can be initialized when the init bit is set. after each dma transfer, the address counter is incriminated to the next register. table 16-9. mode (hm1, hm0) bit definition (hrms = 0) hm1 hm0 mode 0 0 interrupt mode (hdma off) 01 illegal 1 0 hdma mode; 16-bit 1 1 hdma mode; 8-bit host side registers host interface eight (hi8), rev. 4 freescale semiconductor 16-21 when the address counter reaches the highest register (rxl or txl), the address counter is not incriminated but is loaded with the value in hm1 and hm0. this allows 8- or 16-bit data to be transferred in a circular fashion and eliminates the need for the dma controller to supply the host address ha2, ha1, and ha0 pins. for 16-bit data transfers, the dsc interrupt rate is reduced by a factor of two from the host request rate. hm1 and hm0 are cleared by dsc reset. note: when operating in 8-bit hdma mode, the hlend affects the location (upper or lower byte) of the 8-bit value in the dsc register (hrx/htx). for example, in host-to-dsc transfers, if hlend = 0 the transferred data is placed in the lower half of the hrx register. if hlend = 1 the data would appear in the upper half of the register. note: prior to initiating an 8-bit host-to-dsc transfer the host should ensure the txh/txl registers at address 6 is initialized to 0 because the contents of this register are transferred with the txl/txh register to the hrx register. 16.9.1.3 host flag 1 (hf1)?bit 4 the host flag 1 (hf1) bit is used as a general purpose flag for host-to-dsc communication. the hf1 bit can be set or cleared by the host processor, but cannot be changed by the dsc core. the hf1 bit is reflected in the hsr on the dsc side. the hf1 bit is cleared on dsc reset. 16.9.1.4 host flag 0 (hf0)?bit 3 the host flag 0 (hf0) bit is used as a general purpose flag for host-to-dsc communication. the hf0 bit can be set or cleared by the host processor, but cannot be changed by the dsc core. the hf0 bit is reflected in the hsr on the dsc side. the hf0 bit is cleared on dsc reset. 16.9.1.5 icr host little endian (hlend)?bit 2 the host little endian (hlend) bit allows the hi8 to be accessed by the host in little endian or big endian data order. when the hlend bit is set, the hi8 can be accessed by the host in little endian order. the rxh/txh is located at address $7 and rxl/txl at $6. when the hlend bit is cleared, the hi8 can be accessed by the host in big endian host data order. the rxh/txh is located at address $6 and rxl/txl at $7. the hlend bit is cleared on hardware reset. host side registers 5685x digital signal controller user manual, rev. 4 16-22 freescale semiconductor 16.9.1.6 icr transmit request enable (treq)?bit 1 the transmit request enable (treq) bit is used to control the hreq pin for host transmit data transfers. in the interrupt mode, and the dma is off, treq is used to enable interrupt requests via the external host request (hreq or htrq ) pin when the transmit data register empty (txde) status bit in the interrupt status register (isr) is set. when treq is cleared, txde interrupt is disabled. when treq is set, the external host request hreq or htrq pin is asserted if txde is set in the interrupt mode. in dma modes, the treq must be set or cleared by software to select the direction of dma transfers. setting treq sets the direction of the dma transfer to be from host-to-dsc and enables the hreq pin to request these data transfers. 16.9.1.7 receive request enable (rreq)?bit 0 this bit is used to control the hreq pin for host receive data transfers. in the interrupt mode (hdma off), the rreq is used to enable interrupt requests via the external host request (hreq or hrrq ) pin when the receive data register full (rxdf) status bit in the interrupt status register (isr) is set. when rreq is cleared, rxdf interrupts are disabled. when rreq is set, the external host request hreq pin or hrrq is asserted if rxdf is set in interrupt mode. in hdma modes, the rreq bit must be set or cleared by software to select the direction of dma transfers. setting the rreq bit sets the direction of the hdma transfer to be from the dsc-to-host, enabling the hreq pin to request these data transfers. rreq is cleared by dsc reset. table 16-10 , table 16-11 , and table 16-12 summarizes the effect of rreq and treq on the hreq /htrq and hack /hrrq pins. treq is cleared by dsc reset. table 16-10. hreq pin definition?interrupt mode (hrms = 0, hm1 = hm0 = 0) treq rreq hreq pin 0 0 no interrupts (polling) 0 1 rxdf request (interrupt) 1 0 txde request (interrupt) 1 1 rxdf and txde request (interrupt) host side registers host interface eight (hi8), rev. 4 freescale semiconductor 16-23 16.9.2 command vector register (cvr) the command vector register (cvr) is used by the host processor, causing the dsc core to execute an interrupt. the host command feature is independent of any of the data transfer mechanisms in the hi8. the host interface can execute any of the 128 possible interrupt requests to the dsc core. please refer to the interrupt controller (itcn) chapter for further details. figure 16-11. command vector register (cvr) see programmer?s sheet on appendix page b - 142 16.9.2.1 host command (hc)?bit 7 this bit is used by the host processor to handshake the execution of host command interrupts. normally, the host processor sets hc = 1 to request the host command interrupt from the dsc core. when the host command interrupt is acknowledged by the dsc core the hc bit is cleared by the hi8 hardware. the host processor can read the state of the hc bit to determine when the host command has been accepted. after writing hc = 1 to the cvr, the host must not write to the cvr again until the hc bit is cleared by the hi8 hardware. setting the hc bit causes host command pending to be set in the host status register. table 16-11. hreq pin definition?host mode (hrms = 0, hm1, hm0 set for dma) treq rreq rreq pin 0 0 dma transfers disabled 0 1 dsc?> host request (rx) 1 0 host?> dsc request (tx) 1 1 undefined (illegal) table 16-12. htrq and hrrq interrupt mode (hrms = 1) treq rreq htrq pin hrrq pin 0 0 no interrupts (polling) no interrupts (polling) 0 1 no interrupts (polling) rxdf request (interrupt) 1 0 txde request (interrupt) no interrupt (polling) 1 1 txde request (interrupt) rxdf request (interrupt) base + $1 7 6 5 4 3 2 1 0 read hc hv6 hv5 hv4 hv3 hv2 hv1 hv0 write reset 00000 0 00 servicing the host interface 5685x digital signal controller user manual, rev. 4 16-24 freescale semiconductor 16.9.2.2 cvr host vector (hv)?bits 6?0 these seven bits select the host command interrupt offset address in the vector table to be used by the host command interrupt logic. when the host command interrupt is recognized by the dsc interrupt control logic the offset address of the interrupt vector table taken is 2 hvi0, 6. the host can write hc and hv in the same write cycle. the host processor can select any of the 128 possible offset addresses of the interrupt vector table in the dsc by writing this address divided by 2, and equal to the vector number, into hv bits. this means the host processor can force any of the existing interrupt handlers, sw interrupts such as essi, sci, irqa, or irqb and can use any of the reserved or otherwise unused interrupt vectors. 16.10 servicing the host interface the hi8 can be serviced by using one of the following protocols: ? polling ? interrupts ? host dma from the host processor viewpoint, the service consists of making a data transfer because this is the only way to reset the appropriate status bits. 16.10.1 interface status register (isr) the interface status register (isr) is an 8-bit read-only status register used by the host processor to interrogate the status and flags of the hi8. the host processor can write this address without affecting the internal state of the hi8, useful to access all of the hi8 registers by stepping through the hi8 addresses. the isr can not be accessed by the dsc core. the status bits are described in the following paragraphs. figure 16-12. interface status register (isr) see programmer?s sheet on appendix page b - 143 base + $2 7 6 5 4 3 2 1 0 read hreq dma 0 hf3 hf2 trdy txde rxdf write 0 reset 00000 0 10 servicing the host interface host interface eight (hi8), rev. 4 freescale semiconductor 16-25 16.10.1.1 host request (hreq)?bit 7 this bit indicates the status of the external host request (hreq ) output pin if the hrms bit is cleared; or the external host transmit receive request (htrq ) output pins, and hrrq respectively, if hrms is set. when the hreq status bit is cleared, it indicates the host request pin, hreq or htrr , htrq and hrrq , are deasserted and either host processor interrupts or host dma transfers are being requested. if the hreq status bit is set, it means the host request (hreq ) pin, the host transmit request (htrq ), or host receive request (hrrq ) are asserted, indicating the dsc is interrupting the host processor or a host dma transfer request is being made. the hreq interrupt request may originate from one or more of two sources: 1. the receive byte registers are full 2. the transmit byte registers are empty these conditions are indicated by the interrupt status register (isr) rxdf and txde status bits, respectively. if the interrupt source has been enabled by the associated request enable bit in the interface control register (icr); hreq, htrq, or hrrq bits is set if one or more of the two enabled interrupt sources is set. dsc reset clears hreq. 16.10.1.2 host dma status (dma)?bit 6 the dma status bit (dma) indicates the host processor has enabled the dma mode of the hi8 (hm1 or hm0 =1). when the dma status bit is clear, it indicates the dma mode is disabled by the host mode bits (hm0 and hm1) in the interface control register (icr) and no dma operations are pending. when dma is set, it indicates the dma mode is enabled and the host processor should not use the active dma channel (rxh:rxl or txh:txl depending on dma direction) to avoid conflicts with the dma data transfers. note: this bit is always 0 if hrms = 1 in the host control register because the hreq and hack function is disabled, thereby disabling the host dma operations. 16.10.1.3 reserved bit?bit 5 this bit is reserved or not implemented. it is read as, and written with 0s. 16.10.1.4 host flag 3 (hf3)?bit 4 the host flag 3 (hf3) bit in the interrupt status register indicates the state of host flag 3 in the host control register on the dsc side. the hf3 bit can only be changed by the dsc side. please see figure 16-4 . servicing the host interface 5685x digital signal controller user manual, rev. 4 16-26 freescale semiconductor 16.10.1.5 host flag 2 (hf2)?bit 3 the host flag 2 (hf2) bit in the interface control register (isr) indicates the state of host flag 2 in the host control register on the dscdsc side. the hf2 bit can only be changed by the dsc side. please see figure 16-4 . 16.10.1.6 transmitter ready (trdy)?bit 2 the transmitter ready (trdy) flag bit indicates txh, txl, and the hrx registers are empty. when the trdy bit is set, the data the host processor writes to the txh and txl registers is immediately transferred to the dsc side of the hi8. the many applications can use this feature. for example, if the host processor issues a host command causing the dsc core to read the hrx, the host processor can be guaranteed the data transferred to the hi8 is being received by the dsc core. 16.10.1.7 transmit data register empty (txde)?bit 1 setting the transmit data register empty (txde) bit indicates the transmit byte registers (txh, and txl) are empty and can be written by the host processor. txde is set when the transmit byte registers are transferred to the hrx register. txde is cleared when the transmit txl/txh register (based on hlend setting, the one at address offset seven) is written by the host processor. txde can be set by the host processor using the initialize feature. txde may be used to assert the external hreq pin if the treq bit is set. regardless of whether the txde interrupt is enabled, txde provides valid status so polling techniques may be used by the host processor. 16.10.1.8 receive data register full (rxdf)?bit 0 setting the receive data register full (rxdf) flag bit indicates the receive byte registers (rxh and rxl) contain data from the dsc side and can be read by the host processor. the rxdf bit is set when the htx is transferred to the receive byte registers. rxdf is cleared when the receive data rxl/rxh (based on hlend setting, the one at address offset seven) is read by the host processor. rxdf can be used to assert the external hreq pin if the rreq bit is set. regardless of whether the rxdf interrupt is enabled, rxdf provides valid status so polling techniques may be used by the host processor. 16.10.2 interrupt vector register (ivr) the interrupt vector register (ivr) is an 8-bit read/write register typically containing the interrupt vector number used with mc68000 family processor vectored interrupts. only the host processor can read and write this register. the contents of ivr are placed on the host data bus (h0?h7) when both hreq and hack pins are asserted and host dma is not enabled. the servicing the host interface host interface eight (hi8), rev. 4 freescale semiconductor 16-27 contents of this register are initialized to a pre-defined value by a hardware or software reset, corresponding to the uninitialized interrupt vector in the mc68000 family . figure 16-13. interrupt vector register (ivr) see programmer?s sheet on appendix page b - 144 16.10.3 receive byte registers (rxh, rxl) the receive byte registers are viewed as two 8-bit read-only registers by the host processor. these registers are called receive data high (rxh) and receive data low (rxl). these two registers receive data from the high byte and low byte, respectively from the htx register. they are selected by three external host address (ha2, ha1, and ha0) inputs during a host processor read operation or by an on-chip address counter in dma operations. the receive byte registers contain valid data when the receive data register full (rxdf) bit is set. the host processor may program the rreq bit to assert the external hreq pin when the rxdf bit is set. this informs the host processor or host dma controller of the receive byte registers full condition. reading the data register at host address $7 clears the rxdf bit. ? when the hlend bit in the interface control register (icr) is cleared , the receive data register high (rxh) register is located at address $6 and rxl at $7. ? when the hlend bit in the icr is set , the rxh register is located at address $7 and the rxl register, at $6. figure 16-14. hi8 receive byte high register (rxh) see programmer?s sheet on appendix page b - 145 * depends on hlend setting base + $3 7 6 5 4 3 2 1 0 read iv7 iv6 iv5 iv4 iv3 iv2 iv1 iv0 write reset 00001111 base + $6/$7* 7 6 5 4 3 2 1 0 read rxh write reset 00000000 servicing the host interface 5685x digital signal controller user manual, rev. 4 16-28 freescale semiconductor figure 16-15. hi8 receive byte low register (rxl) see programmer?s sheet on appendix page b - 145 * depends on hlend setting 16.10.4 transmit byte registers (txh, txl) the transmit byte registers are viewed as two 8-bit write-only registers by the host processor. these registers are called transmit high (txh) and transmit low (txl). the two registers transmit data to the high byte and low byte, respectively from the hrx register. they are selected by three external host address (ha2, ha1, and ha0) inputs during a host processor write operation, or by an on-chip address counter in dma operations. data can be written into the transmit byte registers when the transmit data register empty (txde) bit is set. the host processor can program the treq bit to assert the external hreq pin when txde is set. this informs the host processor, or host dma controller the transmit byte registers are empty. writing the data register at host address $7 clears the txde bit. ? when the hlend bit in the icr is cleared , the txh register is located at address $6 and txl at $7. ? when the hlend bit in the icr is set , the txh register is located at address $7 and txl at $6. the transmit byte registers are transferred as 16-bit data to the hrx register when both txde and the hrdf bits are cleared. this transfer operation sets the txde and hrdf bits. figure 16-16. hi8 transmit byte high register (txh) see programmer?s sheet on appendix page b - 146 * depends on hlend setting base + $7/$6* 7 6 5 4 3 2 1 0 read rxl write reset 00000000 base + $6/$7* 7 6 5 4 3 2 1 0 read write txh reset 00000000 servicing the host interface host interface eight (hi8), rev. 4 freescale semiconductor 16-29 figure 16-17. hi8 transmit byte low register (txl) see programmer?s sheet on appendix page b - 146 * depends on hlend setting 16.10.5 host side registers after reset table 16-13 shows the result of the three kinds of reset on bits in each of the hi8 registers seen by the host processor. the hardware reset is caused by asserting the reset pin. execute the reset instruction to set the software reset. execute the stop instruction to set the stop reset. base + $7/$6* 7 6 5 4 3 2 1 0 read write txl reset 00000000 table 16-13. host side registers after reset register name register data reset type hardware reset software reset stop reset icr all bits 0 0 ? cvr hc 0 0 0 hv[6:0] $00 $00 ? isr hreq 0 0 1 if treq is set, 0 if treq is cleared dma 0 0 ? hf[3:2] 0 0 ? trdy 1 1 1 txde 1 1 1 rxdf 0 0 0 ivr iv[7:0] $0f $0f ? rx rxh:rxl empty empty empty tx txh:txl empty empty empty servicing the host interface 5685x digital signal controller user manual, rev. 4 16-30 freescale semiconductor 16.10.6 hi8 host processor data transfer the hi8 looks like static ram to the host processor. to transfer data with the hi8, the host processor must: ? assert the hi8 address to select the register to be read or written ? select the direction of the data transfer ? strobe the data transfer 16.10.7 polling in the polling mode of operation, the hreq pin is not connected to the host processor and hack must be negated, ensuring the ivr data is not being driven on h0?h7 when other registers are being polled. hack can also be configured as a gpio pin if the hack function is not required. figure 16-18 illustrates the host processor first performs a data read transfer to read the isr to determine, whether: ? rxdf = 1 indicates the receive data register is full, and a data read should be performed. ? txde = 1 indicates the transmit data register is empty, and a data write can be performed. ? when hreq = 1, the hreq pin has been asserted, and one of the previous two conditions exist. generally, after the appropriate data transfer has been made, the corresponding status bit is updated to reflect the transfer. if the host processor has issued a command to the dsc by writing to the cvr and setting the hc bit, it can read the hc bit in the cvr to determine when the command has been accepted by the interrupt controller in the dsc core. when the command has been accepted for execution, the hc bit is cleared by the interrupt controller in the dsc core.and/or rxdf = 1 and the corresponding enable bit (treq or rreq, respectively) are set. this procedure is depicted in figure 16-18 . servicing the host interface host interface eight (hi8), rev. 4 freescale semiconductor 16-31 figure 16-18. hi8 host request structure 16.10.8 servicing interrupts when hreq is connected to the host processor interrupt input, the hi8 can request service from the host processor by asserting hreq. hreq is asserted when txde = 1. generally, servicing the interrupt begins with reading the interface status register (isg21r) to determine which dsc flag has generated the interrupt. the host processor interrupt service routine must read or write the appropriate hi8 register in order to clear the interrupt. hreq is deasserted when the enabled request is cleared or masked. the host processor interrupts are external and use the hreq pin. hreq is normally connected to the host processor maskable interrupt input. the host processor acknowledges host interrupts by executing an interrupt service routine. the two lsbs (rxdf and txde) of the interrupt status register may be tested by the host processor to determine the interrupt source. please refer to figure 16-18 . the host processor interrupt service routine must read or write the appropriate hi8 register in order to clear the interrupt. hreq is deasserted when one of the following occurs: ? the enabled request is cleared or masked ? the dsc is reset 76 543210 rxdf txde trdy hf2 hf3 dma hreq isr 76543210 rre q tre q hlend hf0 hf1 hm0 hm1 init icr host request asserted hrrq hreq htrq status enable reserved hf3 txde hf3 servicing the host interface 5685x digital signal controller user manual, rev. 4 16-32 freescale semiconductor in the case where the host processor is a member of the mc680xx family , servicing the interrupt starts by asserting hreq to interrupt the processor. the host processor then acknowledges the interrupt by asserting hack . when hreq and hack are simultaneously asserted, the contents of the ivr are placed on the host data bus. this vector tells the host processor which routine to use to service the hreq interrupt. 16.10.9 host side dma mode operation the host dma mode allows the transfer of 8-bit or 16-bit data between the dsc hi8 and an external dma controller. the hi8 provides the synchronization logic between the two asynchronous processor systems. the dsc side of the interface is serviced by any appropriate servicing mechanism such as polling, interrupts, or dma transfer. the external dma controller provides the transfers between the dsc hi8 registers and the external dma memory. the external dma controller must provide the address to the external dma memory. the address of the selected hi8 register is provided by a dma address counter in the dsc hi8. 16.10.9.1 host-to-dsc host interface action the following four procedure outlines the steps the hi8 hardware takes to transfer dma data from the host data bus to dsc memory. 1. assert the host request hreq output pin when the transmit byte registers txh/txl are empty. this always occurs in host-to-dsc dma mode when txde = 1. 2. write the selected transmit byte register from the host data bus when the hack input pin is asserted by the dma controller. deassert the hreq pin. 3. if the highest register address has not been reached, such as txde = 1, post-increment the dma address counter to select the next register. wait until hack is deasserted then go to step 1. 4. if the highest register address has been reached, such as txde = 0, load the dma address counter with the value in hm1 and hm0 and transfer the transmit byte registers txh:txl to the host receive data register hrx when hrdf = 0. this sets hrdf = 1. wait until hack is deasserted then go to step 1. note: the dsc-to-host data transfers can occur normally in the channel not used for dma except when the host must use polling and not interrupts. note: the transfer of data from the txh/txl register to the hrx register automatically loads the dma address counter from the hm1 and hm0 bits in the dma host-to-dsc mode. servicing the host interface host interface eight (hi8), rev. 4 freescale semiconductor 16-33 the host exception is triggered when hrdf = 1. the host exception routine must read the host receive data register hrx to clear hrdf. the transfer from steps 4 to 1 is automatic if txde = 1. note: the execution of the host exception on hrdf = 1 condition occurs after the transfer to step 1 and is independent of the handshake since it is only dependent on hrdf = 1. 16.10.9.2 host-to-dsc host processor procedure the following procedure outlines the typical steps that the host processor must take to setup and terminate a host-to-dsc dma transfer. 1. setup the external dma controller source address, direction, byte count, and other control registers. enable the dma controller channel. 2. the dsc must be configured to handle the incoming host data via polling, interrupts, or dsc side dma configuration. if interrupt operation is desired hrie must be set to enable the hrdf interrupt. if dsc side dma operations are desired, set rdmae to enable dsc transfers when hrdf is set. this could be done with a separate host command exception routine in the dsc. 3. set txde and clear hrdf. this can be done with the appropriate initialize function. the host must also initialize the dma counter in the hi8 using the initialize feature. hreq output pin is asserted immediately by the dsc hardware which begins the dma transfer. 4. perform other tasks until interrupted by the dma controller dma complete interrupt. the dsc interface control register (icr), the interrupt status register (isr), and rxh/rxl may be accessed at any time by the host processor (using ha0-ha2, hrw/hrd , hds /hwr , and hcs ) but the transmit byte registers (txh/txl) may not be accessed until the dma mode is disabled. 5. terminate the dma controller channel to disable dma transfers. 6. terminate the dsc hi8 dma mode by clearing the hm1 and hm0 bits and clearing treq in the interface control register (icr). 16.10.9.3 dsc-to-host interface action the following procedure outlines the steps that the hi8 hardware takes to transfer dma data from dsc memory to the host data bus. 1. the transmit exception is triggered when htie = 1 and htde = 1, for interrupt mode transfers, or when tdmae = 1 and htde = 1, for on-chip dma transfers. the exception routine software, or on-chip dma, writes the data word into htx. servicing the host interface 5685x digital signal controller user manual, rev. 4 16-34 freescale semiconductor 2. transfer the htx register to the receive byte registers rxh/rxl when they are empty (rxdf = 0). this automatically occurs. load the host dma address counter from hm1 and hm0. this action sets htde = 1 and trigger another dsc transmit exception to write htx. 3. assert the host request (hreq ) pin when the receive byte registers are full. 4. enable the selected receive byte register on the host data bus when hack is asserted. deassert the host request hreq pin. 5. if the highest register address has not been reached (i.e., rxdf = 1), post-increment the hi8 dma address counter to select the next register. wait until hack is deasserted, then go to step 3. 6. if the highest register address has been reached (i.e., rxdf = 0), wait until hack is deasserted then go to step 2. the dsc transmit exception must have written htx (i.e., htde = 0) before step 2 is executed. note: the host ?> dsc data transfers can occur normally in the channel not used for dma except when the host must use polling and not interrupts. note: the transfer of data from the htx register to the rxh/rxl registers automatically loads the hi8 dma address counter from the hm1 and hm0 bits when in dma dsc-to-host mode. 16.10.9.4 dsc-to-host processor procedure the following procedure outlines the typical steps the host processor must take to setup and terminate a dsc-to-host dma transfer. 1. setup the external dma controller destination address, direction, byte count, and other control registers. enable the dma controller channel. 2. the dsc must be configured to provide the outgoing data via polling, interrupts, or dsc side dma configuration. if interrupt operation is desired htie must be set to enable the htde interrupt. if dsc side dma operations are desired, set tdmae to enable dsc transfers when htde is set. this could be done with a separate host command exception routine in the dsc. 3. set htde and clear rxdf. this can be done with the appropriate init function. the dsc host transmit exception is activated immediately by dsc hardware which begins the dma transfer. 4. perform other tasks until interrupted by the dma controller dma complete interrupt. the dsc interface control register (icr), the interrupt status register (isr), and txh/txl may be accessed at any time by the host processor (using ha0-ha2, hrw/hrd , servicing the host interface host interface eight (hi8), rev. 4 freescale semiconductor 16-35 hds /hwr , and hcs ) but the receive byte registers (rxh and rxl) may not be accessed until the dma mode is disabled. 5. terminate the dma controller channel to disable dma transfers. 6. terminate the dsc hi8 dma mode by clearing the hm1 and hm0 bits and clearing rreq in the interface control register (icr). 16.10.10 host port use considerations careful synchronization is required when reading multi-bit registers written by another asynchronous system. this is a common problem when two asynchronous systems are connected. the situation exists in the host port. however, if the port is used in the way it was designed, proper operation is guaranteed. the considerations for proper operation are discussed below. 16.10.10.1 host programmer considerations 1. unsynchronized reading of receive byte registers. when reading receive byte registers, rxh or rxl, the host programmer should use interrupts or poll the rxdf flag indicating data is available. this guarantees the data in the receive byte registers are stable. 2. overwriting transmit byte registers. the host programmer should not write to the transmit byte registers, txh or txl, unless the txde bit is set, indicating the transmit byte registers are empty. after writing, time must be allowed for txde to update. from the rising edge of the clock effecting write of the tx register pair high order byte (address 0x7) to the valid indication of txde is a period of two dsc clock cycles. this guarantees the dsc will read stable data when it reads the hrx register. 3. synchronization of status bits from dsc-to-host. hc, hreq, dma, hf3, hf2, trdy, txde, and rxdf status bits are set or cleared from inside the dsc and read by the host processor. the host can not read these status bits very quickly without regard to the clock rate used by the dsc there is a chance the state of the bit could be changing during the read operation. this is generally not a system problem because the bit is read correctly in the next pass of any host polling routine. however, if the host holds the hcs input pin for the minimum assert time plus 1.5 clock cycles, the status data is guaranteed to be stable. the 1.5 clock cycles is first used to synchronize the hcs signal and then to block internal updates of the status bits. there is no other minimum hcs assert time relationship to the dsc clocks. there is a minimum hcs deassert time of 1.5 clock cycles so that the blocking latch can be deasserted to allow updates if the host is in a tight polling loop. this only applies to reading status bits. servicing the host interface 5685x digital signal controller user manual, rev. 4 16-36 freescale semiconductor the only potential system problem with the uncertainty of reading any status bits by the host is hf3 and hf2 as an encoded pair. for example, if the dsc changes hf3 and hf2 from 00 to 11, there is a very small probability the host could read the bits during the transition and receive 01 or 10 instead of 11. if the combination of hf3 and hf2 has significance, the host would potentially read the wrong combination. solutions: ? read the bits twice and check for consensus. ? assert hcs access for hcs + 1.5 clock cycles so the status bit transitions are stabilized. 4. overwriting the host vector the host programmer should change the host vector register only when the host command (hc) bit is clear. this guarantees the dsc interrupt control logic receives a stable vector. 5. cancelling a pending host command exception the host processor may elect to clear the hc bit to cancel the host command exception request at any time before it is recognized by the dsc. the dsc may execute the host exception after the hc bit is cleared: ? because the host does not know exactly when the exception is recognized ? because of synchronization ? because of exception processing pipelining. as a result, the hv must not be changed at the same time the hc bit is cleared. in this way, if the exception was taken, the vector is known. 16.10.10.2 dsc programmer considerations reading hf1 and hf0 as an encoded pair: ?dma ?hf1 ?hf0 ?hcp ?htde ?hrdf jtag port, rev. 4 freescale semiconductor 17-1 chapter 17 jtag port 5685x digital signal controller user manual, rev. 4 17-2 freescale semiconductor introduction jtag port, rev. 4 freescale semiconductor 17-3 17.1 introduction this chapter describes the 56f800e core-based family of chips, providing board and chip-level debugging and high-density circuit board testing specific to joint test action group (jtag). the 5685x provides board and chip-level testing capability through two on-chip modules, both accessed through the jtag port/eonce module interface: ? enhanced on-chip emulation (eonce) module ? test access port (tap) and 16-state controller, also known as the jtag port presence of the jtag port/eonce module interface permits insertion of the dsc chip into a target system while retaining debug control. this capability is especially important for devices without an external bus, because it eliminates the need for an expensive cable to bring out the chip footprint required by a traditional emulator system. the enhanced once (eonce) module is used in digital signal controller (dsc) chips to debug application software employed with the chip. the port is a separate on-chip block allowing non-intrusive dsc interaction with accessibility through the pins of the jtag interface. the eonce module makes it possible to examine registers, memory, or on-chip peripherals? contents in a special debug environment. this avoids sacrificing any user-accessible, on-chip resources to perform debugging procedures. please refer to the dsp56f800e core-based reference manual (dsp56800erm)for details about implementation of the 5685x eonce module. the jtag port is a dedicated user-accessible tap compatible with the ieee 1149.1a-1993 standard test access port and boundary scan architecture . problems associated with testing high-density circuit boards have led to the development of this proposed standard under the sponsorship of the test technology committee of ieee and the jtag. 5685x supports circuit board test strategies based on this standard. six dedicated pins interface to the tap containing a 16-state controller. the tap uses a boundary scan technique to test the interconnections between integrated circuits after they are assembled onto a printed circuit board (pcb). boundary scans allow observation and control signal levels at each component pin through a shift register placed next to each pin. this is important for testing continuity and determining if pins are stuck at a one or zero level. features 5685x digital signal controller user manual, rev. 4 17-4 freescale semiconductor 17.2 features features of the test access port (tap) port include: ? perform boundary scan operations to test circuit board electrical continuity ? bypass the tap for a given circuit board test by replacing the boundary scan register (bsr) with a single-bit register ? sample system pins during operation and transparently shift-out the results in the bsr ? preload output pins prior to invoking the extest instruction ? disable the output drive to pins during circuit board testing ? provide a means of accessing the eonce module controller and circuits to control a target system ? query the idcode from any tap in the system ? force test data onto the peripheral outputs while replacing its bsr with a single bit register ? enable/disable pull-up devices on peripheral boundary scan pins 17.3 master test access port (tap) the master tap consists of: ? synchronous finite 16-bit state machine ? eight-bit instruction register (ir) ? chip identification (cid) register ? bypass (bypass) register ? boundary scan register (bsr) please see figure 17-1 for additional information. 17.3.1 signal description as described in ieee 1149.1a, the jtag port requires a minimum of four pins to support tdi, tdo, tck, and tms signals. the 5685x also uses the optional trst input signal and the de output signal used by the eonce module interface. pin functions are described in table 17-1 . tap block diagram jtag port, rev. 4 freescale semiconductor 17-5 17.4 tap block diagram figure 17-1. test access port (tap) block diagram table 17-1. jtag pin descriptions pin name pin description tdi test data input ?this input pin provides a serial input data stream to the jtag and the eonce modules. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. tdo test data output ?this tri-state output pin provides a serial output data stream from the jtag and the eonce modules. it is driven in the shift-ir and shift-dr controller states of the jtag state machine and changes on the falling edge of tck. tck test clock input ?this input pin provides the clock to synchronize the test logic and shift serial data to and from all tap controllers and the tlm. if the eonce module is not being accessed using the master tap controllers, the maximum tck frequency is 1/4 the maximum frequency for the 56800e core. when accessing the eonce module through the 56800e core tap controller, the maximum frequency for tck is 1/8 the maximum frequency for the 56800e core. the tck pin has an on-chip pull-down resistor. tms test mode select input ?this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. trst test reset ?this input provides a reset signal to the jtag tap controller. the trst pin has an on-chip pull-up resistor. de debug event ?this output signal debugs events detected on a trigger condition. boundary scan register instruction decode tdi tdo tap tms tck trst idcode register bypass register instruction register controller jtag port architecture 5685x digital signal controller user manual, rev. 4 17-6 freescale semiconductor 17.5 jtag port architecture the tap controller is a simple state machine used to sequence the jtag port through its varied operations: ? serially shift in or out a jtag port command ? update and decode the jtag port instruction register (jtagir) ? serially input or output a data value ? update a jtag port or eonce module register note: the jtag port supervises the shifting of data into and out of the eonce module through tdi and tdo pins respectively. in this case, the shifting is guided by the same controller used when shifting jtag information. the jtag block diagram is illustrated in figure 17-1 . the jtag port has four read/write registers: 1. instruction register (jtagir) 2. chip identification (cid) register 3. bypass register (jtagbr) 4. boundary scan register (bsr) access to the eonce registers is described in the dsp56800e reference manual . 17.5.1 jtag instruction register (jtagir) and decoder the tap controller contains a 8-bit instruction register. the instruction is presented to an instruction decoder during the update-instruction register state. please see section 17.8 for a description of the tap controller operating states. the instruction decoder interprets and executes the instructions according to the conditions defined by the tap controller state machine. the 5685x includes the three mandatory public instructions: 1. bypass 2. sample/preload 3. extest jtag port architecture jtag port, rev. 4 freescale semiconductor 17-7 the 5685x includes four public instructions: 1. clamp 2. highz 3. idcode 4. tlm_select the eight bits b[7:0] of the ir, decode the nine instructions, illustrated in figure 17-2 and its data provided in table 17-2 . all other encodings are reserved. figure 17-2. jtagir register caution reserved jtag instruction encodings should not be used. hazardous operation of the chip could occur if these instructions are used. table 17-2. master tap instructions opcode instruction target register opcode extest boundary 00000000 bypass bypass 11111111 sample_preload boundary 00000001 idcode idcode 00000010 tlm_sel tlm 00000101 highz bypass 00000110 clamp bypass 00000111 reserved reserved 00000011 reserved reserved 00000100 reserved reserved 00001000 ir 7 6 5 4 3 2 1 0? read/write b7 b6 b5 b4 b3 b2 b1 b0 reset 00000010 jtag port architecture 5685x digital signal controller user manual, rev. 4 17-8 freescale semiconductor 17.5.1.1 external test instruction (extest) the external test (extest) instruction enables the bsr between tdi and tdo, including cells for all digital device signals and associated control signals. the extal and reset pins, and any codec pins associated with analog signals, are not included in the bsr path. in extest, the bsr is capable of scanning user-defined values onto output pins, capturing values presented to input signals, and controlling the direction and value of bidirectional pins. extest instruction asserts internal system reset for the dsc system logic during its run in order to force a predictable internal state while performing external boundary scan operations. 17.5.1.2 bypass instruction (bypass) the bypass instruction enables the single-bit bypass register between tdi and tdo, illustrated in figure 17-3 . this creates a shift register path from tdi to the bypass register and finally to tdo, circumventing the bsr. this instruction is used to enhance test efficiency by shortening the overall path between tdi and tdo when no test operation of a component is required. in this instruction, the system logic is independent of the tap. when this instruction is selected, the test logic has no effect on the operation of the on-chip system logic, required in ieee 1149.1-1993a. 17.5.2 sample and preload instructions (sample/preload) the sample/preload instruction enables the bsr between tdi and tdo. when this instruction is selected, the test logic operation has no effect on the operation of the on-chip system logic. nor does it have an effect on the flow of a signal between the system pin and the on-chip system logic, specified by ieee 1149.1-1993a. this instruction provides two separate functions. 1. first, it provides a means to obtain a snapshot of system data and control signals (sample). the snapshot occurs on the rising edge of tck in the capture-dr controller state. the data can be observed by shifting it transparently through the bsr. in a normal system configuration, many signals require external pull-ups assuring proper system operation. consequently, the same is true for the sample/preload figure 17-3. bypass register diagram dq shift_dr clock_dr ck tdi to tdo mux jtag port architecture jtag port, rev. 4 freescale semiconductor 17-9 functionality. data latched into the bsr during the capture-dr controller state may not match the drive state of the package signal if the system requiring pull-ups are not present within the test environment. 2. the second function of the sample/preload instruction is to initialize the bsr output cells (preload) prior to selection of the clamp or extest instruction. this initialization ensures known data appears on the outputs when executing extest. the data held in the shift register stage is transferred to the output latch on the falling edge of tck in the update data register (dr) controller state. data is not presented to the pins until the clamp or extest instruction is executed. note: since there is no internal synchronization between the jtag clock (tck) and the system clock (clk), some form of external synchronization to achieve meaningful results when sampling system values using the sample/preload instruction must be provided. 17.5.2.1 identification code instruction (idcode) the idcode instruction enables the idregister between tdi and tdo. it is provided as a public instruction to allow the manufacturer part number and version of a component to be determined through the tap. 17.5.2.2 tap linking module select (tlm_sel) tlm_sel instruction is a user-defined jtag instruction. it is used to disable the master tap and enable the tap linking module (tlm). the tlm provides a means of connecting one or more taps in a multi-tap design, responding to the ic?s test pins in ieee 1149.1 scan operations. tlm serves as a community data register used to set the tap linking configuration desired. the tlm register is a 4-bit register, illustrated in figure 17-3 , and enabled between tdi and tdo during a shift data register (dr) operation. it is updated on the update dr operation. table 17-3. tlm register update dr (load) shift dr (capture) bit master tap n/a 0 56800e tap n/a 1 n/c n/a 2 n/c n/a 3 jtag port architecture 5685x digital signal controller user manual, rev. 4 17-10 freescale semiconductor 17.5.2.3 high z instruction (highz) the highz instruction enables the single-bit bypass register between tdi and tdo. it is provided as a public instruction in order to prevent having to drive the output signals back during circuit board testing. when the highz instruction is invoked, all output drivers are placed in an inactive-drive state. highz asserts internal system reset for the system logic for the duration of highz in order to force a predictable internal state while performing external boundary scan operations. 17.5.3 jtag chip identification (cid) register the chip identification (cid) register is a 32-bit register providing a unique jtag id for the dsp56853/54/55/57/58. it is offered as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the tap. figure 17-4 illustrates the cid register configuration. figure 17-4. jtag chip identification (cid) register the device identification number for the initial release of the 5685x family is $01f5a01d. cir = $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pnum 3 pnum 2 pnum 1 pnum 0 mfg id 11 mfg id 10 mfg id 9 mfg id 8 mfg id 7 mfg id 6 mfg id 5 mfg id 4 mfg id 3 mfg id 2 mfg id 1 mfg id 0 write reset 1010000000011101 cir = $2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 read ver 3 ver 2 ver 1 ver 0 pnum 15 pnum 14 pnum 13 pnum 12 pnum 11 pnum 10 pnum 9 pnum 8 pnum 7 pnum 6 pnum 5 pnum 4 write reset 0000000111110101 jtag boundary scan register (bsr) jtag port, rev. 4 freescale semiconductor 17-11 17.6 bypass register (bypass) the jtag bypass register is a one-bit register used to provide a simple, direct path from the tdi pin to the tdo pin. this is useful in boundary scan applications where many chips are serially connected in a daisy-chain. individual dscs, or other devices, can be programmed with the bypass instruction so individually they become pass-through devices during testing. this allows testing of a specific chip, while still having all of the chips connected through the jtag ports. figure 17-5. jtag bypass register (jtagbr) 17.7 jtag boundary scan register (bsr) the jtag boundary scan register (bsr) is configured as described in figure 17-6 . this register is enabled via the jtag master tap by issuing the extest, or sample_preload instructions enabling the boundary scan registers between tdi and tdo. boundary scan register cell number one is connected to tdo making it the first data bit shifted into tdi. it is the first bit shifted out of tdo when loading and unloading the boundary scan chain. for the most current bsdl files, please refer to www.freescale.com . figure 17-6 illustrates the register, while table 17-5 provides the contents of the bsr for the 5685x. figure 17-6. boundary scan register (bsr) table 17-4. device id register bit assignment bit no. code use 56853/854/855/857/858 values 31?28 version number 0000 (for initial version only?these bits may vary) 27?22 design center id 00 0111 21?12 family and part id 11 0101 1010 11-1 manufacturer id 000 0000 1110 0 ieee requirement always 1 ir = $0, $1, $3 337 336 335 334 333 bits 332 through 5 43210 read-only ir = $6, $7, $ff read/write reset 0 jtag boundary scan register (bsr) 5685x digital signal controller user manual, rev. 4 17-12 freescale semiconductor table 17-5. bsr contents for 5685x bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) 0 miso input/output bc_7 11?11b2 1 pull-up bc_1 2 control bc_2 3 mosi input/output bc_7 2 2 ? 2 2 c3 4 pull-up bc_1 5 control bc_2 6 sck input/output bc_7 33?33c2 7 pull-up bc_1 8 control bc_2 9 ss input/output bc_7 4 4 ? 4 4 d2 10 pull-up bc_1 11 control bc_2 12 rd input/output bc_7 773?8d3 13 pull-up bc_1 14 control bc_2 15 wr input/output bc_7 8 8 4 ? 9 d4 16 pull-up bc_1 17 control bc_2 18 a0 input/output bc_7 995?10e5 19 pull-up bc_1 20 control bc_2 21 a1 input/output bc_7 10 10 6 ? 11 e4 22 pull-up bc_1 23 control bc_2 24 a2 input/output bc_7 11 11 7 ? 12 e3 25 pull-up bc_1 26 control bc_2 27 a3 input/output bc_7 12 12 8 ? 13 e2 28 pull-up bc_1 29 control bc_2 30 mdoa input/output bc_7 15 15 11 10 17 f4 31 pull-up bc_1 32 control bc_2 33 modb input/output bc_7 16 16 12 11 18 f3 34 pull-up bc_1 35 control bc_2 jtag boundary scan register (bsr) jtag port, rev. 4 freescale semiconductor 17-13 36 modc input/output bc_7 17 17 13 12 19 f2 37 pull-up bc_1 38 control bc_2 39 * internal bc_1 ? ? ? ? ? ? 40 irqa input bc_1 20 20 16 15 22 g2 41 pull-up bc_1 42 irqb input bc_1 21 21 17 16 23 f5 43 pull-up bc_1 44 a4 input/output bc_7 26 26 22 ? 29 j2 45 pull-up bc_1 46 control bc_2 47 a5 input/output bc_7 27 27 23 ? 30 h3 48 pull-up bc_1 49 control bc_2 50 a6 input/output bc_7 28 28 24 ? 31 g4 51 pull-up bc_1 52 control bc_2 53 a7 input/output bc_7 29 29 25 ? 32 h4 54 pull-up bc_1 55 control bc_2 56 hd0 input/output bc_7 30 30 ? 22 33 j3 57 pull-up bc_1 58 control bc_2 59 hd1 input/output bc_7 31 31 ? 23 34 k2 60 pull-up bc_1 61 control bc_2 62 hd2 input/output bc_7 3232?2435l2 63 pull-up bc_1 64 control bc_2 65 clko output bc_1 33 33 26 26 37 l3 66 control bc_1 67 rsto output bc_1 34 34 27 27 38 k3 68 control bc_1 69 hd3 input/output bc_7 36 36 ? 29 40 j4 70 pull-up bc_1 71 control bc_2 table 17-5. bsr contents for 5685x (continued) bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) jtag boundary scan register (bsr) 5685x digital signal controller user manual, rev. 4 17-14 freescale semiconductor 72 hd4 input/output bc_7 3737?3041l4 73 pull-up bc_1 74 control bc_2 75 hd5 input/output bc_7 38 38 ? 31 42 j5 76 pull-up bc_1 77 control bc_2 78 hd6 input/output bc_7 39 39 ? 32 43 k5 79 pull-up bc_1 80 control bc_2 81 hd7 input/output bc_7 40 40 ? 33 44 h5 82 pull-up bc_2 83 control bc_2 84 a8 input/output bc_7 43 43 31 ? 48 g5 85 pull-up bc_1 86 control bc_2 87 a9 input/output bc_7 44 44 32 ? 49 l5 88 pull-up bc_1 89 control bc_2 90 a10 input/output bc_7 45 45 33 ? 50 j6 91 pull-up bc_1 92 control bc_2 93 a11 input/output bc_7 46 46 34 ? 51 k6 94 pull-up bc_1 95 control bc_2 96 de input/output bc_7 49 49 37 39 55 h6 97 pull-up bc_1 98 control bc_2 99 * internal bc_1 ? ? ? ? ? ? 100 a12 input/output bc_7 57 57 45 ? 63 j8 101 pull-up bc_1 102 control bc_2 103 a13 input/output bc_7 58 58 46 ? 64 k8 104 pull-up bc_1 105 control bc_2 106 a14 input/output bc_7 59 59 47 ? 65 l9 107 pull-up bc_1 108 control bc_2 table 17-5. bsr contents for 5685x (continued) bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) jtag boundary scan register (bsr) jtag port, rev. 4 freescale semiconductor 17-15 109 a15 input/output bc_7 60 60 48 ? 66 k9 110 pull-up bc_1 111 control bc_2 112 rxd0 input/output bc_7 65 65 51 51 73 l10 113 pull-up bc_1 114 control bc_2 115 txd0 input/output bc_7 66 66 52 52 74 l11 116 pull-up bc_1 117 control bc_2 118 a16 input/output bc_7 67 67 53 ? 75 k10 119 pull-up bc_1 120 control bc_2 121 a17 input/output bc_7 68 68 54 ? 76 k11 122 pull-up bc_1 123 control bc_2 124 a18 input/output bc_7 69 69 55 ? 77 j9 125 pull-up bc_1 126 control bc_2 127 a19 input/output bc_7 70 70 56 ? 78 j10 128 pull-up bc_1 129 control bc_2 130 a20 input/output bc_7 71 71 57 ? 79 j11 131 pull-up bc_1 132 control bc_2 133 d0 input/output bc_7 73 73 59 ? 81 h7 134 pull-up bc_1 135 control bc_2 136 cs0 input/output bc_7 75 75 61 55 83 h8 137 pull-up bc_1 138 control bc_2 139 cs1 input/output bc_7 76 76 62 56 84 h9 140 pull-up bc_1 141 control bc_2 142 cs2 input/output bc_7 77 77 63 57 85 h11 143 pull-up bc_1 144 control bc_2 table 17-5. bsr contents for 5685x (continued) bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) jtag boundary scan register (bsr) 5685x digital signal controller user manual, rev. 4 17-16 freescale semiconductor 145 cs3 input/output bc_7 78 78 64 58 86 h10 146 pull-up bc_1 147 control bc_2 148 ha0 input/output bc_7 82 82 ? 62 90 g10 149 pull-up bc_1 150 control bc_2 151 ha1 input/output bc_7 83 83 ? 63 91 g11 152 pull-up bc_1 153 control bc_2 154 ha2 input/output bc_7 84 84 ? 64 92 g9 155 pull-up bc_1 156 control bc_2 157 hrw input/output bc_7 85 85 ? 65 93 g8 158 pull-up bc_1 159 control bc_2 160 d1 input/output bc_7 86 86 67 ? 94 g7 161 pull-up bc_1 162 control bc_2 163 d2 input/output bc_7 87 87 68 ? 95 f9 164 pull-up bc_1 165 control bc_2 166 d3 input/output bc_7 88 88 69 ? 96 f10 167 pull-up bc_1 168 control bc_2 169 d4 input/output bc_7 89 89 70 ? 97 f11 170 pull-up bc_1 171 control bc_2 172 d5 input/output bc_7 90 90 71 ? 98 e10 173 pull-up bc_1 174 control bc_2 175 std1 input/output bc_7 ? ? ? 66 99 e8 176 pull-up bc_1 177 control bc_2 178 srd1 input/output bc_7 ? ? ? 67 100 e11 179 pull-up bc_1 180 control bc_2 table 17-5. bsr contents for 5685x (continued) bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) jtag boundary scan register (bsr) jtag port, rev. 4 freescale semiconductor 17-17 181 sck1 input/output bc_7 ? ? ? 68 101 e9 182 pull-up bc_1 183 control bc_2 184 sc10 input/output bc_7 ? ? ? 69 102 d10 185 pull-up bc_1 186 control bc_2 187 sc11 input/output bc_7 ? ? ? 70 103 d11 188 pull-up bc_1 189 control bc_2 190 sc12 input/output bc_7 ? ? ? 71 104 c11 191 pull-up bc_1 192 control bc_2 193 rxd1 input/output bc_7 94 94 74 74 107 b11 194 pull-up bc_1 195 control bc_2 196 txd1 input/output bc_7 95 95 75 75 108 c10 197 pull-up bc_1 198 control bc_2 199 tio3 input/output bc_7 97 97 ? 77 110 b10 200 pull-up bc_1 201 control bc_2 202 tio2 input/output bc_7 98 98 ? 78 111 d9 203 pull-up bc_1 204 control bc_2 205 tio1 input/output bc_7 99 99 ? 79 112 c9 206 pull-up bc_1 207 control bc_2 208 tio0 input/output bc_7 101 101 77 81 114 b9 209 pull-up bc_1 210 control bc_2 211 hds input/output bc_7 103 103 ? 83 116 c8 212 pull-up bc_1 213 control bc_2 214 hcs input/output bc_7 104 104 ? 84 117 d8 215 pull-up bc_1 216 control bc_2 table 17-5. bsr contents for 5685x (continued) bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) jtag boundary scan register (bsr) 5685x digital signal controller user manual, rev. 4 17-18 freescale semiconductor 217 hreq input/output bc_7 105 105 ? 85 118 b8 218 pull-up bc_1 219 control bc_2 220 hack input/output bc_7 106 106 ? 86 119 c7 221 pull-up bc_1 222 control bc_2 223 d6 input/output bc_7 107 107 79 ? 120 d7 224 pull-up bc_1 225 control bc_2 226 d7 input/output bc_7 108 108 80 ? 121 b7 227 pull-up bc_1 228 control bc_2 229 d8 input/output bc_7 109 109 81 ? 122 e7 230 pull-up bc_1 231 control bc_2 232 d9 input/output bc_7 110 110 82 ? 123 f8 233 pull-up bc_1 234 control bc_2 235 d10 input/output bc_7 111 111 83 ? 124 f7 236 pull-up bc_1 237 control bc_2 238 std0 input/output bc_7 116 116 88 92 131 b6 239 pull-up bc_1 240 control bc_2 241 srd0 input/output bc_7 117 117 89 93 132 c6 242 pull-up bc_1 243 control bc_2 244 sck0 input/output bc_7 118 118 90 94 133 c5 245 pull-up bc_1 246 control bc_2 247 sc00 input/output bc_7 119 119 91 95 134 d6 248 pull-up bc_1 249 control bc_2 250 sc01 input/output bc_7 120 120 92 96 135 b5 251 pull-up bc_1 252 control bc_2 table 17-5. bsr contents for 5685x (continued) bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) tap controller jtag port, rev. 4 freescale semiconductor 17-19 * test mode 17.8 tap controller the tap controller is a synchronous 16-bit finite state machine illustrated in figure 17-7 . it responds to changes at the tms and tck pins. transitions from one state to another will occur on the rising edge of tck. the value shown adjacent to each state transition represents the signal present on tms at the time of a rising edge of tck. the tdo pin will remain in the high impedance state except during the shift-dr and shift-ir tap controller states. in these controller states, tdo will update on the falling edge of tck. tdi is sampled on the rising edge of tck. the tap controller will execute the last instruction decoded until a new instruction is entered at the update-ir state, or test-logic-reset is entered. 253 sc02 input/output bc_7 121 121 93 97 136 e6 254 pull-up bc_1 255 control bc_2 256 d11 input/output bc_7 122 122 94 ? 137 d5 257 pull-up bc_1 258 control bc_2 259 d12 input/output bc_7 123 123 95 ? 138 b4 260 pull-up bc_1 261 control bc_2 262 d13 input/output bc_7 126 126 98 ? 142 c4 263 pull-up bc_1 264 control bc_2 265 d14 input/output bc_7 127 127 99 ? 143 f6 266 pull-up bc_1 267 control bc_2 268 d15 input/output bc_7 128 128 100 ? 144 b3 269 pull-up bc_1 270 control bc_2 table 17-5. bsr contents for 5685x (continued) bit number pin/bit name pin type bsr cell 853 pin number (128 lqfp package) 854 pin number (128 lqfp package) 855 pin number (100 lqfp package) 857 pin number (100 lqfp package) 858 pin number (144 lqfp package) 858 pin number (144 mapbga package) tap controller 5685x digital signal controller user manual, rev. 4 17-20 freescale semiconductor figure 17-7. tap controller state diagram the tap controller will execute the last instruction decoded until a new instruction is entered at the update-ir state, or test-logic-reset is entered. there are two paths through the 16-state machine. the shift-ir-scan path captures and loads jtag instructions into the jtagir. the shift-dr-scan path captures and loads data into the other jtag registers. the tap controller executes the last instruction decoded until a new instruction is entered at the update-ir state, or until the test-logic-reset state is entered. when using the jtag port to access eonce module registers, follow these four steps: 1. enable the tlm by shifting the tlm_sel instruction into the jtagir. 2. when selected, the tlm must enable the 56800e tap by shifting in the appropriate value into the tlm register. 3. when the 56800e tap is selected, the eonce module is selected by shifting the enable_eonce instruction. 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 0 0 00 0 0 0 0 0 0 0 0 0 capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr-scan 7 6 2 1 3 0 5 d 8 b 9 a e 4 test-logic-reset f run-test/idle c tap controller jtag port, rev. 4 freescale semiconductor 17-21 4. the eonce module registers and commands are read and written through the jtag pins using the shift-dr-scan path. asserting the jtag?s trst pin asynchronously forces the jtag state machine into the test-logic-reset state. 17.8.1 operation all state transitions of the tap controller occur based on the value of tms at the time of a rising edge of tck. actions of the instructions occur on the falling edge of tck in each controller state illustrated in figure 17-1 . 17.8.1.1 test logic reset (pstate = f) during test-logic-reset all jtag test logic is disabled so the chip can operate in a normal mode. this is achieved by initializing the instruction register (ir) with the idcode instruction. by holding tms high for five rising edges of tck, the device will always remain in test-logic-reset no matter what state the tap controller was in previously. 17.8.1.2 run-test-idle (pstate = c) run-test-idle is a controller state between scan operations. eonce entered, the controller will remain in the run-test-idle mode as long as tms is held low . when tms is high and a rising edge of tck occurs, the controller moves to the select-dr state. 17.8.1.3 select data register (pstate = 7) the select-dr state is a temporary state. in this state, all test data registers selected by the current instruction retains their previous states. if tms is held low and a rising edge of tck occurs when the controller is in this state, the controller moves into the capture-dr state and a scan sequence for the selected test data register is initiated. if tms is held high and a rising edge of tck occurs, the controller moves to the select-ir state. 17.8.1.4 select instruction register (pstate = 4) the select-ir state is a temporary state. in this state, all test data registers selected by the current instruction retain their previous states. if tms is held low and a rising edge of tck occurs when the controller is in this state, the controller moves into the capture-ir state and a scan sequence for the instruction register is initiated. if tms is held high and a rising edge of tck occurs, the controller moves to the test-logic-reset state. tap controller 5685x digital signal controller user manual, rev. 4 17-22 freescale semiconductor 17.8.1.5 capture data register (pstate = 6) in this controller state, data may be parallel loaded into test registers selected by the current instruction on the rising edge of tck. if a test data register selected by the current instruction does not have a parallel input, the register retains its previous value. 17.8.1.6 shift data register (pstate = 2) in this controller state, the test data register is connected between tdi and tdo. this data is then shifted one stage towards its serial output on each rising edge of tck. the tap controller will remain in this state while tms is held at a low . when a one is applied to tms and a positive edge of tck occurs the controller will move to the exit1-dr state. 17.8.1.7 exit1 data register (pstate = 1) this is a temporary controller state. if tms is held high , and a rising edge is applied to tck while in this state causes the controller to advance to the update-dr state. this terminates the scanning process. 17.8.1.8 pause data register (pstate = 3) this controller state allows shifting of the test data register in the serial path between tdi and tdo to be temporarily halted. all test data registers selected by the current instruction retain their previous state unchanged. the controller remains in this state while tms is held low . when tms goes high and a rising edge is applied to tck, the controller advances to the exit2-dr state. 17.8.1.9 exit2 data register (pstate = 0) this is a temporary controller state. if tms is held high , and a rising edge is applied to tck while it is in this state, the scanning process terminates and the tap controller advances to the update-dr state. if tms is held low and a rising edge of tck occurs, the controller advances to the shift-dr state. 17.8.1.10 update data register (pstate = 5) all boundary scan register contain a two stage data register. it isolates the shifting and capturing of data on the peripheral from what is applied to internal logic during scan mode. this register is the second stage, or parallel output, and it is used to apply a stimulus to internal logic. data is latched on the parallel output of these test data registers from the shift register path on the falling edge of tck in the update-dr state. on a rising edge of tck, the controller advances to the select_dr state if tms is held high or the run-test-idle state if tms is held low . tap controller jtag port, rev. 4 freescale semiconductor 17-23 17.8.1.11 capture instruction register (pstate = e) when the tap controller is in this state and a rising edge of tck occurs, the controller advances to the exit1-ir state if tms is held at a one or the shift-ir state if tms is held at a zero. 17.8.1.12 shift instruction register (pstate = a) in this controller state, the shift register contained in the instruction register (ir) is connected between tdi and tdo and shifts data one stage towards it?s serial output on each rising edge of tck. when the tap controller is in this state and a rising edge of tck occurs, the controller advances to the exit1-ir state if tms is held at a one or remains in the shift-ir state if tms is held at a zero. 17.8.1.13 exit1 instruction register (pstate = 9) this is a temporary controller state. if tms is held high , and a rising edge is applied to tck while in this state causes the controller to advance to the update-ir state. this terminates the scanning process. if tms is held low and a rising edge of tck occurs the controller advances to the pause-ir state. 17.8.1.14 pause instruction register (pstate = b) this controller state allows shifting of the instruction register (ir) in the serial path between tdi and tdo to be temporarily halted. all test data registers selected by the current instruction retain their previous state unchanged. the controller remains in this state while tms is held low . when tms goes high and a rising edge is applied to tck, the controller advances to the exit2-ir state. 17.8.1.15 exit2 instruction register (pstate = 8) this is a temporary controller state. if tms is held high , and a rising edge is applied to tck while in this state, the scanning process terminates and the tap controller advances to the update-ir state. if tms is held low and a rising edge of tck occurs, the controller advances to the shift-ir state. 17.8.1.16 update instruction register (pstate = d) during this state, instruction shifted into the instruction register (ir) is latched from the shift register path on the falling edge of tck and into the instruction latch. it becomes the current instruction. on a rising edge of tck, the controller advances to the select_ir state if tms is held high or the run-test-idle state if tms is held low . 5685x restrictions 5685x digital signal controller user manual, rev. 4 17-24 freescale semiconductor 17.9 5685x restrictions the control afforded by the output enable signals using the bsr and the extest instruction requires a compatible circuit board test environment to avoid any device-destructive configurations. avoid situations when the 5685x output drivers are enabled into actively driven networks. during power-up, the trst pin must be externally asserted to force the tap controller into this state. after power-up is concluded, tms must be sampled as a logic 1 for five consecutive tck rising edges. if tms either remains unconnected or is connected to v dd , then the tap controller cannot leave the test-logic-reset state, regardless of the state of tck. 5685x features a low-power stop mode invoked using the stop instruction. jtag interaction with low-power stop mode is as follows: 1. the tap controller must be in the test-logic-reset state to either enter or remain in stop mode. leaving the tap controller test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. 2. the tck input is not blocked in low-power stop mode. to consume minimal power, the tck input should be tied to ground only. 3. the tms and tdi pins include on-chip pull-up resistors. in low-power stop mode, these two pins should remain either unconnected or connected to v dd to achieve minimal power consumption. because all 5685x clocks are disabled during stop state, the jtag interface provides the means of polling the device status, sampled in the capture-ir state. appendix - a glossary, rev. 4 freescale semiconductor a-1 appendix a glossary 5685x digital signal controller user manual, rev. 4 a-2 freescale semiconductor appendix - a glossary, rev. 4 freescale semiconductor a-3 a.1 glossary this glossary is intended to reduce potential confusion caused by the use of many acronyms and abbreviations throughout this manual. acim a/c induction motors a/d analog-to-digital adc analog to digital converter adcr adc control registe addr address adhlmt adc high limit registers adllmt adc low limit registers adlst adc channel list registers adlstat adc limit status register adm application development module adofs adc offset registers adr pd address bus pull-up disable adrslt adc result registers adsdis adc sample disable register adstat adc status register adzcc adc zero crossing control register adzcstat adc zero crossing status register agu address generation unit alu arithmetic logic unit api application program interface barrel shifter part of the alu that allows single cycle shifting and rotating of data word bcr bus control register bdc brush dc motor be breakpoint enable bfiu boot flash interface unit bflash boot flash bk breakpoint configuration bit bldc brushless dc motor blksz base address and block size register in the emi peripherial 5685x digital signal controller user manual, rev. 4 a-4 freescale semiconductor botneg bottom-side pwm polarity bit bs breakpoint selection bsdl boundary scan description language bsr boundary scan register can controller area network cc condition codes cap capture cdbr core data bus read cdbw core data bus write cen cop enable bit cfg config cgdb core global data bus cgm clock generator module cgmdb clock generator module divide-by register in the occs module cgmtod clock generator module time of day register in the occs module cgmtst clock generator module test register in the occs module chcnf channel configure cid chip identification register ckdivisor clock divisor clko clock output pin clkosel clko select clkosr clock select register cmos complementary metal oxide semiconductor. (a form of digital logic that is characterized by low power consumption, wide power suppply range, and high noise immunity.) cmp compare cnt count cntr counter codec coder/decoder cop computer operating properly cop/rti computer operating properly/real time interface copctl cop control copdis cop timer disable copr cop reset appendix - a glossary, rev. 4 freescale semiconductor a-5 copsrv cop service copto cop time out cp charge pump cpha clock phase cpol clock polarity cpu central processing unit crc cyclic redundancy code cs chip select csen cop stop enable csor chip select option register in the emi peripheral ctrl control ctrl pd control signal pull-up disable cvr command vector regsiter cwen cop wait enable bit cwp cop write protect dac digital to analog converter dat data/address select data alu data address limit data pd data bus i/o pull-up disable dc down counter programmable divide by n counter dda analog power ddr data direction register dec quadrature decoder module dee dumb erase enable dfiu data flash interface unit dflash data flash die watchdog time-out interrupt enable dirq watchdog time-out interrupt request dm data memory dma direct memory access dmadr data memory address dmw data memory write 5685x digital signal controller user manual, rev. 4 a-6 freescale semiconductor dpe dumb programming enable dr data register drv drive control bit dsc digital signal controller dso data shift order dsp digital signal processor edg edge-aligned or center-aligned pwms ee erase enable eeof enable external oflag force em event modifier emi external memory interface en enable3 ena enables (tap tlm) encr encoder control register eosi end of scan interrupt eosie end of scan interrupt enable erase erase cycle errie error interrupt enable ex external x memory extboot external boot extr external reset fault fault input to pwm fe framing error flag flagx faultx pin flag fh fifo halt fiex faultx pin interrupt enable fsm finite state machine fir filter interval register floci force loss of clock floli force loss of lock fmodex faultx pin clearing mode fosc oscillator frequency appendix - a glossary, rev. 4 freescale semiconductor a-7 fpinx faultx pin fref reference frequency ftackx faultx pin acknowledge gpio general purpose input/output gpr group priority register harvard a microprocessor architecture using separate buses for program and data. this is architecture data is typically used on dsps to optimise the data throughput. hack host acknowledge input pin hbo hardware breakpoint occurrence hc host command bit hcie host command interrupt enable bit hcp host command pending bit hcr host interface control register hdds host dual data strobe bit hdma host dma status bit hf0 host flag 0 bit (general-purpose flag) hf1 host flag 1 bit (general-purpose flag) hf2 host flag 2 bit (general-purpose flag) hf3 host flag 3 bit (general-purpose flag) hlend host little endian bit hlmti high limit interrupt bit hlmtie high limit interrupt enable bit hm0 host mode control 0 bit hm1 host mode control 1 bit hold hold register home home switch input hrdf host status receive data full bit hreq host request output bit hrie host receive interrupt enable bit hrms host request mode select bit hrrq host receive request bit hrx host interface data register 5685x digital signal controller user manual, rev. 4 a-8 freescale semiconductor hsr host interface status register htde host transmit data empty bit htie host transmit interrupt enable bit htrq host transmit request bit htx host transmit data register hv host vector bits ia interrupt assert ic integrated circuit icr interface control register ie interrupt enable iee intelligent erase enable ief input edge flag iefie input edge flag interrupt enable ienr interrupt enable register ies interrupt edge sensitive ifren information block enable imr input monitor register indep independent or complimentary pair operation index index input init initialize bit input external input signal inv invert i/o input/output ip interrupt pending ipbus intellectual properties bus ipe intelligent program enable ipol current polarity ipolr interrupt polarity register ipbba interrupt properties bus bridge address ipbb interrupt pending bus bridge ipr interrupt pending register (in gpio) ipr interrupt priority register (in the core) appendix - a glossary, rev. 4 freescale semiconductor a-9 ips input polarity select irq interrupt request is interrupt source isc in select control (tap tlm) isr interface status register ivr interrupt vector regsiter itcn interrupt controller jtag joint test action group jtagbr jtag bypass register jtagir jtag instruction register lc link controls lcd liquid crystal display lck loss of lock ldok load okay lf loop filter lir lower initialization register llmti low limit interrupt llmtie low limit interrupt enable load load register loci loss of clock locie los of clock interrupt enable loli pll lock of lock interrupt loop loop select bit lpos lower position counter register lposh lower position hold register lsb least significant bit lsh_id most significant half of jtag_id lvd low voltage detect lvie low voltage interrupt enable lvis low voltage interrupt source m mode ma mode a 5685x digital signal controller user manual, rev. 4 a-10 freescale semiconductor mac multiply and accumulate mas mass cycle erase mb mode b mcu microcontroller unit - mhz megahertz mips million instructions per second miso master in/slave out modf mode fault error modfen mode fault enable mosi master out/slave in mpio multi-purpose input/output (a, b, c, d, e or f) msb most significant bit mscan motorola scalable controller area network msh_id most significant half of jtag id mstr master mode mux multiplexer nf noise flag nl nested looping nor an inversion of the logical or function nvstr non-volatile store cycle definition obar once breakpoint address register obctl once breakpoint control register obmsk once breakpont mask register ocmdr once command register occs on-chip clock synthesis ocntr once count register ocr once control register odec once decoder oen output enable omac once memory address comparator omal once memory address latch omr operating mode register appendix - a glossary, rev. 4 freescale semiconductor a-11 once on-chip emulation (unit) opabdr once program address bus decode register opaber once program address bus execute register opabfr once program address bus fetch register opdbr once program data bus register opfifo once pab change of flow opgdbr once program global data bus register ops output polarity select or overrun oshr once shift register osr once status register ovrf overflow pab program address bus pd permanent stop/wait disable pdb program data bus pe program enable pe parity enable bit per peripheral enable register pf parity error flag pfd phase frequency detector pfiu program flash interface unit pflash program flash pgdb peripheral global data bus pll phase locked loop module pllcid pll clock in divide pllcod pll clock out divide plldb pll divide-by pllcr pll control register pllpdn pll power down pllsr pll status register plr priority level register pmccr pwm channel control register 5685x digital signal controller user manual, rev. 4 a-12 freescale semiconductor pmcfg pwm configuration register pmcnt pwm counter register pmctl pwm control register pmdeadtm pwm deadtime register pmdismap pwm disable mapping registers pmfctl pwm fault control register pmfsa pwm fault status acknowledge pmout pwm output control register pmport pwm port register pol polarity por power on reset pram program ram prog program cycle psr processor status register pt parity type ptm peripheral test mode pur pull-up enable register pwd power down mode pwm pulse width modulator pwmen pwm enable pwmf pwm reload flag pwmrie pwm reload interrupt enable pwmval pwm value registers qe quadrature encoder qdn quadrature decoder negative signal raf receiver active flag ram random access memory rdrf receive data register full re receiver enable reie receive error interrupt enable rev revolution counter register revh revolution hold register appendix - a glossary, rev. 4 freescale semiconductor a-13 rdmaen receive dma enable bit ridle receiver idle line rie receiver full interrupt enable rom read only memory rpd re-programmable stop/wait disable rreq receive request bit rsrc receiver source bit rwu receiver wake up rxdf receive data register full bit rxh receive byte high register rxl receive byte low register sa saturation sample a word or time-slot of data to be transferred in a frame sbk send break sbo software breakpoint occurrence sbr sci baud rate sci serial communications interface3 scibr sci baud rate register scicr sci control register scidr sci data register scisr sci status register sclk serial clock scr status and control sd stop delay sdk software development kit sel selects (tap tlm) sext sign extend sim system integration module smode scan mode spdrr spi data receive register spdsr spi data size register spdtr spi data transmit register 5685x digital signal controller user manual, rev. 4 a-14 freescale semiconductor sp spi enable spi serial peripheral interface spmstr spi master sprf spi receiver full sprie spi receiver interrupt enable spscr spi status control register spte spi transmitter empty sptie spi transmit interrupt enable sr status register srm switched reluctance motor ss slave select ssi synchronous serial interface swai stop in wait mode sys_cntl system control register sys_sts system status register tap test access port tcsr text control and status register tce test counter enable tcf timer compare flag tcfie timer compare flag interrupt enable tck tap clock tdi tap data in tdo tap data out tdmaen transmit dma enable bit tdre transmit date register empty te transmitter enable teie transmitter empty interrupt enable ten test mode enable terasel terase limit testr test register tfdbk test feedback clock tfref test reference frequency clock appendix - a glossary, rev. 4 freescale semiconductor a-15 tidle transmitter idle tiie transmitter idle interrupt enable time-slot a frame divided into time-slots, allowing for the transfer of a word of data tirq test interrupt request register tisr test interrupt source register tm test mode bit tmel time limit tmode test mode bit tmr quadrature timer tmr pd timer i/o pull-up disable tnvhl tnvh limit tnvsl tnvs limit to trace occurrence tod time of day module tof timer overflow flag tofie timer oerflow flag interrupt enable topneg top-side pwm polarity bit tprogl tprog limit tpgsl tpgs limit trcvl trcv limit trdy transmit ready flag bit treq transmit reuest enable bit tstreg test register txde transmit data register empty bit uir upper initialization register upos upper position hold register uposh upper position hold register vab vector address bus vba vector base address are pins on the 56800e core vco voltage controlled oscillator v dd voltage digital drain (power) v dda analog power 5685x digital signal controller user manual, rev. 4 a-16 freescale semiconductor vel velocity counter register velh velocity hold register vlmode value register load mode vref voltage reference vrm variable reluctance motor v ss ground v ssa analog ground wake wake up condition wde watchdog enable wp write protect wspm wait state p memory wsx wait state data memory wtr watchdog timeout register www world wide web xdb2 x data bus xe x address enable xie index pulse interrupt enable xirq index pulse interrupt request xne use negative edge of index pulse xram data ram ye y address enable zci zero crossing interrupt zcie zero crossing interrupt enable zcs zero crossing status zsrc zclock source appendix - b programmer?s sheets, rev. 4 freescale semiconductor b-1 appendix b programmer?s sheets 5685x digital signal controller user manual, rev. 4 b-2 freescale semiconductor appendix - b programmer?s sheets, rev. 4 freescale semiconductor b-3 b.1 introduction the following pages provide a set of reference tables and programming sheets intended to simplify programming the 5685x. the programming sheets provide room to add the value of each bit and the hexadecimal value for each register. these pages may be photocopied. for complete instruction set details, please refer to chapter 4 of the dsp56800e reference manual (dsp56800erm). b.2 programmers? sheets each described instruction contains notations used to abbreviate certain operands and operations described in tab le b-1 . programmers? sheets are arranged to correspond with the chapters in this document. the same table lists programmers? sheets by module, the registers in each module, and the appendix pages where the programmers? sheets are located. note: reserved bits ( ) should always be set to 0 unless otherwise stated. ? table b-1. list of programmer?s sheets register type register page system integration module (sim) sys_base = $1fff08 sim control register (scr) b-8 sim control data registers 1-2 (scd1-2) b-9 external memory interface (emi) emi_base = $1ffe40 base address and block size register (csbar) b-10 chip select option register (csor) b-11 bus control register (bcr) b-13 on-chip clock synthesis (occs) cgm_base = $1ffff10 cgm control register (cgmcr) b-14 , b-15 cgm divide-by register (cgmdb) b-16 cgm time of day register (cgmtod) b-17 computer operating properly (cop) cop_base = $1fffd0 cop control register (copctl) b-18 cop timeout register (copto) b-19 cop counter register (copctr) b-20 5685x digital signal controller user manual, rev. 4 b-4 freescale semiconductor interrupt control (itcn) itcn_base = $1fff20 interrupt priority register 0 (ipr0) b-21 interrupt priority register 1 (ipr1) b-22 interrupt priority register 2 (ipr2) b-23 interrupt priority register 3 (ipr3) b-25 interrupt priority register 4 (ipr4) b-27 interrupt priority register 5 (ipr5) b-29 , b-30 interrupt priority register 6 (ipr6) b-31 , b-32 interrupt priority register 7 (ipr7) b-33 , b-34 vector base address register (vba) b-37 fast interrupt match register 0 (fim0) b-38 fast interrupt match register 1 (fim1) b-39 fast interrupt vector address low 0 and high 0 (fival0 and fivah0) b-40 fast interrupt vector address low 1 and high 1 (fival1 and fivah1) b-41 interrupt request pending register 0-3 (irqp0-3) b-42 interrupt control register (ictl) b-43 , b-44 direct memory access (dma) dma0_base = $1ffec0 dma1_base = $1ffec8 dma2_base = $1ffed0 dma3_base = $1ffed8 dma4_base = $1ffee0 dma5_base = $1ffee8 source address high register (dmasah) b-45 source address low register (dmasal) b-46 destination address high register (dmadah) b-47 destination address low register (dmadal) b-48 transfer count register (dmacnt) b-49 circular queue size register (dmacqs) b-50 transfer control register (dmatc) b-51 , b-52 serial communication interface (sci0-1) sci0_base = $1fffe0 sci1_base = $1ffdf8 baud register (scibr) b-53 control register (scicr) b-54 , b-55 , b-56 control register 2 (scicr2) b-57 status register (scisr) b-58 , b-59 , b-60 data register (scidr) b-61 table b-1. list of programmer?s sheets (continued) register type register page appendix - b programmer?s sheets, rev. 4 freescale semiconductor b-5 serial peripheral interface (spi) spi_base = $1fffe8 status and control register (spscr) b-62 , b-63 , b-64 data size and control register (spdscr) b-65 data receive register (spdrr) b-66 data transmit register (spdtr) b-66 enhanced synchronous serial interface (essi) essi0_base = $1ffe20 essi1_base = $1ffe00 transmit data register 0-2 (stx0-2) b-68 receive data register (srx) b-69 status register (ssr) b-70 , b-71 control register 2 (scr2) b-72 , b-73 control register 3 (scr3) b-74 , b-75 control register 4 (scsr4) b-76 , b-77 transmit and receive control registers (stxcr, srxcr) b-78 time slot register (stsr) b-79 fifo control/status register (sfcsr) b-80 , b-81 transmit slot mask registers (tsma, tsmb) b-82 receive slot mask registers (rsma, rsmb0 b-83 quad timer (tmr) tmr_base = $1ffe80 control register (ctl) b-90 , b-91 , b-92 status/control register (scr) b-93 , b-94 compare register 1 (cmp1) b-84 compare register 2 (cmp2) b-85 capture register (cap) b-86 load register (load) b-87 hold register (hold) b-88 counter register (cntr) b-89 time of day (tod) tod_base = $1fffc0 tod control/status register (todcs) b-95 clock scaler (todscl) b-96 seconds register (todsec) b-97 seconds alarm register (todsal) b-98 minutes register (todmin) b-99 minutes alarm register (todmal) b-100 hours register (todhr) b-101 table b-1. list of programmer?s sheets (continued) register type register page 5685x digital signal controller user manual, rev. 4 b-6 freescale semiconductor hours alarm register (todhal) b-102 days register todday) b-103 days alarm register (toddal) b-104 general purpose in/out (gpio) gpio a_base = $1ffe60 gpio b_base = $1ffe64 gpio c_base = $1ffe68 gpio d_base = $1ffe6c gpio e_base = $1ffe70 gpio f_base = $1ffe74 gpio g_base = $1ffe78 gpio h_base = $1ffe7c port a peripheral enable register (mpa_per) b-105 port b peripheral enable register (mpb_per) b-106 port c peripheral enable register (mpc_per) b-107 port d peripheral enable register (mpd_per) b-108 port e peripheral enable register (mpe_per) b-109 port f peripheral enable register (mpf_per) b-110 port g peripheral enable register (mpg_per) b-111 port h peripheral enable register (mph_per) b-112 port a data direction register (mpa_ddr) b-113 port b data direction register (mpb_ddr) b-114 port c data direction register (mpc_ddr) b-115 port d data direction register (mpd_ddr) b-116 port e data direction register (mpe_ddr) b-117 port f data direction register (mpf_ddr) b-118 port g data direction register (mpg_ddr) b-119 port h data direction register (mph_ddr) b-120 port a data register (mpa_dr) b-121 port b data register (mpb_dr) b-122 port c data register (mpc_dr) b-123 port d data register (mpd_dr) b-124 port e data register (mpe_dr) b-125 port f data register (mpf_dr) b-126 port g data register (mpg_dr) b-127 port h data register (mph_dr) b-128 port a pull-up enable register (mpa_pur) b-129 port b pull-up enable register (mpb_pur) b-130 port c pull-up enable register (mpc_pur) b-131 port d pull-up enable register (mpd_pur) b-132 port e pull-up enable register (mpe_pur) b-133 port f pull-up enable register (mpf_pur) b-134 table b-1. list of programmer?s sheets (continued) register type register page appendix - b programmer?s sheets, rev. 4 freescale semiconductor b-7 port g pull-up enable register (mpg_pur) b-135 port h pull-up enable register (mph_pur) b-136 host interface 8 hi8_base = $1fffd8 host control register (hcr) b-137 host status register (hsr) b-138 transmit data register (htx) b-139 receive data receive (hrx) b-140 interface control register (icr) b-141 command vector register (cvr) b-142 interface status register (isr) b-143 interrupt vector register (ivr) b-144 receive byte registers (rxh, rxl) b-145 transmit byte registers (txh, txl) b-146 table b-1. list of programmer?s sheets (continued) register type register page application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-8 freescale semiconductor 1 of 21 of 2 bits name description 14 - 12 boot mode this bit field is set to the value on the input pins, modc, modb, and moda when the last active reset source (accept cop reset) deasserts. its value determines boot mode executed upon reset. boot mode 0 bootstrap from byte-wide external memory boot mode 1 bootstrap from spi boot mode 2 normal expanded mode boot mode 3 development expanded mode boot mode 4 bootstrap from host port-single strobe clocking boot mode 5 bookstrap from host port-dual strobe clocking boot mode 6 bootstrap from sci boot mode 7 reserved 6 eonce ebl enhanced once enable 0 once clock to core is enabled only when the core tap is enabled 1 once clock to core is always enabled 5 clkout dbl clock out disable 0 clkout output presents clkmstr/8 (this is half the peripheral bus clock frequency) 1 clkout output pin presents static 0 4 pram dbl program ram disable 0 internal program ram enabled 1 internal program ram disabled and acce sses redirected to external memory 3 dram dbl data ram disable 0 internal data ram enabled 1 internal data ram disabled and accesses redirected to external memory 2 sw rst software reset to reset part, write a 1 to this bit 1 stop dbl stop disable 0 the stop mode will be entered when the core executes a stop instruction 1 the core stop instruction will not cause entry into the stop mode 0 wait dbl wait disable 0 the wait mode will be entered when the core executes a wait instruction 1 the core wait instruction will not cause entry into the wait mode sim control register (scr) $1fff08 +$0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 boot mode chip rev 0 eonce ebl clkout dbl pram dbl dram dbl sw rst stop dbl wait dbl write reset 000000010 0 0 0 0 0 0 0 sim system integration module control register (scr) denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-9 2 of 2 sim control data register 1 (scd1) $1fff08 + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read software control data 1 write por 0000000000000000 reset xxxxxxxxxxxxxxxx bits name description 15 - 0 scd1 software control data one this register is reset only by the por and is in tended for use by software developers to place data to be unaffected by other reset sources. 15 - 0 scd2 software control data two this register is reset only by the por and is in tended for use by software developers to place data to be unaffected by other reset sources. sim system integration module control data registers 1-2 (scd1-2) sim control data register 2 (scd2) $1fff08 +$2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read software control data 2 write por 0000000000000000 reset xxxxxxxxxxxxxxxx application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-10 freescale semiconductor 1 of 4 emi chip select register base address and block size (csbar ) cs register base address/block size (csbar0-csbar3) $1ffe40 + $0-$3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 blksz write reset 000000000000 0011 bits name description 15 addr23 determines the memory map start address where the chip select is active. 14 addr22 13 addr21 12 addr20 11 addr19 10 addr18 9 addr17 8 addr16 7 addr15 6 addr14 5 addr13 4 addr12 3 - 0 blksz determines which bits in the base address field are compared to corresponding bits on the address bus during an access. application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-11 2 of 4 emi chip select option register (csor0-3) chip select option register (csor0-csor3) $1ffe40 + $8-$b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rws byte_en r/w ps/ds wws write reset 101110000001 0111 bits name description 9 - 8 byte_en upper/lower byte enable (ubs and lbs ) accesses to external data memory are typically through the use of a word. for data memory access, the 56800 core can also access bytes, yielding the upper and lower half of a word. csor encoding of cs ubs functionality csor encoding of cs lbs functionality 00 disabled 00 disabled 01 lower byte enabled 01 lower byte enabled 10 upper byte enabled 10 upper byte enabled 11 both bytes enabled 11 both bytes are enabled 7 - 6 r/w read/write 00 the chip select will be disabled 01 the chip select will be enabled for both read/write 10 the chip select will allow read only 11 the chip select will allow read/write 5 - 4 ps/ds program/data space select 00 the chip select will be disabled 01 the chip select will allow data space only 10 the chip select will allow program space only 11 the chip select will be enabled 3 - 0 wws write wait state specifies minimum number of ipbus_clk wait states required by an emi access. application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-12 freescale semiconductor 3 of 4 emi chip select timing control registers (cstc0?3) chip select timing control register (cstc0-csor3) $1ffe40 + $10-$13 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read wwss wwsh rwss rwsh 0 0 0 0 0 mdar write reset 000000000000 0011 bits name description 15 - 14 wwss write wait states setup delay this field affects the write cycle timing diagram, illustrated in figure 5-16 . additional time (clock cycles) is provided between the assertion of cs n and address lines and the assertion of wr . the value of wwss should be set as indicated in section 5.7.2 . 13 - 12 wwsh write wait states hold delay this field affects the write cycle timing diagram, illustrated in figure 5-17 . the wwsh field specifies the number of additional system clocks to hold the address, data, and cs n signals after the wr signal is deasserted. the value of wwsh should be set as indicated in section 5.7.2 . 11 - 10 rwss read wait states setup delay this field affects the read cycle timing diagram, illustrated in figure 5-10 . additional time (clock cycles) is provided between the assertion of cs n and address lines and the assertion of rd . the value of rwss should be set as indicated in section 5.7.1 . 9 - 8 rwsh read wait states hold delay this field affects the read cycle timing diagram, illustrated in figure 5-11 . the rwsh field specifies the number of additional system clocks to hold the address, data, and cs n signals after the rd signal is deasserted. the value of rwsh should be set as indicated in section 5.7.1 . 2 - 0 mdar minimal delay after read this field specifies the number of system clocks to delay between reading from memory in a cs n controlled space and reading from another device. since a write to the device implies activating the device on the bus, this is also considered a read from another device. figure 5-6 illustrates the timing issue requiring the introduction of the mdar field. in this diagram, cs1 is assumed to operate a slow flash memory in p-space while cs2 is operating a faster ram in x-space. in some bus contention cases, it is possible to encounter data integrity problems where the contention is occurring at the time the data bus is sampled. denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-13 4 of 4 emi bus control register (bcr) bus control register (bcr) $1ffe40 +$18 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read drv bmdar 0 0 bwws brws write reset 0000001011110111 bits name description 15 drv drive this control bit is used to specify what occurs on the external memory port pins when no external access is performed. for example, it determines whether pins are placed in tri-state or remain driven. 14 - 12 bmdar base minimal delay after read this bit field specifies the number of system cloc ks to delay after reading from memory not in cs controlled space. since a write to the device implie s activating the device on the bus, this is also considered a read from another devic e, therefore activating the bmdar timing control. please see the description of the mdar field of the cstc regi sters for a discussion of the function of this control. 9-5 bwws base write wait states this bit field specifies the number of additional syst em clocks 0-30 (31 is invalid) to delay for write access to the selected memory when the memory address does not fall within cs controlled range. the value of bwws should be set as indicated in section 5.7 . 4-0 brws base read wait states this bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for read access to the selected memory when the memory address does not fall within cs controlled range. the value of brws should be set as indicated in section 5.7 . denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-14 freescale semiconductor 1 of 4 bits name description 13 lck1 lock 1 status this bit shows the status of the lock detector state for the lck1 circuit. 0 pll not locked 1 pll locked 12 lck0 lock 0 status this bit shows the status of the lock detector state for the lck0 circuit. 0 pll not locked 1 pll locked 11 sel clock source select this bit is used to control the source of the master clock to the sim. 0 oscillator output selected (default) 1 pll output selected 6 - 5 lck1_ie lock 1 interrupt enable this is an optional interrupt bit. 00 disable interrupt (default) 01 enable interrupt on rising edge of lck1 10 enable interrupt on falling edge of lck1 11 enable interrupt on any edge of lck1 occs cgm control register (cgmcr) cgm control register (cgmcr) $1fff10 + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 lck1 lck0 sel 0 0 0 0 lck1_ie lck0_ie lckon tod_sel pdn write reset 00 0 0 0 000000 0 0 0 0 1 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-15 bits name description 4 - 3 lck0_ie lock 0 interrupt enable this is an optional interrupt bit. 00 disable interrupt (default) 01 enable interrupt on rising edge of lck0 10 enable interrupt on falling edge of lck0 11 enable interrupt on any edge of lck0 2 lckon lock detector on this is an optional interrupt bit. 0 lock detector disabled (default) 1 lock detector enabled 1 tod_sel time of day select this bit is used to select between the two possible tod_sel sources. 0 tod_clk is generated by the oscillator (default) 1 tod_clk is generated by the cgm 0 pdn the pll power-down this bit can be turned off by setting the power-down bit to 1. 0 pll turned on 1 pll powered down (default) 2 of 4 occs cgm control register (cgmcr) continued cgm control register (cgmcr) $1fff10 + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 lck1 lck0 sel 0 0 0 0 lck1_ie lck0_ie lckon tod_sel pdn write reset 00 0 0 0 000000 0 0 0 0 1 denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-16 freescale semiconductor 3 of 4 occs cgm divide-by register (cgmdb) $1fff10 + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read post 0 0 0 0 0 0 plldb write reset 0000000000111011 cgm divide-by register (cgmcr) bits name description 15 - 13 post pll post scaler the output of the pll is postscaled by 1-128 based on this field. to change this field, set the sel bit to choose the oscillator output, then this fiel d is changed. the sel bit is then returned to selecting the pll postscaled output. 000 pll output is divided by 1 (default) 001 pll output is divided by 2 010 pll output is divided by 4 011 pll output is divided by 8 100 pll output is divided by 16 101 pll output is divided by 32 110 pll output is divided by 64 111 pll output is divided by 128 6 - 0 plldb pll divide-by the pll output frequency is controlled by the pll divide-by value. each time a new value is written into the plldb field, the lock detector circuit is reset. before changing the divide-by, set the sel bit to choose the oscillator output. denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-17 4 of 4 occs cgm time-of-day register (cgmtod) cgm time of day register (cgmtod) $1ffff10 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 tod write reset 0000000000000000 bits name description 11 - 0 tod time-of-day the output of the oscillator is divided by (tod + 1) and then divided by 2 to generate the tod clock used by the cop module when tod_sel is high. the value of tod should be chosen to result in a tod clock frequency in the range of 15.12khz to 31.25khz. this register is only reset during power-on reset (por). denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-18 freescale semiconductor denotes reserved bits 1 of 3 cop cop control register (copctl) bits name description 4 byps bypass (for factory use only) when this bit is set, it allows factory testing of the cop is accelerated by routing the ipbus clock to the counter instead of the oscclk. this bit should not be set during normal chip operation. 3 csen cop stop enable this bit controls the operation of the copcounter stop mode. it can be changed only when the cwp bit is set to zero. 2 cwen cop wait enable this bit controls the operation of the cop counter in the wait mode. it can be changed only when the cwp bit is set to zero. 1 cen cop enable this bit controls the operation of the cop count er. this bit can only be changed when cwp is set to zero. this bit always reads as zero when the chip is in the debug mode. 0 cwp cop write protect this bit controls the write prot ection feature of the cop control (copctl) and the cop timeout (copto) registers. once set, this bit can only be cleared by resetting the module. cop control register (copctl) $1fffd0 + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 byps csen cwen cen cwp write reset 00000000000 00000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-19 cop timeout register (copto) $1fffd0 + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read timeout write reset 11111111111 11111 2 of 3 cop cop time-out register (copto) bits name description 15 - 0 timeout cop time-out period this register determines the time-out period of the cop counter. timeout should be written before the cop is enabled. once the cop is enabled, the recommended procedure for changing timeout is to disable the cop, write to copto, then re-enable the cop, ensuring the new timeout is loaded into the counter. alternatively, the cpu can write to copto, then write the proper patterns to copctr, caus ing the counter to reload with the new timeout value. the cop counter is not reset by a write to copto. changing timeout while the cop is enabled will result in a time-out period differing from the expect ed value. these bits can only be changed when the cwp bit is set to zero. application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-20 freescale semiconductor cop counter register (copctr) $1fffd0 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read count write service reset 1111111111111111 3 of 3 cop cop counter register (copctr) bits name description 15 - 0 copctr cop counter(count) this is the current value of the cop counter as it counts down from the timeout value to zero. a reset is issued when this count reaches zero. 15 - 0 copctr cop counter (service) when enabled, the cop requires a service sequence be performed periodically in order to clear the cop counter and prevent a reset from being issued. this routine consists of writing $5555 to the copctr followed by writing $aaaa before the timeout period expires. the writes to copctr must be performed in the correct order, but any number of other instructions, and writes to other registers, may be executed between the two writes. application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-21 1 of 24 itcn interrupt priority register 0 (ipr0) interrupt priority register 0 (ipr0) $1fff20 + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 bkpt_u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 write reset 00 0 0 000000000000 bits name description 13 - 12 bkpt_u0 ipl breakpoint unit 0 eonce interrupt priority level this bit field is used to set the interrupt priority levels for this eonce irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 11 - 10 stpcent ipl eonce step counter interrupt priority level this bit field is used to set the interrupt priority levels for this eonce irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-22 freescale semiconductor 2 of 24 itcn interrupt priority register 1 (ipr1) interrupt priority register 1 (ipr1) $1fff20 + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl write reset 00 0 0 000000000000 bits name description 5 - 4 rx_reg ipl receive data empty register interrupt priority level this bit field is used to set the interrupt priority levels for this once irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 3 - 2 tx_reg ipl transmit data full interrupt priority level this bit field is used to set the interrupt priority levels for this once irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 1 - 0 trbuf ipl trace buffer interrupt priority level this bit field is used to set the interrupt priority levels for this once irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-23 3 of 24 itcn interrupt priority register 2 (ipr2) interrupt priority register 2 (ipr2) $1fff20 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma2 ipl dma1 ipl dma0 ipl 0 0 lock ipl 0 0 irqb ipl irqa ipl write reset 00 0 0 000000000000 bits name description 15 - 14 dma2 ipl done interrupt priority level 2 these bit fields are used to set the interrupt priority levels for certain eonce irqs. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 13 -12 dma1 ipl done interrupt priority level 1 these bit fields are used to set the interrupt priority levels for certain eonce irqs. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 11 -10 dma0 ipl done interrupt priority level 0 these bit fields are used to set the interrupt priority levels for certain eonce irqs. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-24 freescale semiconductor 4 of 24 itcn interrupt priority register 2 (ipr2) continued interrupt priority register 2 (ipr2) $1fff20 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma2 ipl dma1 ipl dma0 ipl 0 0 lock ipl 0 0 irqb ipl irqa ipl write reset 00 0 0 000000000000 bits name description 7 - 6 lock ipl loss of lock interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 3 - 2 irqb ipl external irqb interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 1 - 0 irqa ipl external irqa interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 1 10 irq is priority level 2 11 irq is priority level 3 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-25 5 of 24 itcn interrupt priority register 3 (ipr3) bits name description 15 - 14 essi0_td ipl essi0 transmit data interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 13 - 12 essi0_tdes ipl essi0 transmit data with exception status interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 11 - 10 essio_rls ipl essio receive last slot interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 9 - 8 essi0_rd ipl essi0 receive data interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 3 (ipr3) $1fff20 + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read essi0_td ipl essi0_tdes ipl essio_rls ipl essi0_rls ipl essi_rdes ipl dma5 ipl dma4 ipl dma3 ipl write reset 000 0000000000000 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-26 freescale semiconductor 6 of 24 itcn interrupt priority register 3 (ipr3) continued bits name description 7 - 6 essi0_rdes ipl essi0 receive data with exception status interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 5 - 4 dma5 ipl done interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 3 - 2 dma4 ipl done interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 1 - 0 dma3 ipl done interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 3 (ipr3) $1fff20 + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read essi0_td ipl essi0_tdes ipl essio_rls ipl essi0_rls ipl essi_rdes ipl dma5 ipl dma4 ipl dma3 ipl write reset 000 0000000000000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-27 7 of 24 itcn interrupt priority register 4 (ipr4) bits name description 15 - 14 spi_rcv ipl spi receiver full interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 13 -12 essi1_tls ipl essi1 transmit last slot interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 11 - 10 essi1_td ipl essi1 transmit data interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 9 - 8 essi1_tdes ipl essi1receive data with exception status interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 4 (ipr4) $1fff20 + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spi_rcv ipl essi1_tls ipl essi1_td ipl essi1_td es ipl essi1_rls ipl essi1_rd ipl essi1_rd es ipl essi0_tls ipl write reset 0000000000000000 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-28 freescale semiconductor 8 of 24 itcn interrupt priority register 4 (ipr4) continued bits name description 7 - 6 essi1_rls ipl spi receive last slot interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 5 -4 essi1_rd ipl essi1 receive data interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 3 - 2 essi1_rdes ipl essi1 receive data with exception status interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 1 - 0 essi0_tls ipl essi0 transmit last slot interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 4 (ipr4) $1fff20 + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spi_rcv ipl essi1_tls ipl essi1_td ipl essi1_td es ipl essi1_rls ipl essi1_rd ipl essi1_rd es ipl essi0_tls ipl write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-29 9 of 24 itcn interrupt priority register 5 (ipr5) bits name description 15 - 14 host_xmit ipl sci receive full interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 13 - 12 host_rcv ipl sci receive error interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 11 - 10 sci0_rcv ipl sci receive idle interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 9 - 8 sci0_rerr ipl sci0 transmitter idle interrupt priority level this bit field is used to set the interrupt priority levels for certain peripheral irqs. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 5 (ipr5) $1fff20 + $5 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read host_xmit ipl host_rcv ipl sci0_rcv ipl sci0_rerr ipl sc0_ridl ipl sci0_tdl ipl sci0_xmit ipl spi_xmit ipl write reset 0000000000000000 see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-30 freescale semiconductor 10 of 24 itcn interrupt priority register 5 (ipr5) continued interrupt priority register 5 (ipr5) $1fff20 + $5 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read host_xmit ipl host_rcv ipl sci0_rcv ipl sci0_rerr ipl sc0_ridl ipl sci0_tidl ipl sci0_xmit ipl spi_xmit ipl write reset 0000000000000000 bits name description 7 - 6 sci0_ridl ipl sci0 receiver idle interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 5 - 4 sci0_tidl ipl sci transmitter idle interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 3 - 2 sci0_xmit ipl spi transmitter empty interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 1 - 0 spi_xmit ipl spi transmitter empty interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-31 11 of 24 itcn interrupt priority register 6 (ipr6) interrupt priority register 6 (ipr6) $1fff20 +$6 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tovf1 ipl tcmp1 ipl tinp0 ipl tovf0 ipl tcmp0 ipl tod ipl tod_alrm ipl tod_cmd ipl write reset 0000000000000000 bits name description 15 - 14 tovf1 ipl timer overflow 1 interrupt priority level these two bits are used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 13 -12 tcmp1 ipl timer compare 1 interrupt priority level these two bits are used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 11 - 10 tinp0 ipl timer input edge 0 interrupt priority level these two bits are used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 9 - 8 tovf0 ipl timer overflow 0 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-32 freescale semiconductor 12 of 24 itcn interrupt priority register 6 (ipr6) continued bits name description 7 -6 tcmp0 ipl timer compare 0 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 5 - 4 tod ipl timer compare 0 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 3 - 2 tod_alrm ipl time of day alarm interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 1 - 0 host_cmd ipl host i/f command interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 6 (ipr6) $1fff20 + $6 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tovf1 ipl tcmp1 ipl tinp0 ipl tovf0 ipl tcmp0 ipl tod ipl tod_alrm ipl host_cmd ipl write reset 0000000000000000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-33 13 of 24 itcn interrupt priority register 7 (ipr7) bits name description 13 - 12 tinp3 ipl timer input edge 3 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 11 - 10 tovf3 ipl timer overflow 3 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 9 - 8 tcmp3 ipl timer compare 3 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 7 - 6 tinp2 ipl timer input edge 2 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 7 (ipr7) $1fff20 + $7 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 tinp3 ipl tovf3 ipl tcmp3 ipl tinp2 ipl tovf2 ipl tcmp2 ipl tinp1 ipl write reset 0000000000000000 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-34 freescale semiconductor 14 of 24 itcn interrupt priority register 7 (ipr7) continued bits name description 5 - 4 tovf2 ipl timer overflow 2 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 3 - 2 tcmp2 ipl timer compare 2 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 1 - 0 tinp1 ipl timer input edge 1 interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 7 (ipr7) $1fff20 + $7 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 tinp3 ipl tovf3 ipl tcmp3 ipl tinp2 ipl tovf2 ipl tcmp2 ipl tinp1 ipl write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-35 15 of 24 itcn interrupt priority register 8 (ipr8) bits name description 9 - 8 sci1_rcv ipl sci1 receiver full interrupt priority level this bit field is used to set the interrupt priority le vels for this peripheral irq. these irqs are limited to priorities 0-2 and are disabled by default. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 7 - 6 sci1_rerr ipl sci1 receiver error interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq.these irqs are limited to priorities 0-2 and are disabled by default. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 5 - 4 sci1_ridl ipl sci1 receiver idle interrupt priority level this bit field is used to set the interrupt priority le vels for this peripheral irq. these irqs are limited to priorities 0-2 and are disabled by default. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 8 (ipr8) $1fff20 + $8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 sci1_rcv ipl sci1_rerr ipl sci1_ridl ipl sci1_tidl ipl sci1_xmit ipl write reset 0000000000000000 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-36 freescale semiconductor bits name description 3 - 2 sci1_tidl ipl sci1 receiver idle interrupt level this bit field is used to set the interrupt priority le vels for this peripheral irq. these irqs are limited to priorities 0-2 and are disabled by default. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 1 - 0 sci1_tidl ipl sci1 transmitter idle interrupt priority level this bit field is used to set the interrupt priority levels for this peripheral irq.these irqs are limited to priorities 0-2 and are disabled by default. 00 irq disabled by default 01 irq is priority level 0 10 irq is priority level 1 11 irq is priority level 2 interrupt priority register 8 (ipr8) $1fff20 + $8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 sci1_rcv ipl sci1_rerr ipl sci1_ridl ipl sci1_tidl ipl sci1_xmit ipl write reset 0000000000000000 denotes reserved bits 16 of 24 itcn interrupt priority register 8 (ipr8) continued application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-37 17 of 24 itcn vector base address register (vba) bits name description 12 - 0 vba vector base address the value in this register is used as the upper 13 bits of the interrupt vector vab[20:0]. the lower eight bits are determined based on the highest priority interrupt, which are appended onto vba before presenting the full vab to the core. vector base address register (vba) $1fff20 + $9 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 vector base address write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-38 freescale semiconductor 18 of 24 itcn fast interrupt match register 0 (fim0) bits name description 6 - 0 fim0 fast interrupt match 0 this value is used to declare which two irqs will be fast interrupts. fast interrupt vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level two. unexpected results will occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest priority level two interrupts regar dless of their actual location in the interrupt table prior to being declared fast interrupts. fast interrupt 0 has priority over fast interrupt 1. fast interrupt match register 0 (fim0) $1fff20 + $a bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 0 write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-39 19 of 24 itcn fast interrupt match register 1 (fim1) bits name description 6 - 0 fim1 fast interrupt match 1 this value is used to declare which two ipqs will be fast interrupts. fast interrupt vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first. irqs used as fast interrupts must be set to priority level two. unexpected results will occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest priority level two interrupts regar dless of their actual location in the interrupt table prior to being declared fast interrupts. fast interrupt 0 has priority over fast interrupt 1. fast interrupt match register 1 (fim1) $1fff20 + $d bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 1 write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-40 freescale semiconductor 20 of 24 itcn fast interrupt vector 0 address low and high 0 (fival0, fivah0) bits name description 15 - 0 fival0 fast interrupt vector address low 0 this register is combined with the fivah0 regist er to forma 21-bit vector address for the fast interrupt defined in the fival0 and fivah0 registers. lower 16 bits of vector address for fast interrupt 0. fast interrupt vector address low 0 (fival0) $1fff20 + $b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 0 vector address low write reset 0000000000000000 bits name description 4 - 0 fivah0 fast interrupt vector address high 0 this register is combined with the fival0 register to form a 21-bit vector address for the fast interrupt defined in the fival0 and fivah0 registers. upper 5 bits of vector address for fast interrupt 0. fast interrupt vector address high 0 (fivah0) $1fff20 + $c bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-41 21 of 24 itcn fast interrupt 1 vector address low and high 1 (fival1, fivah1) bits name description 15 - 0 fival1 fast interrupt 1 vector address low this register is combined with the fivah1 register to form a21-bit vector address for the fast interrupt defined in the fival1 and fivah1 registers. lower 16 bits of vector address for fast interrupt 1. fast interrupt 1 vector address low (fival1) $1fff20 + $e bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 1 vector address low write reset 0000000000000000 bits name description 4 - 0 fivah1 fast interrupt 1 vector address high this register is combined with the fival1 register to form a 21-bit vector address for the fast interrupt defined in the fival1 and fivah1 registers. upper 5 bits of vector address for fast interrupt 1. fast interrupt 1 vector address high (fivah1) $1fff20 + $f bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-42 freescale semiconductor 22 of 24 itcn irq pending registers 0 - 3 (irqp0 - irqp3) bits name description 64 - 1 irqp0 - 3 irq pending registers these registers combine to show the st atus of interrupt requests 2 through 64. 0 irq pending for this vector number 1 no irq pending for this vector number irq pending register 0 (irqp0) $1fff20 + $10 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [16:1] 1 write reset 1111111111111111 denotes reserved bits irq pending register 1 (irqp1) $1fff20 + $11 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [32:17] write reset 1111111111111111 irq pending register 2 (irqp2) $1fff20 + $12 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [48:33] write reset 1111111111111111 irq pending register 3 (irqp3) $1fff20 + $13 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [64:49] write reset 1111111111111111 irq pending register 4 (irqp4) $1fff20 + $14 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 pending [69:65] write reset 1111111111111111 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-43 23 of 24 itcn interrupt control register (ictl) bits name description 15 int interrupt 0 no interrupt is being presented to the core 1 an interrupt is being presented to the core 14 - 13 iplc interrupt priority level core this bit field reflects the state of the new interrupt priority level bits being presented to the core at the time the last irq was taken. 00 required nested exception priority levels are 0, 1, 2, or 3 01 required nested exception priori ty levels are 1, 2, or 3 10 required nested exception priority levels are 2 or 3 11 required nested exception priority level is 3 12 - 6 vab vector number this field shows bits [7:1] of the vector number of the last irq. the field is only updated when the core jumps to a new interrupt service routine. 5 int_dis interrupt disable disables all interrupts 0 normal operation (default) 1 all interrupts disabled irq control register (ictl) $1fff20 + $1a bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int iplc vab int_dis 0 irqb_state irqa_state irqb_edg irqa_ edg write reset 0 0 0 0000000 0 0 1 1 0 0 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-44 freescale semiconductor bits name description 3 irqb_state state of irqb this bit reflects the state of the external irqb 2 irqa_state state of irqa this bit reflects the state of the external irqa 1 irqb_edg irqb edge this bit controls whether the external irqb interrupt is edge or level sensitive. automatically level sensitive during stop and wait modes. 0 irqb interrupt is level sensitive (default) 1 irqb interrupt is falling edge sensitive 0 irqa_edg irqa edge this bit controls whether the external irqa interrupt is edge or level sensitive. automatically level sensitive during stop and wait modes. 0irqa interrupt is low level sensitive (default) 1irqa interrupt is falling edge sensitive 24 of 24 itcn interrupt control register (ictl) continued irq control register (ictl) $1fff20 + $1a bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int iplc vab int_dis 0 irqb_state irqa_state irqb_edg irqa_ edg write reset 0000000000 0 0 1 1 0 0 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-45 1 of 8 dma source address high register (dmasah) denotes reserved bits dma source address high register (dmasah) base + $6 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 dma source address (high) write 0 0 0 0 0 0 0 0 reset 0000000000000000 bits name description 7 - 0 dmasah dma source address (high) this is the upper byte of the dma source addr ess. dma data is read from this address. if post-incrementing (or decrementing) is enabled, this value is updated with each read transaction. application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-46 freescale semiconductor 2 of 8 dma source address low register (dmasal) dma source address low register (dmasal) base + $5 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma source address (low) write reset 0000000000000000 bits name description 15 - 0 dmasal dma source address (low) this is the lower word of the dma source addr ess. dma data is read from this address. if post-incrementing (or decrementing) is enabled, this value is updated with each read transaction. application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-47 3 of 8 dma destination address high register (dmadah) dma destination address high register (dmadah) base + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 dma destination address (high) write reset 0000000000000000 bits name description 7 - 0 dmadah dma destination address (high) this is the upper byte of the dma destination addr ess. dma data is written from this address. if post-incrementing (or decrementing) is enabl ed, this value is updated with each write transaction. denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-48 freescale semiconductor dma destination address low register (dmadal) base + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma destination address (low) write reset 0000000000000000 bits name description 15 - 0 dmadal dma destination address (low) this is the lower byte of the dma destination addr ess. dma data is written from this address. if post-incrementing (or decrementing) is enabl ed, this value is updated with each write transaction. 4 of 8 dma destination address low register (dmadal) application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-49 5 of 8 dma dma transfer count register (dmacnt) dma transfer count register (dmacnt) base + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma transfer count write reset 0000000000000000 bits name description 15 - 0 dmacnt dma transfer count this is the count of the number of items (byt es or words) to transfer in the dma data block. application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-50 freescale semiconductor 6 of 8 dma dma circular queue size register (dmacqs) dma circular queue size register (dmacqs) base + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma circular queue size write reset 0000000000000000 bits name description 15 - 0 dmacqs dma circular queue size this is the size of the circular queue. the register defaults to zero. when zero, the circular queue operation is disabled. as a non-zero, the queue mode is operational. application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-51 7 of 8 dma dma transfer control register (dmatc) bits name description 15 dmaon direct memory access on this bit enables/disables the dma operation. 0 dma operation is disabled 1 dma operation is enabled 14 intron interrupt on this bit enables/disables the dma interrupt operation 0 dma interrupt operation is disabled 1 dma interrupt operation is enabled 13 intrpend interrupt pending this is the dma interrupt pending bit 0 dma interrupt is not pending 1 dma interrupt is pending 12 datasize data size this bit defines the data size of the dma transfers 0 dma transfers are performed in bytes (8 bits) 1 dma transfers are performed in words (16 bits) dma transfer control register (dmatc) base + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma_on intr_on intr_pend data_size 0 0 0 periph sel ss/m ds/m write 0 0 0 reset 0 0 0 0 0 0 0 000000 0 0 0 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-52 freescale semiconductor 8 of 8 dma dma transfer control register (dmatc) continued bits name description 8 - 4 periph sel peripheral select this bit field selects on of 31 possible dma peripherals. when the field is equal to 0, operation begins upon enabling dma operation. when a peripheral-to-peripheral dma transfer is desired, this field should be set to the slower of the two peripherals thereby preventing data overruns. 3 - 2 ss/m source sign/magnitude this bit field determines how the dma source address register gets changed after each dma read operation. 0x do not change the address register 10 increment the address register by data size amount after each read 11 decrement the address register by data size amount after each read 1 - 0 ds/m destination sign/magnitude this bit field determines how the dma destination address register gets changed after each dma write operation. 0x do not change the address register 10 increment the address register by data size amount after each read 11 decrement the address register by data size amount after each read denotes reserved bits dma transfer control register (dmatc) base + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dma_on intr_on intr_pend data_size 0 0 0 periph sel ss/m ds/m write 0 0 0 reset 0 0 0 0 0 0 0 000000 0 0 0 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-53 1 of 9 sci sci baud register (scibr) sci baud register (scibr) base + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 sbr write reset 0000000000000000 bits name description 12 - 0 sbr sci baud register this register may be read at any time. bits 12 through 0 can be written at any time. (sbr = contents of the baud rate registers, a value from 1 to 8191.) denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-54 freescale semiconductor 2 of 9 sci sci control register (scicr) sci control register (scicr) base + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read loop swai rsrc m wake pol pe pt teie tiie rfie reie te re rwu sbk write reset 0000000000000000 bits name description 15 loop loop select this bit enables loop operation. loop operation disconnects the rxd pin from the sci and the transmitter output goes into the receiver input. both transmitter and receiver must be enabled to use the internal loop function as opposed to si ngle wire operation, requiring only one or the other to be enabled. 0 normal operation enabled 1 loop operation enabled 14 swai stop in wait mode this bit disables the sci in the wait mode. 0 sci enabled in wait mode 1 sci disabled in wait mode 13 rsrc receiver source when loop = 1, the rsrc bit determines the internal feedback path for the receiver. 0 receiver input internally connected to transmitter output 1 receiver input connected to txd pin 12 m data format mode the mode bit determines whether data characters are eight or nine bits long. 0 one start bit, eight data bits, one stop bit 1 one start bit, nine data bits, one stop bit 11 wake wake up condition this bit determines which condition wakes up the sci. 0 idle line wake up 1 address mark wake up 10 pol polarity this bit determines whether to invert the data as it goes from the transmitter to the txd pin and from the rxd pin to the receiver. all bits (start , data, and stop) will be inverted as they leave the transmit shift register and before they enter the receive shift register. 0 doesn?t invert transmit and receive data bits (normal mode) 1 invert transmit and receive data bits (inverted mode) see the following page for continuation of this register application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-55 3 of 9 sci sci control register (scicr) continued bits name description 9 pe parity enable this bit enables the parity function. when enabled, t he function replaces the most significant bit of the data character with a parity bit. 0 parity function disabled 1 parity function enabled 8 pt parity type this bit determines if the sci generates and c hecks for even or odd parity of the data bits. 0 even parity 1 odd parity 7 teie transmitter empty interrupt enable this bit enables transmit data register empt y (tdre) flag to generate interrupt requests. 0 tdre interrupt requests disabled 1 tdre interrupt requests enabled 6 tiie transmitter idle interrupt enable this bit enables the transmitter idle (t idle) flag to generate interrupt requests. 0 tidle interrupt requests disabled 1 tidle interrupt requests enabled 5 rfie receiver full interrupt enable this bit enables the receive data register full ( rdrf) flag, or the overrun (or) flag to generate interrupt requests. 0 rdrf and or interrupt requests disabled 1 rdrf and or interrupt requests enabled sci control register (scicr) base + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read loop swai rsrc m wake pol pe pt teie tiie rfie reie te re rwu sbk write reset 0000000000000000 see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-56 freescale semiconductor bits name description 4 reie receiver error interrupt enable this bit enables receive error (re) flags (nf, pf, fe, an or) to create interrupt requests. 0 error interrupt requests disabled 1 error interrupt requests enabled 3 te transmitter enable this bit enables the sci transmitter, configuring the txd pin as the sci transmitter output. 0 transmitter disabled 1 transmitter enabled 2 re receiver enable this bit enables the sci receiver. 0 receiver disabled 1 receiver enabled 1 rwu receiver wake up this bit enables the wake up function and inhibits further receiver interrupt requests. 0 standby state 1 normal operation 0 sbk send break toggling sbk sends one break character (10 or 11 logic 0s). as long as sbk is set, the transmitter sends logic 0s. 0 no break characters 1 transmit break characters 4 of 9 sci sci control register (scicr) continued sci control register (scicr) base + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read loop swai rsrc m wake pol pe pt teie tiie rfie reie te re rwu sbk write reset 0000000000000000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-57 5 of 9 sci sci control register 2 (scisr2) sci control register 2 (scicr2) base + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 riie tde rde write reset 0000000000000000 bits name description 2 riie receiver idle interrupt enable this bit is used to inform the processor a me ssage has completed when using dma in a wake-up mode of operation. the receiver is norma lly configured until a message is detected. 1 tde transmitter dma enable setting this bit allows transmi t dma requests to the dma controller. fro transmit dma operation, this bit must be set and a dma channel must be enabled to utilize the request. 0 transmit dma disabled 1 transmit dma enabled 0 rde receiver dma enable setting this bit allows received dma requests to the dma controller. for receive dma operation, this bit must be set and a dma channel must be enabled to utilize the request. 0 receive dma disabled 1 receive dma enabled denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-58 freescale semiconductor 6 of 9 sci sci status register (scisr) sci status register (scisr) base + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tdre tidle rdrf ridle or nf fe pf 0 0 0 0 0 0 0 raf write reset 0000000000000000 bits name description 15 tdre transmit data register empty this bit is set when the transmit shift register re ceives a character from the sci data register (scidr). clear tdre by reading scisr with tdre set and then writing to sci data register in normal mode or by writing the scidr with tde set. 0 no character transferred to transmit shift register 1 character transferred to transmit shift register; transmit data register empty 14 tidle transmitter llde this bit is set when the tdre flag is set and not data, preamble, or break character is being transmitted. when tidle is set, the txd pin becom es idle (logic 1). clear tidle by reading the sci status register (scisr) with tidle set and then writing to the sci data register (scidr). tidle is not generated when a data character, a preamble, or a break is queued and ready to be sent. 0 transmission in progress 1 no transmission in progress 13 rdrf receive data register full this bit is set when the data in the receive shift register transfers to the sci data register (scidr) clear rdrf by reading the sci status register (scisr) with rdrf set and then reading the sci data register in normal mode or by reading the scidr with rde set. 0 data not available in sci data register 1 received data available in sci data register denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-59 7 of 9 sci sci status register (scisr) continued sci status register (scisr) base + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tdre tidle rdrf ridle or nf fe pf 0 0 0 0 0 0 0 raf write reset 0000000000000000 denotes reserved bits bits name description 12 ridle receiver idle line this bit is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. once the ridle flag is cleared (the receiver detects a logic 0), a valid frame must again set the rdrf flag before an idle condition can set the ridle flag. 0 receiver input is either active now or has never become active since the ridle flag was last cleared 1 receiver input has become idle (after receiving a valid frame) 11 or overrun this bit is set when software fails to read the sc i data register (scidr) before the receive shift register receives the next frame. the data in the shift register is lost, but the data already in the sci data register is not affected. clear or by reading the sci status register (scisr) with or set and then writing the sci status register with any value. 0 no overrun 1overrun 10 nf noise flag this bit is set when the sci detects noise on the re ceiver input. the nf bit is set during the same cycle as the rdrf flag but does not get set in the case of an overrun. clear nf by reading the sci status register (scisr) and then writing the sci status register with any value. 0 no noise 1noise see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-60 freescale semiconductor sci status register (scisr) base + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tdre tidle rdrf ridle or nf fe pf 0 0 0 0 0 0 0 raf write reset 0000000000000000 bits name description 9 fe framing error this bit is set when a logic 0 is accepted as the stop bit. the fe bit is set during the same cycle as the rdrf flag but does not get set in the case of an overrun. fe inhibits further data reception until it is cleared. clear fe by reading the sci status register (scisr) with fe set and then writing the sci status register with any value. 0 no framing error 1 framing error 8 pf parity error flag this bit is set when the parity enable pe bit is set and the parity of the received data does not match its parity bit. clear pf by reading the sci status register (scisr) and then writing the sci status register with any value. 0 no parity error 1 parity error 0 raf receiver active flag this bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. raf is cleared when the receiver detects fals e start bits (usually from noise or baud rate mismatch) or when the receiver detects a preamble. 0 no reception in progress 1 reception in progress denotes reserved bits 8 of 9 sci sci status register (scisr) continued application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-61 9 of 9 sci sci data register (scidr) sci data register (scidr) base + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 receive data write 0 0 0 0 0 0 0 transmit data reset 0000000000000000 bits name description 8 - 0 receive data data received 8 - 0 transmit data data to be transmitted denotes reserved bits application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-62 freescale semiconductor 1 of 6 spi spi status and control register (spscr) spi status and control register (spscr) $1fffe8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spr dso errie modfen sprie spmstr cpol cpha spe sptie sprf ovrf modf spte write reset 0110 0 0 0 1 01000000 bits name description 15 - 13 spr spi baud rate these are read/write bits while in master mode, selects one of four baud rates. 12 dso data shift order this read/write bit determines whether the msb or lsb bit is transmitted or received first. 0 msb transmitted first (msb->lsb) 1 lsb transmitted first (lsb->msb) 11 errie error interrupt enable this read/write bit enables the modf and ovrf bits to generate interrupt requests. reset clears the errie bit. errie bit enables both the modf and ovrf bits to generate a receiver/error interrupt request. 0 modf and ovrf cannot generate interrupt requests 1 modf and ovrf can generate interrupt requests 10 modfen mode fault enable this read/write bit when set to one allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. 9 sprie spi receiver interrupt enable this read/write bit enables interrupt requests generated by the sprf bit. the sprf bit is set when a full data length transfers from the shif t register to the receive data register. 0 sprf interrupt requests disabled 1 sprf interrupt requests enabled 8 spmstr spi master this read/write bit selects master mode operation or slave mode operation. 0 slave mode 1 master mode denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-63 2 of 6 spi spi status and control register (spscr) continued spi status and control register (spscr) $1fffe8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spr dso errie modfen sprie spmstr cpol cpha spe sptie sprf ovrf modf spte write reset 0110 0 0 0 1 01000000 bits name description 7 cpol clock parity this read/write bit determines the logic state of the sclk pin between transmissions. to transmit data between spi modules, the sppi modules musts have identical cpol values. 0 falling edge of sclk starts transmission 1 rising edge of the sclk starts transmission 6 cpha clock phase this read/write bit controls the timing relationship between the serial clock and spi data. to transmit data between spi modules, there must be identical cpha values. when cpha = 0, the ss pin of the slave spi module musts be set to logic 1 between full length data transmissions. 5 spe spi enable this read/write bit enables the spi module. clear ing spe causes a partial reset of the spi. when setting/clearing this bit, no other bits in the spscr should be changed. failure to following this statement may result in spurious clocks. 0 spi module disabled 1 spi module enabled 4 sptie spi transmit interrupt enable this read/write bit enables interrupt requests generated by the spte bit. spte is set when a full data length transfers from the transmit data register to the shift register. 0 spte interrupt requests disabled 1 spte interrupt request enabled 3 sprf spi receiver full this read-only flag enables interrupt requests generated by the spte bit. 0 receive data register not full 1 receive data register full denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-64 freescale semiconductor 3 of 6 spi spi status and control register (spscr) continued bits name description 2 ovrf overflow this read-only flag is set if software does not read the data in the receive data register before the next full data enters the shift register. 0 no overflow 1 overflow 1modf mode fault this read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. 0 ss pin at appropriate logic level 1 ss pin at inappropriate logic level 0 spte spi transmitter empty this read-only flag is set each time the transmit data register transfers a full data length into the shift register. 0 transmit data register not empty 1 transmit data register empty spi status and control register (spscr) $1fffe8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spr dso errie modfen sprie spmstr cpol cpha spe sptie sprf ovrf modf spte write reset 0110 0 0 0 1 01000001 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-65 4 of 6 spi denotes reserved bits bits name description 15 wom wired or mode 0 wired or mode disabled 1 wired or mode enabled 14 tdmaen transmitter dma enable 0 transmitter dma mode disabled 1 transmitter dma mode enabled 13 rdmaen receiver dma enable 0 receiver dma mode disabled 1 receiver dma mode enabled 3 - 0 tds transmission data size detailed transmission data provided in the following table: ds3 - ds0 size of transmission ds3 - ds0 size of transmission $0 not allowed $8 9 bits $1 2 bits $9 10 bits $2 3 bits $a 11 bits $3 4 bits $b 12 bits $4 5 bits $c 13 bits $5 6 bits $d 14 bits $6 7 bits $e 15 bits $7 8 bits $f 16 bits spi data size and control register (spdscr) spi data size and control register (spdscr) $1fffe9 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read wom tdmaen rdmaen 0 0 0 0 0 0 0 0 0 tds write reset 0 0 0 0000000001111 application : date : programmer : sheet c 5685x digital signal controller user manual, rev. 4 b-66 freescale semiconductor 5 of 6 denotes reserved bits denotes reserved bits spi spi data receive register (spdrr) spi data receive register (spdrr) $1fffea bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 write reset 0000000000000000 bits name description 15 - 0 r receive this is a read-only data register. reading data from the regist er will show the last full data received after a complete transmission. the sprf bit will set when new data transfers to this register. application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-67 6 of 6 denotes reserved bits denotes reserved bits spi spi data transmit register (spdtr) $1fffeb bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 write t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 reset 0000000000000000 spi data transmit register (spdtr) bits name description 15 - 0 t transmit this is a write-only data register. writing data to the register modifies data to the transmit data buffer. when the spte bit is set, new data should be written to this register. if new data is not written while in the master mode, a new transaction wi ll not be initiated until this register is written. when in the slave mode, the old data will be re-transmitted. all data should be written with the lsb at bit 0. application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-68 preliminary essi transmit data register 0 - 2 (stx0-2) essi bits name description 15 -0 data write data stx0-2 are 16-bit write-only data registers. essi transmit data register (stx0) base + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write data reset 0000000000000000 denotes reserved bits 1 of 16 essi transmit data register (stx1) base + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write data reset 0000000000000000 essi transmit data register (stx2) base + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write data reset 0000000000000000 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-69 freescale semiconductor preliminary 2 of 16 essi receive data register (srx) bits name description 15 - 8 high byte srx is a read-only register. the register always ac cepts data from the receiver shift register as it becomes full. 7 - 0 low byte essi receive data register (srx) base + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read high byte low byte write reset 0000000000000000 denotes reserved bits essi application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-70 preliminary essi status register (ssr) bits name description 15 if1 input flag 1 this bit is enabled only when sc1 is configured as an input flag and synchronous mode is selected. if not enabled, the if1 bit is cleared. 14 if0 input flag 0 this bit is enabled only when sc0 is configured as an input flag and the synchronous mode is selected. if it is not enabled, the if0 bit is cleared. 12 tff transmit fifo full this status bit allows monitoring when the ttf is full. 0 transmit fifo can accept more data 1 transmit fifo is full 11 tls transmit last slot this status bit indicates timing of the last transmit slot during the network mode operation 0 not currently transmitting the last time slot of the transmit frame 1 last slot of the transmit fram e is currently being transmitted 10 rls receive last slot this status bit indicates the timing of the last receive slot during the network mode operation 0 not currently receiving the last time slot of the receive frame 1 last slot of the receive frame is currently being received 9 tf1err transmit fifo 1 error when the transmitter status control txsf1 is set and the fifos are in use, this status bit will indicate the state of fifo1 is not the same as fifo0. 0 state of txfifo0 and txfifo1 contains the same amount of data 1 state of txfifo is different than the state of the txfifo1 8 tf2err transmit fifo 2 error when the transmitter status control txsf2 is set and fifos are in use, this status bit indicates the state of fifo2 is not the same as fifo0. 0 status of txfifo2 matches the other enabled txfifos 1 status (data content level) of txfifo2 is different than the other enabled txfifos essi status register (ssr) base + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read if1 if0 tff tls rls tf1err tf2err rdr tde roe tue tfs rfs rff tfe write reset 000000 0 0 00000000 essi 3 of 16 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-71 freescale semiconductor preliminary essi status register (ssr) continued bits name description 7 rdr receive data ready flag this flag bit is set when receive data regist er or the receive fifo is loaded with a new value. the rdr is cleared when the cpu reads the srx register. when rxfifo is enabled, rdr is cleared when receive fifo is empty. 6 tde transmit data register empty this flag bit is set when there is no data waiti ng to be transferred to the txsr register. a transmit fifo is enabled when there is at least one empty slot in stx or txfifo. when the txfifo is not enabled, the stx is empty. 5 roe receive overrun error this flag bit is set when the receive shift register (rxsr) is enabled, filled, ready to transfer to the srx or the rxfifo registers, and when these registers are already full. 4 tue transmitter underrun error this flag bit is set when the txsr is empty, or when there is no data to be transmitted, as indicated by the tde bit being set, and a transmit time slot occurs. when a transmit underrun error occurs, the previously sent data is retransmitted. 3 tfs transmit frame sync when set, this flag bit indicates a frame sync occurred during transmission of the last word written to the stx register. 2 rfs receive frame sync when set, this flag bit indicates a frame sync occurred during receiving of the next word into the srx register. 1 rff receive fifo full when set, this bit indicates data can be read using the srx register. the data level in the rxfifo must reach the your selected receive fifo watermark (rfwm) threshold. 0 tfe transmit fifo empty when set, the tfe bit indicates data can be written to the txfifo register. the tfe bit is cleared by writing data to the stx register unt il the txfifo data content level reaches the watermark level. essi status register (ssr) base + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read if1 if0 tff tls rls tf1err tf2err rdr tde roe tue tfs rfs rff tfe write reset 000000 0 0 00000000 essi 4 of 16 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-72 preliminary essi control register 2 (scr2) 5 of 16 bits name description 15 rie receive interrupt enable this control bit allows interr upting the program controller 0 receive fifo is disabled: no interrupt is generated 1 receive fifo is disabled: interrupt is generated if the rdr flag in the ssr is set 0 receive fifo is enabled: no interrupt is generated 1 receive fifo is enabled: interrupt is generated if the rff flag in the ssr is set 14 tie transmit interrupt enable this control bit provides program controller interruption 0 transmit fifo is disabled: no interrupt is generated 1 transmit fifo is disabled: interrupt is generated if the tde flag in the ssr is set 0 transmit fifo is enabled: no interrupt is generated 1 transmit fifo is enabled: interrupt is gener ated if the tfe flag in the ssr is set 13 re receive enable this control bit enables the receive portion of the essi 0 receiver is disabled by inhibiting data transfer into the srx 1 receiver portion of the essi is enabled and received data will be processed beginning with the next frame sync 12 te0 transmit enable 0 this control bit enables the transfer of the c ontents of the stx0 register to its txsr0 0 the transmitter continues to send data in txsro, then transmitter is disabled 1 on the next frame boundary, the transmit 0 portion of the essi is enabled 11 te1 transmit enable 1 this control bit enables the transfer of the c ontents of the stx1 register to its txsr1 0 transmitter continues to send data current ly in txsr1, then disables transmitter 1 on the next frame boundary, the transmit 1 portion of the essi is enabled 10 te2 transmit enable 2 this control bit enables the transfer of the c ontents of the stx2 register to its txsr2 0 transmitter continues to send data current ly in txsr2, then disables transmitter 1 on the next frame boundary, the transmit 2 portion of the essi is enabled essi control register 2 (scr2) base + $5 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rie tie re te0 te1 te2 syn tshfd tsckp essien net tfsi tfsl tefs write reset 000000 0 0 0 0 0 0 0 0 0 0 essi denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-73 freescale semiconductor preliminary essi control register 2 (scr2) continued bits name description 7 syn synchronous mode this control bit enables the synchronous mode of operation 6 tshfd transmit shift direction this bit controls whether the msb or lsb is transmitted first for the transmit section 0 msb is transmitted first 1 lsb is transmitted first 5 tsckp transmit clock parity this control bit determines which bit clock edge is used to clock out data in the transmit 0 data is clocked out on the rising edge of the bit clock 1 falling edge of the bit clock is used to clock the data out 4 essien essi enable this control bit enables and disables the essi 0 the essi is disabled 1 the essi is enabled 3 net network mode this control bit selects the operational mode of the essi 0 normal mode is selected 1 network mode is selected 2 tfsi transmit frame sync invert this control bit selects the logic of frame sync i/o 0 frame sync is active high 1 frame sync is active low 1 tfsl transmit frame sync length this control bit selects the length of the frame sync signal to be generated or recognized 0 a one-word long frame sync is selected 1 a one-bit long frame sync is selected 0 tefs transmit early frame sync this bit controls when the frame sync is initiated for the transmit and receive sections 0 frame sync is initiated as the first bit of data is transmitted 1 frame sync is initiated one bit before the data is transmitter essi 6 of 16 essi control register 2 (scr2) base + $5 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rie tie re te0 te1 te2 syn tshfd tsckp essien net tfsi tfsl tefs write reset 000000 0 0 0 0 0 0 0 0 0 0 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-74 preliminary 7 of 16 essi control register 3 (scr3) denotes reserved bits essi control register 3 (scr3) base + $6 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read div4dis rshfd rsckp rdmae tdmae rfsi rfsl refs rfen tfen init syn rst rlie tlie write reset 0 0 0 0 0 0 0 0 0 0 000000 bits name description 15 div4dis divider 4 disable 0 fix_clk is equal to the ip_clk/4 for both transmitter and receiver clock generator circuits 1 fix_clk is equal to the ip_clk 14 rshfd receive shift direction this control bit determines if msb or lsb is received first for the receive section 0 data received msb first 1 data received lsb first 13 rsckp receive clock polarity this control bit determines if bit clock edge is used to capture data for the receive section 0 captured data during clock falling edge 1 capture data input during rising edge of the clock 12 rdmae receive dma enable this bit allows the essi to request a dma module transfer of received data 0 if receive fifo is disabled: no dma transfer is requested 1 if receive fifo is disabled: dma request is generated when the essi rdr bit is set 0 if receive fifo is enabled: no dma transfer is requested 1 if receive fifo is enabled: dma request is generated when the essi frr bit in ssr is set 11 tdmae transmit dma enable this bit allows the essi to request a dma transfer for the next data to transmit 0 if transmit fifo is disabled: no dma transfer is requested 1 if transmit fifo is disabled: dma request is generated when the essi tde bit in tde is set 0 if transmit fifo is enabled: no dma transfer is requested 1 if transmit fifo is enabled: dma request is generated when the essi tfe bit in ssr is set 10 rfsi receive frame sync invert this bit selects the logic of frame sync i/o for the receive section 0 frame sync is active high 1 frame sync is active low see the following page for continuation of this register essi application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-75 freescale semiconductor preliminary bits name description 2 synrst frame sync reset 0 data must be read to be cleared from the registers 1 resets the accumulation of data in the srx register and rxfifo bit in frame sync 1 rlie receive last slot interrupt enable 0 the receive last slot interrupt is disabled 1 an interrupt is generated after the last slot of a receive frame ends when the essi is in the network mode. interrupt occurs regardless of the receive mask register setting. 0 tlie transmit last slot interrupt enable 0 the transmit last slot interrupt is disabled 1 an interrupt is generated at the beginning of the last slot of the transmit frame when the essi is in the network mode. the interrupt occurs regardless of the transmit mask register setting. 8 of 16 essi control register 3 (scr3) continued essi denotes reserved bits essi control register 3 (scr3) base + $6 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read div4dis rshfd rsckp rdmae tdmae rfsi rfsl refs rfen tfen init syn rst rlie tlie write reset 0 0 0 0 0 0 0 0 0 0 000000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-76 preliminary 9 of 16 essi control register 4 (scr4) denotes reserved bits bits name description 10 txsfo transmit status flag control 0 0 the indicated transmitter does not affect the status bits 1 the indicated transmitter status will affect the tff, tde, tue, and tfe status bits 9 txsf1 transmit status flag control 1 0 the indicated transmitter does not affect the status bits 1 the indicated transmitter status will affect the tff, tde, tue, and tfe status bits 8 txsf2 transmit status flag control 2 0 the indicated transmitter does not affect the status bits 1 the indicated transmitter status will affect the tff, tde, tue, and tfe status bits 6 ssc1 select sc1 this bit controls the functionality of the sc1 signal and is used only if syn = 1 and te2 = 0 0 the sc1 acts as the serial i/o flag (if1/of1) 1 when configured as an output (scd1 = 1), the sc1 signal acts as the transmitter 0 driver-enable, enabling an external buffer for the transmitter 0 output 5 sckd clock source direction this bit configures the source of the clock signal used to clock the transmit shift register in asynchronous mode and both transmit and receive shift registers are in synchronous mode 0 sck pin is configured as an input. th is pin is used as the clock source 1 internal transmit clock generator is selected. this clock is output on the sck pin 4 scd2 serial control direction 2 this bit controls the direction of the sc2 pin 0 sc2 is an input 1 sc2 is an output essi control register 4 (scr4) base + $7 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read txsfo txsf1 txsf2 ssc1 sckd scd2 scd1 scd0 of1 of0 write reset 00000 0 0 0 0 0 0 0 0 0 0 0 essi see the following page for continuation of this register application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-77 freescale semiconductor preliminary 10 of 16 essi control register 4 (scr4) continued denotes reserved bits bits name description 3 scd1 serial control direction 1 this bit controls the direction of the sc1 pin depending on the stat of the other controls 0 sc1 is an input 1 sc1 is an output 2 scd0 serial control direction 0 this bit controls the direction of the sc0 pin depending on the state of other controls 0 sc0 is an input 1 sc0 is an output 1 of1 serial output flag 1 when sc1 is configured for output flag functionality the control bit determines the state of the output pin. changes in the of1 bit will appear on the sc1 pin at the beginning of the next frame in the normal mode, or at the beginning of the next time slot in the network mode. 0 of0 serial output flag 0 when sc0 is configured for output flag functionality, the control bit determines the state of the output pin. changes in the of0 bit will appear on the sc0 pin at the beginning of the next frame in the normal mode, or at the beginning of the next time slot in the network mode. essi control register 4 (scr4) base + $7 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read txsfo txsf1 txsf2 ssc1 sckd scd2 scd1 scd0 of1 of0 write reset 000000 0000000000 essi application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-78 preliminary 11 of 16 essi transmit and receive control registers (stxcr, srxcr) bits name description 15 psr prescaler range this bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. it extends the range of the prescaler for those cases where a slower bit clock is desired. 0 when the psr bit is cleared, the fixed prescaler is by-passed 1 when the psr bit is set, the fixed di vide-by eight prescaler is operational 14 - 13 wl word length control these bits are used to select the length of the data words being transferred by the essi 12 - 8 dc frame rate divider control this bit field controls the divide rati o for the programmable frame rate dividers 7 - 0 pm prescaler modulus select this bit field specifies the divide ratio of the prescale divider in the essi clock generator. this prescaler is used only in internal clock m ode to divide the internal peripheral clock. essi essi transmit control register (stxcr) base + $8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read psr wl dc pm write reset 0000000000000000 essi receive control register (srxcr) base + $9 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read psr wl dc pm write reset 0000000000000000 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-79 freescale semiconductor preliminary 12 of 16 essi time slot register (stsr) essi time slot register (stsr) base + $a bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write dummy register, written during inactive time slots (network mode) reset xxxxxxxxxxxxxxxx denotes reserved bits essi bits name description 15 - 0 stsr issi time slot register used when data is not to be transmitted in an available transmit time slot. the time slot register is a write-only register behaving like an alternat ive transmit data register, except instead of transmitting data, the std pin signal is tri-stated. using this register is important in avoiding overflow/underflow during inactive time slots. application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-80 preliminary 13 of 16 essi fifo control/status register (sfcsr) essi fifo control/status register (sfcsr) base + $b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rfcnt tfcnt rfwm tfwm write reset 0000000010000001 denotes reserved bits bits name description 15 - 12 rfcnt receive fifo counter this read-only bit field indicates the number of data words in the rxfifo. following demonstrates the rfcnt bit field encoding. 0000 0 data words in rxfifo 0001 1 data word in rxfifo 0010 2 data words in rxfifo 0011 3 data words in rxfifo 0100 4 data words in rxfifo 0101 5 data words in rxfifo 0110 6 data words in rxfifo 0111 7 data words in rxfifo 1000 8 data words in rxfifo 11 - 8 tfcnt transmit fifo counter this read-only bit field indicates the number of data words in the txfifo. following demonstrates the tfcnt bit field encoding. 0000 0 data words in txfifo 0001 1 data word in txfifo 0010 2 data words in txfifo 0011 3 data words in txfifo 0100 4 data words in txfifo 0101 5 data words in txfifo 0110 6 data words in txfifo 0111 7 data words in txfifo 1000 8 data words in txfifo essi see the following page for continuation of this register application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-81 freescale semiconductor preliminary 14 of 16 denotes reserved bits essi fifo control/status register (sfcsr) base + $b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rfcnt tfcnt rfwm tfwm write reset 0000000010000001 7 - 4 rfwm receive fifo full watermark this bit field controls the threshold setting of the receive fifo full flag will be set. rff is set whenever the data level in the rxfifo reaches the selected threshold. the following data shows the status of rff for all data levels of the rxfifo. 0000 reserved 0001 rff set when at least 1 data word has been written to the rxfifo. set when rxfifo = 1, 2, 3, 4, 5, 6, 7, or 8 data words 0010 rff set when 2 or more data word has been written to the rxfifo. set when rxfifo = 2, 3, 4, 5, 6, 7, or 8 data words 0011 rff set when 3 or more data word has been written to the rxfifo. set when rxfifo = 3, 4, 5, 6, 7, or 8 data words 0100 rff set when 4 or more data word has been written to the rxfifo. set when rxfifo = 4, 5, 6, 7, or 8 data words 0101 rff set when 5 or more data word has been written to the rxfifo. set when rxfifo = 5, 6, 7, or 8 data words 0110 rff set when 6 or more data word has been written to the rxfifo. set when rxfifo = 6, 7, or 8 data words 0111 rff set when 7 or more data word has been written to the rxfifo. set when rxfifo = 7, or 8 data words 1000 rff set when 8 data word has been written to the rxfifo. set when rxfifo = 8 data words 3 - 0 tdwm transmit fifo empty watermark this bit field controls the threshold where the transmit fifo empty flag is set. the following data provides the status of tfe for all data levels of the txfifo. 0000 reserved 0001 tfe set when there is 1 empty slot in txfifo. (default) transmit fifo empty is set when txfifo = <7 data 0010 tfe set when there is 2 or more empty slots in txfifo. transmit fifo empty is set when txfifo = <6 data 0011 tfe set when there is 3 empty slot in txfifo. transmit fifo empty is set when txfifo = <5 data 0100 tfe set when there is 4 empty slot in txfifo. transmit fifo empty is set when txfifo = <4 data 0101 tfe set when there is 5 empty slot in txfifo. transmit fifo empty is set when txfifo = <3 data 0110 tfe set when there is 6 empty slot in txfifo. transmit fifo empty is set when txfifo = <2 data 0111 tfe set when there is 7 empty slot in txfifo. transmit fifo empty is set when txfifo = <1 data 1000 tfe set when there is 8 empty slot in txfifo. transmit fifo empty is set when txfifo = <0 data essi fifo control/status register (sfcsr) continued essi application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-82 preliminary 15 of 16 15 - 0 tsma transmit slot mask a this is a read/write register. in the network mode, these registers are used by the transmitter to determine which action to take in the current transmission slot. depending on the setting of the bits, the transmitter either tri-states the tr ansmitter data signal or transmits a data word and generates the appropriate transmit status. tsma and tsmb can be viewed as a single 32-bit register named tsm. bit n in tsm (tsmn) is an enable/disable control bit for transmission in slot n. 0 the transmit data signal of the transmitter is tri-stated during transmit time slot n. data is not transferred to the txsr, therefore transmit status flags are not changed 1 the transmit sequence proceeds normally. data is transferred from the stx register (or txfifo, if enabled) to the shift register during slot n. appropriate flags are set 16 - 31 tsmb transmit slot mask b this is a read/write register. in the network mode, these registers are used by the transmitter to determine which action to take in the current transmission slot. depending on the setting of the bits, the transmitter either tri-states the tr ansmitter data signal or transmits a data word and generates the appropriate transmit status. tsma and tsmb can be viewed as a single 32-bit register. 0 the transmit data signal of the transmitter is tri-stated during transmit time slot n. data is not transferred to the txsr, therefore transmit status flags are not changed 1 the transmit sequence proceeds normally. data is transferred from the stx register (or txfifo, if enabled) to the shift register during slot n. appropriate flags are set essi transmit slot mask registers (tsma, tsmb) essi essi transmit slot mask register (tsmb) base + $d bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tsmb [31:16] write reset 1111111111111111 essi transmit slot mask register (tsma) base + $c bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tsma [15:0] write reset 1111111111111111 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-83 freescale semiconductor preliminary 16 of 16 15 - 0 rsma receive slot mask a the receive slot mask registers are two 16-bit read/write registers. in the network mode, these registers are used by the receiver to dete rmine which action to take in the current time slot. depending on the setting of the bits, the receiver either ignores the receiver data signal(s), or receives a data word, generating the appropriate receive status. rsma and rsmb can be viewed as one 32-bit register, rsm. bit n in rsm (rsmn) is an enable/disable control bit for time slot n. 0 data is not transferred from the receive shift register (rxsr) to the receive data (srx) register, therefore the rdr and roe flags are not set 1 the receive sequence proceeds normally. data is received during slot n, and the rdr flag is set 31 - 16 rsmb receive slot mask b the receive slot mask registers are two 16-bit read/write registers. in the network mode, these registers are used by the receiver to dete rmine which action to take in the current time slot. depending on the setting of the bits, the receiver either ignores the receiver data signal(s), or receives a data word, generating the appropriate receive status. rsma and rsmb can be viewed as one 32-bit register, rsm. bit n in rsm (rsmn) is an enable/disable control bit for time slot n. 0 data is not transferred from the receive shift register (rxsr) to the receive data (srx) register, therefore the rdr and roe flags are not set 1 the receive sequence proceeds normally. data is received during slot n, and the rdr flag is set essi receive slot mask registers (rsma, rsmb) essi essi receive slot mask register (rsmb) base + $f bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rsmb [31:16] write reset 1111111111111111 essi receive slot mask register (rsma) base + $e bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rsma [15:0] write reset 1111111111111111 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-84 preliminary tmra0_cmp1 (timer a, channel 0 compare 1)?address: tmra_base + $0 tmra1_cmp1 (timer a, channel 1 compare 1)?address: tmra_base + $8 tmra2_cmp1 (timer a, channel 2 compare 1)?address: tmra_base + $10 tmra3_cmp1 (timer a, channel 3 compare 1)?address: tmra_base + $18 tmr compare register1 (cmp1) $1ffe80 +$0, $8, $10, $18 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read comparison value 1 write reset 0000000000000000 bits name description 15 - 0 comparison value1 timer compare register 1 these read/write registers store the va lue used for comparison with counter value. tmr compare register 1 (cmp1) 1 of 11 tmr application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-85 freescale semiconductor preliminary 2 of 11 tmr compare register 2 (cmp2) tmr bits name description 15 - 0 comparison value2 timer compare register 2 these read/write registers store the va lue used for comparison with counter value. tmr compare register (cmp2) $1ffe80 +$1, $9, $11, $19 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read comparison value 2 write reset 0000000000000000 tmra0_cmp2 (timer a, channel 0 compare 2)?address: tmra_base + $1 tmra1_cmp2 (timer a, channel 1 compare 2)?address: tmra_base + $9 tmra2_cmp2 (timer a, channel 2 compare 2)?address: tmra_base + $11 tmra3_cmp2 (timer a, channel 3 compare 2)?address: tmra_base + $19 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-86 freescale semiconductor preliminary 3 of 11 tmr tmr capture register (cap) tmr capture register (cap) $1ffe80 + $2, $a, $12, $1a bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read capture value write reset 0000000000000000 bits name description 15 - 0 capture value timer capture register these read/write registers store t he value captured from the counter. tmra0_cap (timer a, channel 0 capture)?address: tmra_base + $2 tmra1_cap (timer a, channel 1 capture)?address: tmra_base + $a tmra2_cap (timer a, channel 2 ca pture?address: tmra_base + $12 tmra3_cap (timer a, channel 3 capture)?address: tmra_base + $1a application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-87 preliminary 4 of 11 tmr tmr load register (load) bits name description 15 - 0 load value timer load register these read/write registers store the value used to load the counter tmra0_load (timer a, channel 0 load)?address: tmra_base + $3 tmra1_load (timer a, channel 1 load)?address: tmra_base + $b tmra2_load (timer a, channel 2 load)?address: tmra_base + $13 tmra3_load (timer a, channel 3 load)?address: tmra_base + $1b tmr load register (load) $1ffe80 + $3, $b, $13, $1b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read load value write reset 0000000000000000 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-88 freescale semiconductor preliminary 5 of 11 tmr denotes reserved bits tmr hold register (hold) bits name description 15 - 0 hold value timer hold register these read/write registers st ore the channel?s value whe never any counter is read. tmra0_hold (timer a, channel 0 hold)?address: tmra_base + $4 tmra1_hold (timer a, channel 1 hold)?address: tmra_base + $c tmra2_hold (timer a, channel 2 hold)?address: tmra_base + $14 tmra3_hold (timer a, channel 3 hold)?address: tmra_base + $1c tmr hold register (hold) $1ffe80 + $4, $c, $14, $1c bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read hold value write reset 0000000000000000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-89 preliminary denotes reserved bits 6 of 11 tmr counter register (cntr) bits name description 15 - 0 counter timer counter register these read/write registers are the counters. tmra0_cntr (timer a, channel 0 counter)?address: tmra_base + $5 tmra1_cntr (timer a, channel 1 counter)?address: tmra_base + $d tmra2_cntr (timer a, channel 2 c ounter)?address: tmra_base + $15 tmra3_cntr (timer a, channel 3 c ounter)?address: tmra_base + $1d tmr counter register (cntr) $1ffe80 + $5, $d, $15, $1d bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read counter write reset 0000000000000000 tmr application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-90 freescale semiconductor preliminary 7 of 11 tmr tmr control register (ctl) bits name description 15 - 13 cm count mode these bits control the basic counting behavior of the counter 000 no operation 001 count rising edges of primary source. 010 count rising and falling edges of primary source. 011 count rising edges of primary source while secondary input is active high 100 quadrature count mode uses primary and secondary sources 101 count primary source rising edges, secondar y source specifies direction (1=minus) 110 edge of secondary source trigger s primary count until compared 111 cascaded counter mode (up/down) 12 - 9 pcs primary count service source these bits select the primary count source 0000 counter 0 input pin (tio0) 0001 counter 1 input pin (tio1) 0010 counter 2 input pin (tio2) 0011 counter 3 input pin (tio3) 0100 counter 0 output (oflag0) 0101 counter 1 output (oflag1) 0110 counter 2 output (oflag2) 0111 counter 3 output (oflag3) 1000 prescaler (ipbus clock divide by 1) 1001 prescaler (ipbus clock divide by 2) 1010 prescaler (ipbus clock divide by 4) 1011 prescaler (ipbus clock divide by 8) 1100 prescaler (ipbus clock divide by 16) 1101 prescaler (ipbus clock divide by 32) 1110 prescaler (ipbus clock divide by 64) 1111 prescaler (ipbus clock divide by 128) tmr control register (ctl) $1ffe80 + $6, $e, $16, $1e bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read cm pcs scs once length dir ext init om (oflag) write reset 0 0 0 0000 0 0 0 0 00000 see the following page for continuation of this register application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-91 preliminary tmr 8 of 11 tmr control register (ctl) $1ffe80 + $6, $e, $16, $1e bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read cm pcs scs once length dir ext init om (oflag) write reset 000000000 0 0 00000 tmra0_ctrl (timer a, channel 0 control)?address: tmra_base + $6 tmra1_ctrl (timer a, channel 1 control)?address: tmra_base + $e tmra2_ctrl (timer a, channel 2 control)?address: tmra_base + $16 tmra3_ctrl (timer a, channel 3 control)?address: tmra_base + $1e tmr control register (ctl) continued bits name description 8 - 7 scs secondary source this bit field provides additional information used for counting, such as direction. 00 counter 0 input pin (tio0) 01 counter 1 input pin (tio1) 10 counter 2 input pin (tio2) 11 counter 3 input pin (tio3) 6 once count once this bit selects continuous or one-shot counting mode. 0 count repeatedly 1 count until compare, then stop. counting up: compares when counter reaches cmp1 value. counting down: compares when counter reaches cmp2 value. 5 length count length determines whether counter counts to the compare value, reinitializing itself. 0 roll-over 1 count until compare, then reinitialize see the following page for continuation of this register application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-92 freescale semiconductor preliminary bits name description 4 dir direction this bit selects either normal count up direction, or the reverse count down direction. 0 count up 1 count down 3 extinit external initialization this bit enables another counter/tim er within the same module to force the reinitialization of this counter/timer when the other count er has an active compare event 0 external counter/timers cannot force a reinitialization of this counter/timer 1 external counter/timers may force re initialization of this counter/timer 2 - 0 om output mode this bit field determines the mode of operation for the oflag output signal. 000 asserted while counter is active 001 clear oflag output on successful compare 010 set oflag output on successful compare 011 toggle oflag output on successful compare 100 toggle oflag output using alternating compare registers 101 set on compare, cleared on secondary source input edge 110 set on compare, cleared on counter roll over 111 enable gated clock output while counter is active tmra0_ctrl (timer a, channel 0 control)?address: tmra_base + $6 tmra1_ctrl (timer a, channel 1 control)?address: tmra_base + $e tmra2_ctrl (timer a, channel 2 control)?address: tmra_base + $16 tmra3_ctrl (timer a, channel 3 control)?address: tmra_base + $1e tmr control register (ctl) $1ffe80 + $6, $e, $16, $1e bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read cm pcs scs once length dir ext init om (oflag) write reset 0 0 00000 0 0 0 0 0 0 0 0 0 tmr tmr control register (ctl) continued 9 of 11 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-93 preliminary bits name description 15 tcf timer compare flag this bit is set when a successful compare occurs. cleared by writing a 0 to it. 14 tcfie timer compare flag interrupt enable when set, this bit enables interrupts when the tcf bit is set. 13 tof timer overflow flag this bit is set when the counter rolls over it s maximum value $ffff or $0000, depending on count direction. clear the bit by writing 0 to it. 12 tofie timer overflow flag interrupt enable when set, this bit enables interrupts when the tof bit is set. 11 ief input edge flag this bit is set when a positive input transition occurs. clear the bit by writing 0 to it. 10 iefie input edge flag interrupt enable when set, this bit enables interrupts when the ief bit is set. 9 ips input polarity select when set, this bit inverts the input signal polarity. 8 input external input signal this read-only bit reflects the current state of the external input pin selected via the secondary count source after application of the ips bit. 10 of 11 tmr status/control registers (scr) tmr tmr status/control register (scr) $1ffe80 + $7, $f, $17, $1f bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tcf tcfie tof tofoe ief iefie ips input cm mstr eeof val 0 ops oen write force reset 000 0 000 000000 0 00 denotes reserved bits see the following page for continuation of this register application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-94 freescale semiconductor preliminary 11 of 11 tmr status/control register (scr) continued tmr tmr status/control register (scr) $1ffe80 + $7, $f, $17, $1f bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tcf tcfie tof tofoe ief iefie ips input capture mode mstr eeof val 0 ops oen write force reset 00 0 00000 0 0 0 00 0 00 denotes reserved bits bits name description 7 - 6 capture mode input capture mode these bits specify the operation of the capture r egister and the operation of the input edge flag. 00 capture function is disabled 01 load capture register on rising edge of input 10 load capture register on falling edge of input 11 load capture register on any edge of input 5 mstr master mode when set, this bit enables compare function ?s output to be broadcasted to the other counter/timers in the module. this signal can then be used to reinitialize the other counters and/or force their oflag signal outputs. 4 eeof enable external oflag force when set, this bit enables the compare from another counter/timer within the same module to force the state of this counter?s oflag output signal. 3 val forced oflag value this bit determines the value of the oflag output signal when a software triggered force command, or another counter/timer set as a master, issues a force command. 2 force force oflag output this write-only bit forces the current value of t he val bit to be written to the oflag output. this bit is read as 0. the val and force bits can be written simultaneously in a single write operation. write to the force bit only when the counter is disabled. 0 no action 1 forces the current value of the val bit to be written to oflag output 1 ops output polarity select this bit determines the polarity of the oflag output signal. 0 true polarity 1 inverted polarity 0 oen output enable when set, this bit enables the oflag output signal to be placed on the external pin. setting this bit connects a timer?s output pin to its input. polarity of the signal will be determined by ops bit. tmra0_scr (timer a, channel 0 status/control)?address: tmra_base + $7 tmra1_scr (timer a, channel 1 status/control)?address: tmra_base + $f tmra2_scr (timer a, channel 2 status/control)?address: tmra_base + $17 tmra3_scr (timer a, channel 3 status /control)?address: tmra_base + $1f application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-95 freescale semiconductor preliminary 1 of 10 tod control status (todcs) tod tod control status register (todcs) $1fffc0 + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tod sio tod al test tod da tod ha tod ma tod sa tod sen tod aen tod_ lock tod en write reset 0 0 000000 0 0 0 0 0 0 0 0 bits name description 15 todsio time-of-day 1-second interrupt occurred flag this bit is set when one-second interrupt occurs. this bit is cleared by writing a 0 to the bit position. it must be cleared before exiting the interrupt service routine (isr). 14 todal time-of-day alarm interrupt occurred flag this bit is set when tod alarm interrupt occurs. th is bit is cleared by writing a zero to the bit position. this bit must be cleared before exiting the interrupt service routine. 9 - 8 test test bit field this bit field is reserved as factory test bits and must be written as 0. 7 todda time-of-day days alarm enable 0 alarm interrupt ignores days counter 1 alarm interrupt requires match of days alarm register to days counter 6 todha time-of-day hours alarm enable 0 alarm interrupt ignores hours counter 1 alarm interrupt requires match of hours alarm register to hours counter 5 todma time-of-day minutes alarm enable 0 alarm interrupt ignores minutes counter 1 alarm interrupt requires match of minutes alarm register to minutes counter 4 todsa time-of-day seconds alarm enable 0 alarm interrupt ignores seconds counter 1 alarm interrupt requires match of sec onds alarm register to seconds counter 3 todsen time-of-day seconds interrupt enable 0 disables tod seconds interrupt 1 enables tod seconds interrupt 2 todaen time-of-day alarm interrupt enable 0 disables tod alarm interrupt 1 enables tod alarm interrupt 1 tod_lock time-of-day lock 0 tod registers not locked 1 tod registers locked 0 toden time-of-day enable writing 0 to toden disables the time-of-day counting; the time registers will contain the final value of the time counters and the registers can receive writing. denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-96 preliminary 2 of 10 tod clock scaler (todcsl) tod bits name description 15 - 0 todscl time-of-day clock scaler setting this field to x divides the tod input clock frequency by x + 1 to produce the time-base clock used for incrementing the counters. the cl ock generation system and this scaler must be configured so the time-base clo ck is precisely 1hz for correct operation of the tod module as the seconds counter increments with each time-base clock. this register is always readable. it accepts writing only when toden = 0. tod clock scaler register (todcsl) $1fffc0 + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read time -of-day clock scaler write reset 0000000000000000 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-97 freescale semiconductor preliminary denotes reserved bits 3 of 10 tod seconds register (todsec) tod bits name description 5 - 0 todsec time-of-day seconds when toden is set, this register is cont inuously updated to contain the current seconds counter value. the value of the counter can be read through the seconds register, but it cannot be modified. when toden is cleared, tod counting is disabled. this register can then be read or written. when toden is set to one again, the counting resumes from the current register value. tod seconds counter register (todsec) $1fffc0 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todsec write reset 0000000000000000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-98 preliminary 4 of 10 tod seconds alarm register (todsal) tod bits name description 5 - 0 todsal time-of-day seconds alarm when the value contained in this register matches the value of the seconds counter, the seconds alarm is asserted if the seconds alar m enable (todsa) bit and alarm interrupt enable (todaen) bits are set and all other enabled alarm registers also match. tod seconds alarm register (todsal) $1fffc0 + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todsal write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-99 freescale semiconductor preliminary 5 of 10 tod minutes register (todmin) tod bits name description 5 - 0 todmin time-of-day minutes when toden is set, this register is cont inuously updated to contain the current minutes counter value. the value of the counter can be r ead through the minutes register, but it cannot be modified. when toden is cleared, tod counting is disabled. this register can then be read or written. when toden is set to one again, the counting resumes from the current register value. tod minutes register (todmin) $1fffc0 + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todmin write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-100 preliminary 6 of 10 tod minutes alarm register (todmal) tod bits name description 5 - 0 todmal time-of-day minutes alarm when the value contained in this register matches the value of the minutes counter, the minutes alarm is asserted if the minutes alarm enable (todma) bit and alarm interrupt enable (todaen) bit are both set, and all other enabled alarm registers also match the current time. tod minutes alarm register (todmal) $1fffc0 + $5 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todmal write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-101 freescale semiconductor preliminary 7 of 10 tod hours register (todhr) tod bits name description 5 - 0 todhr time-of-day hours when toden is set, this register is continuously updated to contain the current hours counter value. the value of the counter can be read through the hours register, but it can not be modified. when toden is cleared, tod counting is disabled. this register can then be read or written. when toden is set to one again, the counting resumes from the current register value. tod hours register (todhr) $1fffc0 + $6 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todhr write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-102 preliminary 8 of 10 tod hours alarm register (todhal) tod bits name description 4 - 0 todhal time-of-day hours alarm when the value contained in this register matches the value of the hours counter, the hours alarm is asserted if the hours alarm enable (todha) bit and the alarm interrupt enable (todaen) bit are both set and all other enabled alarm registers also match the current time. tod hours alarm register (todhr) $1fffc0 + $7 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todhal write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-103 freescale semiconductor preliminary 9 of 10 tod days register (todday) tod bits name description 15 - 0 todday time-of-day days when toden is set, this counter is continuously updated to contain the current days counter value. the value of the counter can be read thr ough the days register, but it cannot be modified. when toden is cleared, tod counting is disabled. this counter can then be read or written. when toden is set to one again, counting will re sume counting from the current register value. tod days register (today) $1fffc0 + $8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read todday write reset 0000000000000000 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-104 preliminary 10 of 10 tod days alarm register (toddal) tod bits name description 15 - 0 toddal time-of-day days when toden is set, this counter is continuously updated to contain the current days counter value. the value of the counter can be read thr ough the days register, but it cannot be modified. when toden is cleared, tod counting is disabled. this counter can then be read or written. when toden is set to one again, counting will re sume counting from the current register value. tod days alarm register (today) $1fffc0 + $9 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read toddal write reset 0000000000000000 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-105 freescale semiconductor preliminary 1 of 32 bits name description 3 - 0 pe port a peripheral enable this bit field controls whether a given pin is in normal or gpio modes. 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the emi module peripheral enable register (gpioa_per) $1ffe60 + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 gpio port a peripheral enable register (gpioa_per) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-106 preliminary 2 of 32 bits name description 15 - 0 pe port b peripheral enable this bit field controls whether a given pin is in normal or gpio modes 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the host interface module peripheral enable register (gpiob_per) $1ffe60 + $4 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pe write reset 1111111111111111 gpio port b peripheral enable register (gpiob_per) gpio application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-107 freescale semiconductor preliminary bits name description 5 - 0 pe port c peripheral enable this bit field controls whether a given pin is in normal or gpio modes. 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the essi 0 module peripheral enable register (gpioc_per) $1ffe60 + $8 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 gpio port c peripheral enable register (gpioc_per) gpio denotes reserved bits 3 of 32 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-108 preliminary bits name description 5 - 0 pe port d peripheral enable this bit field controls whether a given pin is in normal or gpio modes. 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the essi 1 module peripheral enable register (gpiod_per) $1ffe60 + $c bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 gpio port d peripheral enable register gpiod_per) gpio denotes reserved bits 4 of 32 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-109 freescale semiconductor preliminary bits name description 3 - 0 pe port e peripheral enable this bit field controls whether a given pin is in normal or gpio modes. 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the sci module peripheral enable register (gpioe_per) $1ffe60 + $10 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 gpio port e peripheral enable register (gpioe_per) gpio denotes reserved bits 5 of 32 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-110 preliminary bits name description 3 - 0 pe port f peripheral enable this bit field controls whether a given pin is in normal or gpio modes. 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the spi module peripheral enable register (gpiof_per) $1ffe60 + $14 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 gpio port f peripheral enable register (gpiof_per) gpio denotes reserved bits 6 of 32 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-111 freescale semiconductor preliminary bits name description 3 - 0 pe port g peripheral enable this bit field controls whether a given pin is in normal or gpio modes. 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the tmr module port g peripheral enable register (gpiog_per) $1ffe60 + $18 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 gpio port g peripheral enable register (gpiog_per) gpio denotes reserved bits 7 of 32 gpio denotes reserved bits 7 of 32 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-112 preliminary bits name description 2 - 0 pe port h peripheral enable this bit field controls whether a given pin is in normal or gpio modes. 0 gpio mode; pin operation is controlled by gpio registers 1 normal mode; pin operation is controlled by the sim module peripheral enable register (gpioh_per) $1ffe60 + $1c bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 pe write reset 1111111111111111 gpio port h peripheral enable register (gpioh_per) gpio denotes reserved bits 8 of 32 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-113 freescale semiconductor preliminary bits name description 3 - 0 dd port a data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpioa_ddr) $1ffe60 + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 gpio port a data direction register (gpioa_ddr) gpio denotes reserved bits 9 of 32 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-114 preliminary 10 of 32 bits name description 15 - 0 dd port b data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpiob_ddr) $1ffe60 + $5 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dd write reset 0000000000000000 gpio port b data direction register (gpiob_ddr) gpio gpio application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-115 freescale semiconductor preliminary 11 of 32 bits name description 5 - 0 dd port c data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpioc_ddr) $1ffe60 + $9 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 gpio port c data direct ion register gpioc_ddr) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-116 preliminary 12 of 32 bits name description 5 - 0 dd port d data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpiod_ddr) $1ffe60 + $d bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 gpio port d data direct ion register (gpiod_ddr) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-117 freescale semiconductor preliminary 13 of 32 bits name description 3 - 0 dd port e data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpioe_ddr) $1ffe60 + $11 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 gpio port e data direction register (gpioe_ddr) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-118 preliminary 14 of 32 gpio port f data direction register (gpiof_ddr) gpio bits name description 3 - 0 dd port f data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpiof_ddr) $1ffe60 + $15 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-119 freescale semiconductor preliminary bits name description 3 - 0 dd port g data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpiog_ddr) $1ffe60 + $19 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 denotes reserved bits 15 of 32 gpio port g data direction register (gpiog_ddr) gpio application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-120 preliminary bits name description 2 - 0 dd port h data direction these bits control the pins direction when in gpio mode. in the normal mode, these bits have no effect on the output enables or pull-up enables. 0 pin is an input; pull-ups are dependent on value of pue registers. (default) 1 pin is an output; pull-ups are disabled data direction register (gpioh_ddr) $1ffe60 + $1d bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 dd write reset 0000000000000000 denotes reserved bits 16 of 32 gpio gpio port h data direction register (gpioh_ddr) application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-121 freescale semiconductor preliminary 17 of 32 bits name description 3 - 0 data port a data these bits control the output data while in the gpio mode. data register (gpioa_dr) $1ffe60 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 gpio port a data re gister (gpioa_dr) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-122 preliminary 18 of 32 bits name description 15 - 0 data port c data these bits control the output data while in the gpio mode. data register (gpiob_dr) $1ffe60 + $6 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read data write reset 0000000000000000 gpio port b data register (gpiob_dr) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-123 freescale semiconductor preliminary 19 of 32 bits name description 5 - 0 data port c data these bits control the output data while in the gpio mode. data register (gpioc_dr) $1ffe60 + $a bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 gpio port c data register (gpioc_dr) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-124 preliminary 20 of 32 bits name description 5 - 0 data port d data these bits control the output data while in the gpio mode. data register (gpiod_dr) $1ffe60 + $e bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 gpio port d data register (gpiod_dr) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-125 freescale semiconductor preliminary 21 of 32 bits name description 3 - 0 data port e data these bits control the output data while in the gpio mode. data register (gpioe_dr) $1ffe60 + $12 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 gpio port e data re gister (gpioe_dr) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-126 preliminary 22 of 32 bits name description 3 - 0 data port f data these bits control the output data while in the gpio mode. data register (gpiof_dr) $1ffe60 + $16 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 gpio port f data register (gpiof_dr) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-127 freescale semiconductor preliminary 23 of 32 bits name description 3 - 0 data port g data these bits control the output data while in the gpio mode. data register (gpiog_dr) $1ffe60 + $1a bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 gpio port g data register (gpiog_dr) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-128 preliminary 24 of 32 bits name description 3 - 0 data port h data these bits control the output data while in the gpio mode. data register (gpioh_dr) $1ffe60 + $1e bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 data write reset 0000000000000000 gpio port h data register (gpioh_dr) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-129 freescale semiconductor preliminary 25 of 32 bits name description 3 - 0 pue port a pull-up enable these bits control whether pull ups are enabled for inputs in either normal or gpio mode. 0 pull ups disabled for inputs 1 pull ups enabled for inputs (default) pull-up enable register (gpioa_pue) $1ffe60 + $3 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 gpio port a pull-up enable register (gpioa_pue) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-130 preliminary 26 of 32 bits name description 15 - 0 pue port b pull-up enable these bits control whether pull ups are enabled for inputs in either normal or gpio mode. 0 pull ups disabled for inputs 1 pull ups enabled for inputs (default) pull-up enable register (gpiob_pue) $1ffe60 + $7 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pue write reset 1111111111111111 gpio port b pull-up enable register (gpiob_pue) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-131 freescale semiconductor preliminary 27 of 32 bits name description 5 - 0 pue port c pull-up enable these bits control whether pull ups are enabled for inputs in either normal or gpio mode. 0 pull ups disabled for inputs 1 pull ups enabled for inputs (default) pull-up enable register (gpioc_pue) $1ffe60 + $b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 gpio port c pull-up enab le register (gpioc_pue) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-132 preliminary 28 of 32 bits name description 5 - 0 pue port d pull-up enable these bits control whether pull ups are enabled for inputs in the normal or gpio modes. 0 pull ups disabled for inputs 1 pull ups enabled for inputs (default) pull-up enable register (gpiod_pue) $1ffe60 + $f bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 gpio port d data register gpiod_pue) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-133 freescale semiconductor preliminary 29 of 32 bits name description 3 - 0 pue port e pull-up enable these bits control whether pull ups are enabled for inputs in the normal or gpio modes. 0 pull ups disabled for inputs 1 pull ups enabled for inputs (default) pull-up enable register (gpioe_pue) $1ffe60 + $13 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 gpio port e pull-up register (gpioe_pue) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-134 preliminary 30 of 32 bits name description 3 - 0 pue port f pull-up enable these bits control whether pull ups are enabled for inputs in the normal or gpio modes. 0 pull ups disabled for inputs 1 pull ups enabled for inputs (default) pull-up enable register (gpiof_pue) $1ffe60 + $b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 gpio port f pull-up register (gpiof_pue) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-135 freescale semiconductor preliminary 31 of 32 bits name description 3 - 0 pue port g pull-up enable these bits control whether pull ups are enabled for inputs in the normal or gpio modes. 0 pull ups disabled for inputs 1 pull ups enabled for inputs (default) pull-up enable register (gpiog_pue) $1ffe60 + $1b bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 gpio port g pull-up register (gpiog_pue) gpio denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-136 preliminary 32 of 32 bits name description 2 - 0 pue port h pull-up enable this register is not used because pull ups are always disabled for the moda, b, and c pull-up enable register (gpioh_pue) $1ffe60 + $1f bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 pue write reset 1111111111111111 gpio port h pull-up register (gpioh_pue) gpio denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-137 freescale semiconductor preliminary 1 of 10 bits name description 8 hrms host request mode select the host mode select (hrms) bi t controls the host request pins 7 hdds host dual data strobe when the host dual data strobe (hdds) bit is set, the hi8 operates in the dual data strobe bus mode; a host bus with separated read and write data strobes. when cleared, the hi8 operates in the single strobe bus mode, i.e. a host bus with a single data strobe signal. 6 tdmaen dsc side transmit dma enable the tdmaen bit is used to enable dsc side tr ansmit dma operations. when set, the on-chip dma controller handles transferring data bet ween the htx register and dsc memory. the on-chip dma controller must be appropriately conf igured to implement the desired data transfer. 5 rdmaen dsc side receive dma enable the rdmaen bit is used to enable dsc side rece ive dma operations. when set, the on-chip dma controller handles transferring data between the hrx register and dsc memory. the on-chip dma controller must be appropriately conf igured to implement the desired data transfer. 4 hf2 host flags 2 and 3 3hf3 the host flag 2 and host flag 3 (hf2 and hf3) bits are used as general purpose flags for dsc-to-host communication. hf2 and hf3 may be set or cleared by the core. hf2 and hf3 are reflected in the interrupt status register (isr) on the host side if they are modified by the software, the host processor can read t he modified values by reading the isr. 2 hcie host command interrupt enable the hcie bit is used to enable a core interrupt when the hcp status bit in the hsr is set. when cleared, hcp interrupts are disabled. when set, a host command interrupt request occurs if hcp is set. the interrupt address is determined by the host command vector register. cleared on hardware reset. 1 htie host transmit interrupt enable the htie bit is used to enable a core interrupt when the host transmit data empty status bit in the hsr is set. when cleared, htde interrupts are disabled. when set, a host transmit data interrupt request occurs when the htde bit is set. it is cleared on hardware reset. 0 hrie host receive interrupt enable the hrie bit is used to enable a core interrupt wh en the host receive data full (hrdf) status bit in the host status register (hsr) is set. when cleared, hrdf interrupts are disabled. when set, a host receive data interrupt request occurs if the hrdf bit is also set. it is cleared on hardware reset. hi8 host control register (hcr) $1fffd8 + $0 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 hrms hdds tdmaen rdmaen hf3 hf2 hcie htie hrie write 0 0 0 0 0 0 0 reset 000000000 0 0 00000 hi8 host control register (hcr) hi8 denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-138 preliminary 2 of 10 hi8 hi8 status register (hsr) bits name description 5 hdma host dma status the host dma status (hdma) bit indicates the host processor has enabled the host dma mode of the hi8 by setting hm1 or hm0 to 1. when the hdma status bit is set at 0, it indicates the host dma mode is disabled by the host mode bits hm0 and hm1, both having been cleared, in the interface control register icr and no host dma operations are pending. when the hdma status bit is set, the host dma mode is enabled by the host mode bits hm0 and hm1. the transmit or receive channel not in use can be used by the host for polled or interrupt operation by the device. hdma is cleared by a dsc reset. 4 hf1 host flags 0 and 1 3hf0 the host flag 0-1 (hf0 and hf1) bits are used as a general purpose flags for host-to-dsc communication. the hf0 and hf1 bits can be set or cleared by the host. these bits reflect the status of host flags hf0 and hf1 in the interface control register (icr) on the host side. 2 hcp host command pending the host command pending (hcp) flag bit reflects the status of the hc bit in the command vector register (cvr), indicating a host command interrupt is pending. the hcp bit is set when the hc bit is set, and both bits are cleared by the hi8 hardware when the interrupt request is serviced by the core. the host can also clear the hc bit, thereby clearing the hcp bit as well. the hcp bit is cleared on hardware reset. 1 htde host transmit data empty the host transmit data empty (htde) flag bit indicates the host transmit data (htx) register is empty and can be written by the core. the htde bit is set when the htx register is transferred to the rxh/rxl registers, and cleared w hen host transfer date (htx) is written by the core. when the htde bit is set, the hi8 gen erates a transmit data full dma request. htde can also be set by the host processor using the initialize function. the htde bit is set on hardware reset. 0 hrdf host receive data full the host receive data full (hrdf) flag bit i ndicates the host receive data (hrx) register contains data from the host proc essor. the hrdf bit is set when data is transferred from the txh/txl registers to the host receive data (hrx) register. the hrdf bit is cleared when the hrx register is read by the core. when the hrdf bit is set, the hi8 generates a receive data full dma request. the hrdf bit can also be cleared by the host processor using the initialize function. the hrdf bit is cleared on hardware reset. hi8 host status register (hsr) $1fffd8 + $1 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 hdma hf1 hf0 hcp htde hrdf write 0 0 0 0 0 0 0 0 0 0 reset 0000000000000010 denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-139 freescale semiconductor preliminary 3 of hi8 hi8 transmit data register (htx) bits name description 15 - 0 htx hi8 transmit data register the write-only hi8 transmit data (htx) register is used for dsc-to-host data transfers. writing to the htx register clears the htde bit in t he hsr. the device can program the htie bit causing a host transmit data interrupt when the ht de bit is set. the htx register is transferred as 16-bit data to the receive byte registers rxh/rxl when both the htde bit on the dsc side and the rxdf status bits on the host side are cl eared. this transfer operation sets both rxdf and htde bits. data should not be written to the ht x register until the htde bit is set to prevent the previous data from being overwritten. hi8 transmit data register (htx) $1fffd8 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write high byte (from hrx) low byte (from lrx) reset 0000000000000010 denotes reserved bits 3 of 10 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-140 preliminary hi8 hi8 receive data register (hrx) bits name description 15 - 0 hrx hi8 receive data register the read-only hi8 receive data (hrx) register is used for host-to-dsc data transfers. the hrx register is loaded with 16-bit data from the transmit data registers txh/txl on the host side when both the transmit data register empty txde on the host side, and dsc host receive data full (hrdf) bits are cleared. this transfer operation sets txde and hrdf bits. the hrx register contains valid data when the hrdf bit is set. reading hrx clears hrdf. the dsc may program the hrie bit to cause a host receive data interrupt when hrdf is set. 4 of 10 hi8 receive data register (hrx) $1fffd8 + $2 bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read high byte (from htx) low byte (from ltx) write reset 0000000000000000 denotes reserved bits application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-141 freescale semiconductor preliminary hi8 hi8 interface control register (icr) bits name description 7initinitialize the initialize bit is used by the host processor to force init ialization of the hi8 hardware. 6 hm1 host mode control 5hm0 the host mode control bits hm0 and hm1 select the transfer mode of the hi8. hm1 and hm0 enable the dma mode of operation, or they interrupt a no-host dma mode of operation when hreq bit in the host control register (hcr) is set. 4 hf1 host flag 1 the host flag 1 (hf1) bit is used as a general purpose flag for host-to-dsc communication. the hf1 bit can be set or cleared by the hos t processor, but cannot be changed by the core. the hf1 bit is cleared on dsc reset. 3 hf0 host flag 0 the host flag 0 (hf0) bit is used as a general purpose flag for host-to-dsc communication. the hf0 bit can be set or cleared by the hos t processor, but cannot be changed by the core. the hf0 bit is cleared on dsc reset. 2 hlend icr host little endian this bit allows the hi8 to be accessed by the host in or big endian data order. when the hlend bit is set, the hi8 can be accessed by the host in little endian order. the rxh/txh is located at address $7 and rxl/txl at $6. when the hlend bit is cleared, the hi8 can be accessed by the host in big endian host data order. the rxh/txh is located at address $6 and rxl/txl at $7. the hlend bit is cleared on hardware reset. 1 treq icr transmit request enable this bit is used to control the hreq pin for host transmit data transfers. in the interrupt mode, and the dma is off, treq is used to enable inte rrupt requests via the external host request (hreq or htrq) pin when the txde status bit in the isr is set. when treq is cleared, txde interrupt is disabled. 0 rreq receive request enable this bit is used to control the hreq pin for host receive data transfers. in the interrupt mode (hdma off), the rreq is used to enable interrupt requests via the external host request (hreq or hrrq) pin when the receive data register full (rxdf) status bit in the interrupt status register (isr) is set. when rreq is cleared, rxdf interrupts are disabled. when rreq is set, the external host request hreq pin or hrrq is asserted if rxdf is set in interrupt mode. 5 of 10 hi8 interface control register (icr) $1fffd8 + $0 bits 7 6 5 4 3 2 1 0 read init hm1 hm0 hf1 hf0 hlend treq rreq write reset 00000 0 00 application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-142 preliminary hi8 hi8 command vector register (cvr) bits name description 7hchost command this bit is used by the host processor to hands hake the execution of host command interrupts. normally, the host processor sets hc = 1 to request the host command interrupt from the core. setting the hc bit causes host command pending to be set in the host status register. 6 - 0 hv cvr host vector these seven bits select the host command interrupt offset address in the vector table to be used by the host command interrupt logic. when the host command interrupt is recognized by the dsc interrupt control logic the offset address of the interrupt vector table taken is 2 hvi0, 6. the host can write hc and hv in the same write cycle. 6 of 10 hi8 command vector register (cvr) $1fffd8 + $1 bits 7 6 5 4 3 2 1 0 read hc hv6 hv5 hv4 hv3 hv2 hv1 hv0 write reset 00000 0 00 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-143 freescale semiconductor preliminary hi8 hi8 interface status register (isr) 7 of 10 hi8 interface status register (isr) $1fffd8 + $2 bits 7 6 5 4 3 2 1 0 read hreq dma 0 hf3 hf2 trdy txde rxdf write 0 reset 00000 0 10 bits name description 7 hreq host request this bit indicates the status of the external ho st request (hreq) output pin if the hrms bit is cleared; or the external host transmit receive request (htrq) output pins, and hrrq respectively, if hrms is set. when the hreq status bit is cleared, it indicates the host request pin, hreq or htrr, htrq and hrrq, are deasserted and either host processor interrupts or host dma transfers are being requested. 6 dma host dma status the dma status bit (dma) indicates that the host processor has enabled the dma mode of the hi8 (hm1 or hm0 =1). when the dma status bit is clear, it indicates that the dma mode is disabled by the host mode bits (hm0 and hm1) in the interface control register icr and no dma operations are pending. when dma is set, it indicates that the dma mode is enabled and the host processor should not use the active dma channel (rxh:rxl or txh:txl depending on dma direction) to avoid conflicts with the dma data transfers. 4 hf3 host flag 3 the host flag 3 (hf3) bit in the interrupt status register indicates the state of host flag 3 in the host control register on the dsc side. the hf3 bit can only be changed by the dsc side. 3 hf2 host flag 2 the host flag 2 (hf2) bit in the interface control register (isr) indicates the state of host flag 2 in the host control register on the dsc side. the hf2 bit can only be changed by the dsc side. 2 trdy transmitter ready this flag bit indicates txh, txl, and the hrx registers are empty. when the trdy bit is set, the data the host processor writes to the txh and txl registers is immediately transferred to the dsc side of the hi8. the many applications can use this feature. 1 txde transmit data register empty this bit indicates the transmit byte registers (txh, and txl) are empty and can be written by the host processor. txde is set when the transmit byte registers are transferred to the hrx register. txde is cleared when the transmit (txl or txh according to hlend bit) register is written by the host processor. txde can be set by the host processor using the initialize feature. 0 rxdf receive data register full this flag bit indicates the receive byte register s (rxh and rxl) contain data from the dsc side and can be read by the host processo r. the rxdf bit is set when the htx is transferred to the receive byte registers. rxdf is cleared when the receive data (rxl or rxh according to hlend bit) register is read by the host processor. denotes reserved bits application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-144 preliminary hi8 8 of 10 bits name description 7 - 0 iv7 - iv0 interrupt vector this read/write register typically containing the interrupt vector number used with mc68000 family processor vectored interrupts. only the host processor can read and write this register. the contents of ivr are placed on the host data bus (h0?h7) when both hreq and hack pins are asserted and host dma is not enabled. the c ontents of this register are initialized to a pre-defined value by a hardware or software rese t, corresponding to the uninitialized interrupt vector in the mc68000 family. hi8 interrupt vector register (ivr) hi8 interrupt vector register (ivr) $1fffd8 + $3 bits 7 6 5 4 3 2 1 0 read iv7 iv6 iv5 iv4 iv3 iv2 iv1 iv0 write reset 00001111 application : date : programmer : sheet c 56f853/854/855/857/858 digital signal controller user manual, rev. 4 b-145 freescale semiconductor preliminary hi8 9 of 10 bits name description 7 - 0 rxh receive data high this read-only register receives data from the high byte of the htx register. it is selected by three external host address (ha2, ha1, and ha0) inputs during a host processor read operation or by an on-chip address counter in dma operations. the receive byte registers contain valid data when the receive data register full (rxdf) bit is set. the host processor can program the rreq bit to assert the exter nal hreq pin when the rxdf bit is set. this informs the host processor or host dma controller of the receive byte registers full condition. reading the data register at host address $7 clears the rxdf bit. hi8 receive byte registers (rxh, rxl) hi8 receive byte registers (rxh) $1fffd8 + $6/$7* bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rxh write reset 0000000000000000 denotes reserved bits bits name description 7 - 0 rxl receive data low this read-only register receives data from the low byte of the htx register. it is selected by three external host address (ha2, ha1, and ha0) inputs during a host processor read operation or by an on-chip address counter in dma operations. the receive byte registers contain valid data when the receive data register full (rxdf) bit is set. the host processor may program the rreq bit to assert the external hreq pin when the rxdf bit is set. this informs the host processor or host dma controller of the receive byte registers full condition. reading the data register at host address $7 clears the rxdf bit. hi8 receive byte registers (rxl) base + $7/$6* bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read rxl write reset 0000000000000000 * depends on hlend setting application : date : programmer : sheet appendix b - programmer?s sheets, rev. 4 freescale semiconductor b-146 preliminary hi8 10 of 10 bits name description 7 - 0 txh transmit data high this write-only register transmits data from the high byte of the hrx register. it is selected by three external host address (ha2, ha1, and ha0) inputs during a host processor write operation or by an on-chip address counter in dma operations. data can be written into the transmit data registers when the txde bit is set. the host processor can program the treq bit to assert the external hreq pin when txde bi t is set. this informs the host processor or host dma controller the transmit byte registers are empty. writing the data register at host address $7 clears the txde bit. hi8 transmit byte registers (txh, txl) hi8 transmit byte registers (txh) base + $6/$7* bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write txh reset 0000000000000000 bits name description 7 - 0 txl transmit data low this write-only register transmits data from the low byte of the hrx register. it is selected by three external host address (ha2, ha1, and ha0) inputs during a host processor write operation or by an on-chip address counter in dma operations. data can be written into the transmit data registers when the txde bit is se t. the host processor can program the treq bit to assert the external hreq pin when txde bi t is set. this informs the host processor or host dma controller the transmit byte registers are empty. writing the data register at host address $7 clears the txde bit. hi8 transmit byte registers (txl) base + $7/$6* bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write txl reset 0000000000000000 denotes reserved bits * depends on hlend setting appendix - b programmer?s sheets, rev. 4 freescale semiconductor b-147 preliminary 56f8300 peripheral user manual, rev. 4 b-148 freescale semiconductor preliminary index index, rev. 4 freescale semiconductor index - i symbols (cap) timer channel capture register 13-17 (cgmdb) cgm divide-by register 6-15 (cgmtod) time of day cgm register 6-16 (cmp1) timer channel compare register 1 13-16 (cmp2) timer channel compare register 2 13-16 (cntr) timer channel counter register 13-18 (ctl) timer control registers 13-11 (cvr) command vector register host side hi8 16-23 (dmacnt) transfer count 9-11 (dmacqs) circular queue size 9-10 (dmadal) destination address low 9-11 (dmasal) source address low 9-12 (dmatc) transfer control 9-8 (fim0, fim1) fast interrupt match registers 8-26 (fivah1) fast interrupt 1 vector address high register 8-28 (fival0, fivah0, fival1, fivah1) fast interrupt match registers 8-27 (fival1) fast interrupt 1 vector address low register 8-28 (hcr) dsc side control register hi8 16-10 (hold) timer channel hold register 13-17 (hrx) dsc side receive data register hi8 16-15 (hsr) dsc side status register hi8 16-13 (htx) dsc side transmit data register hi8 16-15 (icr) host side interface control register hi8 16-18 (ictl) interrupt control register 8-30 (ipr1) interrupt priority register 1 8-9 (ipr2) interrupt priority register 2 8-10 (ipr3) interrupt priority register 3 8-12 (ipr4) interrupt priority register 4 8-14 (ipr5) interrupt priority register 5 8-16 (ipr6) interrupt priority register 6 8-19 (ipr7) interrupt priority register 7 8-21 (irq0, irq1, irq3, irq4) pending registers irq 8-29 (isr) interface status register host side hi8 16-24 (ivr) interrupt vector register host side hi8 16-26 (load) timer channel load register 13-17 (miso) master in/slave out 11-5 (mosi) master out/slave in 11-5 (mpa_ddr) port a direction register gpio 15-14 (mpa_dr) port a data register gpio 15-18 (mpa_per) port a peripheral enable register 15-10 (mpa_pue) port a pull-up enable register gpio 15-21 (mpb_ddr) port b direction register 15-14 (mpb_dr) port b data register gpio 15-18 (mpb_per) port b peripheral enable register gpio 15-10 (mpb_pue) port b pull-up enable register gpio 15-22 (mpc_ddr) port c direction register gpio 15-15 (mpc_dr) port c data register gpio 15-18 (mpc_per) port c peripheral enable register gpio 15-11 (mpc_pue) port c pull-up enable register gpio 15-22 (mpd_ddr) port d direction register gpio 15-15 (mpd_dr) port d data register gpio 15-19 (mpd_per) port d peripheral enable register gpio 15-11 (mpd_pue) port d pull-up enable register gpio 15-23 (mpe_ddr) port e direction register gpio 15-16 (mpe_dr) port e data register gpio 15-19 (mpe_per) port e peripheral enable register gpio 15-12 (mpe_pue) port e pull-up enable register gpio 15-23 (mpf_ddr) port f direction register gpio 15-16 (mpf_dr) port f data register gpio 15-20 (mpf_per) port f peripheral enables register gpio 15-12 (mpf_pue) port f pull-up enable register gpio 15-24 (mpg_ddr) port g direction register gpio 15-17 (mpg_dr) port g data register gpio 15-20 (mpg_per) port g peripheral enables register gpio 15-13 (mpg_pue) port g pull-up enable register gpio 15-24 (mph_ddr) port h direction register gpio 15-17 (mph_dr) port h data register gpio 15-21 (mph_per) port h peripheral enables register gpio 15-13 (mph_pue) port h pull-up enable register gpio 15-25 (rls) receive last slot essi 12-64 (rsma, rsmb) receive slot mask registers 12-58 (rx) receive data essi 12-64 (rxd) receive data 10-4 (rxfifo) receive fifo register 12-29 (rxh, rxl) receive byte registers host side hi8 16-27 (rxsr) receive shift register 12-30 (scd1) sim software control data 1 4-13 (scd2) sim software control data 2 4-13 (scicr) control register 10-23 (scicr2) control register 2 10-27 (scidr) data register 10-31 (scisr) status register 10-28 (sclk) serial clock 11-5 (scr) control register sim 4-9 (scr) timer channel status and control registers 13-14 (scr2) control register 12-37 (scr3) control register 12-43 (scr4) control register 4 12-47 (sfcsr) fifo control/status register 12-54 (spdrr) data receive register 11-28 (spdscr) data size and control register 11-26 (spdtr) data transmit register 11-28 index, rev. 4 index - ii freescale semiconductor (spscr) status and control register 11-22 (srx) receive register (srx) 12-29 (ssr) status register 12-31 (stsr) time slot register 12-53 (stx0, stx1, stx2) transmit registers essi 12-26 (tls) transmit last slot essi 12-65 (todcs) control status tod 14-9 (todcsl) clock scaler tod 14-11 (toddal) days alarm register tod 14-14 (todday) days register tod 14-14 (todhal) hours alarm register tod 14-13 (todhr) hours register tod 14-13 (todmal) minutes alarm register tod 14-13 (todmin) minutes register tod 14-12 (todsal) seconds alarm register tod 14-12 (todsec) seconds counter tod 14-11 (tsma, tsmb) transmit slot mask registers 12-57 (tx) transmit data essi 12-64 (txd) transmit data 10-4 (txfifo0, txfifo1, txfifo2) transmit fifo essi 12-27 (txh, txl) transmit byte registers host side hi8 16-28 (txsr0, txsr1, txsr2) transmit shift registers essi 12-28 (vba) vector base address regiser 8-25 numerics 1-second interrupt flag and outputs tod 14-8 a a/d a-3 acim a-3 adc a-3 adcr a-3 addlmt a-3 addr a-3 adhlmt a-3 adlst a-3 adlstat a-3 adm a-3 adofs a-3 adr pd a-3 adrslt a-3 adsdis a-3 adstat a-3 adzcc a-3 adzcstat a-3 after reset host side registers hi8 16-29 agu a-3 alarm interrupt flag and outputs tod 14-7 alu a-3 api a-3 b barrel shifter a-3 baud rate generation sci 10-7 bcr a-3 bdc a-3 be a-3 bfiu a-3 bflash a-3 bk a-3 bldc a-3 block diagram hi8 16-7 block diagram itcn 8-7 boot rom 1-26 botneg a-4 bs a-4 bsdl a-4 bsr a-4 c can a-4 cap a-4 capture register use tmr 13-9 cascade count mode tmr 13-7 cc a-4 cen a-4 cfg a-4 cgdb a-4 cgm divide-by register (cgmdb) 6-15 interrupts 6-17 module memory map 6-13 resets 6-16 time of day register (cgmtod) 6-16 charge pump pll 6-9 chcnf a-4 ckdivisor a-4 clko a-4 clkosel a-4 clkosr a-4 clock and frame sync generation essi 12-60 clock operation description essi 12-60 clock phase and polarity controls spi 11-11 clocks essi 12-59 cmos a-4 cmp a-4 cnt a-4 cntr a-4 codec a-4 compare registers use tmr 13-9 index, rev. 4 freescale semiconductors index - iii controller block diagram 9-7 cop a-4 cop/rti a-4 cop/watchdog timer module 1-32 copctl a-4 copdis a-4 copr a-4 copsrv a-5 copto a-5 core interrupts hi8 16-16 count mode tmr 13-6 counting mode definitions 14-7 counting modes of definitions tmr 13-5 cpha a-5 cpol a-5 cpu a-5 crc a-5 csen a-5 ctrl a-5 ctrl pd a-5 cwen a-5 cwp a-5 d dac a-5 dat a-5 data frame format sci 10-6 data pd a-5 data register access gpio 15-25 data shift ordering spi 11-11 data sram 1-25 data transfer hi8 host processor 16-30 data transmission length spi 11-11 dda a-5 ddr a-5 dec a-5 dee a-5 dfiu a-5 dflash a-5 dirq a-5 dma circular queue size (dmacqs) 9-10 controller block diagram 9-7 features 9-3 memory-to-memory dma operation 9-14 mode operation host side hi8 16-32 peripheral-to-memory circular queue dma operation 9-15 peripheral-to-memory dma operation 9-13 programming examples 9-13 register descriptions 9-8 register maps 9-5 signal description 9-3 source address high (dmasah) 9-12 source address low (damsal) 9-12 transfer control (dmatc) 9-8 transfer count (dmacnt) 9-11 dpe a-6 dr a-6 drv a-6 dso a-6 dsp a-6 dsp56853 peripheral blocks 1-26 dsp56854 peripheral blocks 1-26 dsp56855 peripheral blocks 1-27 dsp56857 peripheral blocks 1-27 dsp56858 peripheral blocks 1-28 dsp5685x memory maps 3-6 e edg a-6 edge count mode tmr 13-6 ee a-6 eeof a-6 em a-6 emi (external memory interface) 1-28 en a-6 encr a-6 enhanced on-chip emulation (eonce) 1-33 enhanced on-chip emulation (eonce) module 1-21 enhanced synchronour serial interface (essi) 1-30 eonce enhanced on-chip emulation module) 1-21 eosi a-6 eosie a-6 erase a-6 errie a-6 error conditions spi 11-17 essi block diagram 12-8 clock and frame sync generation 12-60 clock operation description 12-60 clocks 12-59 configurations 12-23 control register 2 (scr2) 12-37 control register 3 (scr3) 12-43 control register 4 (scr4) 12-47 external signals descriptions 12-4 features 12-3 fifo control/status register (sfcsr) 12-54 fucntional description 12-10 interrupt operation description 12-63 interrupts 12-63 index, rev. 4 index - iv freescale semiconductor network mode 12-14 network mode with mask registers implemented 12-19 normal mode 12-10 receive data (rx) 12-64 receive data with exception 12-63 receive fifo register (rxfifo) 12-29 receive last slot (rls) 12-64 receive register (srx) 12-29 receive shift register (rxsr) 12-30 receive slot mask registers (rsma, rsmb) 12-58 register descriptions 12-26 resets 12-62 signal descriptions 12-4 signal properties 12-4 status register (ssr) 12-31 time slot register (stsr) 12-53 transmit data (tx) 12-64 transmit data with exception 12-64 transmit fifo registers (txfifo0, txfifo1, txfifo2) 12-27 transmit last slot (tls) 12-65 transmit registers (stx0, stx1, stx2) 12-26 transmit shift registers (txsr0, txsr1, txsr2) 12-28 transmit slot mask registers (tsma, tsmb) 12-57 essi (enhanced synchronour serial interface) 1-30 essi enable (essien) 12-42 ex a-6 extboot a-6 external frame sync setup issi 12-65 external i/o signals spi 11-6 external memory interface (emi) 1-28 external signals descriptions essi 12-4 extr a-6 f fault a-6 fe a-6 feature matrix 1-12 fh a-6 fiex a-6 fir a-6 fixed frequency pwm mode tmr 13-8 flash memory a-6 floci a-6 floli a-6 fmodex a-6 fpinx a-7 ftackx a-7 fucntional description essi 12-10 functional description gpio 15-4 functional description sci 10-6 functional description tmr 13-4 functionl description itcn 8-7 g gated count mode tmr 13-6 general information tod 14-7 general purpose i/o port (gpio) 1-29 gpio a-7 (general purpose input/output) 1-29 block diagram 15-3 configuration 15-5 data register access 15-25 features 15-3 functional description 15-4 gpio mode 15-4 interrupts 15-26 modes of operation 15-4 normal mode 15-4 port a data register (mpa_dr) 15-18 port a direction register (mpa_ddr) 15-14 port a peripheral enable register (mpa_per) 15-10 port a pull-up enable register (mpa_pue) 15-21 port b data register (mpb_dr) 15-18 port b direction register (mpb_ddr) 15-14 port b peripheral enable register (mpb_per) 15-10 port b pull-up enable register (mpb_pue) 15-22 port c data register (mpc_dr) 15-18 port c direction register (mpc_ddr) 15-15 port c peripheral enable register (mpc_per) 15-11 port c pull-up enable register (mpc_pue) 15-22 port d data register (mpd_dr) 15-19 port d direction register (mpd_ddr) 15-15 port d peripheral enable register (mpd_per) 15-11 port d pull-up enable register (mpd_pue) 15-23 port e data register (mpe_dr) 15-19 port e direction register (mpe_ddr) 15-16 port e peripheral enable register (mpe_per) 15-12 port e pull-up enable register (mpe_pue) 15-23 port f data register (mpf_dr) 15-20 port f direction register (mpf_ddr) 15-16 port f peripheral enables register (mpf_per) 15-12 port f pull-up enable register (mpf_pue) 15-24 port g data register (mpg_dr) 15-20 port g direction register (mpg_ddr) 15-17 port g peripheral enables register (mpg_per) 15-13 port g pull-up enable register (mpg_pue) 15-24 port h data register (mph_dr) 15-21 port h direction register (mph_ddr) 15-17 port h peripheral enables register (mph_per) 15-13 index, rev. 4 freescale semiconductors index - v port h pull-up enable register (mph_pue) 15-25 register descriptions 15-5 register map gpio a 15-5 register map gpio b 15-6 register map gpio c 15-6 register map gpio d 15-7 register map gpio e 15-7 register map gpio f 15-8 register map gpio g 15-8 , 15-9 resets 15-26 gpr a-7 h harvard architecture a-7 hbo a-7 hi8 block diagram 16-7 dsc core interrupts 16-16 dsc side features 16-3 dsc side hi8 control register (hcr) 16-10 dsc side hi8 receive data register (hrx) 16-15 dsc side hi8 register descriptions 16-8 dsc side hi8 status register (hsr) 16-13 dsc side hi8 transmit data register (htx) 16-15 dsc side registers after reset 16-15 features 16-3 host port 16-5 host port use considerations 16-35 host processor data transfer 16-30 host side command vector register (cvr) 16-23 host side dma mode operation 16-32 host side features 16-4 host side hi8 register descriptions 16-9 host side interface control register (icr) 16-18 host side interface status register (isr) 16-24 host side interrupt vector register (ivr) 16-26 host side polling 16-30 host side receive byte registers (rxh, rxl) 16-27 host side registers 16-17 host side registers after reset 16-29 host side transmit byte registers (txh, txl) 16-28 servicing interrupts host side 16-31 servicing the host interface 16-24 signal desctiptions 16-5 hlmti a-7 hlmtie a-7 hold a-7 home a-7 host control interrupt vector itcn 8-35 host port hi8 16-5 host side registers hi8 16-17 host side servicing interrupts hi8 16-31 i i/o a-8 ia a-8 ic a-8 ie a-8 iee a-8 ief a-8 iefie a-8 ienr a-8 ies a-8 ifren a-8 imr a-8 indep a-8 index a-8 input a-8 interface signals sim 4-6 interrupt handshake timing itcn 8-36 interrupt operation description essi 12-63 interrupt vectors 3-19 inv a-8 ip a-8 ipbus a-8 ipbus bridge 1-22 ipe a-8 ipol a-8 ipolr a-8 ipr a-8 ips a-9 irq a-9 is a-9 issi external frame sync setup 12-65 maximum external clock rate 12-65 itcn a-9 after reset 8-36 block diagram 8-7 fast interrupt 1 vector address high register (fivah1) 8-28 fast interrupt 1 vector address low register (fival1) 8-28 fast interrupt match registers (fim0, fim1) 8-26 fast interrupt vector address registers (fival0, fivah0, fival1, fivah1) 8-27 features 8-4 functional description 8-7 host control interrupt vector 8-35 interrupt control register (ictl) 8-30 interrupt handshake timing 8-36 interrupt nesting 8-37 index, rev. 4 index - vi freescale semiconductor interrupt priortity register 1 (ipr1) 8-9 interrupt priortity register 2 (ipr2) 8-10 interrupt priortity register 3 (ipr3) 8-12 interrupt priortity register 4 (ipr4) 8-14 interrupt priortity register 5 (ipr5) 8-16 interrupt priortity register 6 (ipr6) 8-19 interrupt priortity register 7 (ipr7) 8-21 interrupt vector map 8-32 interrupts 8-36 irq pending registers (irq0, irq1, irq3, irq4) 8-29 module memory map 8-5 reset handshake timing 8-36 resets 8-36 signal description 8-4 vector base address register (vba) 8-25 wait and stop mode operations 8-35 j jtag a-9 tap block diagram 17-5 tap controller 17-19 tck pin 17-5 tdi pin 17-5 tdo pin 17-5 test clock input pin (tck) 17-5 test data input pin (tdi) 17-5 test data output pin (tdo) 17-5 test mode select input pin (tms) 17-5 test reset/debug event pin (trst /de ) 17-5 tms pin 17-5 trst /de pin 17-5 jtag/eonce port 1-33 jtagbr a-9 jtagir a-9 l lcd a-9 lck a-9 ldok a-9 lir a-9 llmti a-9 llmtie a-9 load a-9 loci a-9 locie a-9 loli a-9 loop a-9 loop operation sci 10-20 lpos a-9 lposh a-9 lsb a-9 lsh_id a-9 lvd a-9 lvie a-9 lvis a-9 m ma a-9 mac a-10 mas a-10 maximum external clock rate issi 12-65 mb a-10 mcu a-10 memory map cgm 6-13 memory map itcn 8-5 memory map spi 11-21 memory maps 5685x 3-6 method of operation por 7-4 mhz a-10 mips a-10 miso a-10 mode fault error spi 11-19 modes of operation gpio 15-4 modf a-10 modfen a-10 mosi a-10 mpio a-10 msb a-10 mscan a-10 msh_id a-10 mstr a-10 mux a-10 n nesting interrupt itcn 8-37 network mode with implemented mask registers essi 12-19 nl a-10 nor a-10 normal mode gpio 15-4 nvstr a-10 o obar a-10 obctl a-10 obmsk a-10 occs a-10 ocmdr a-10 ocntr a-10 ocr a-10 index, rev. 4 freescale semiconductors index - vii odec a-10 oen a-10 omac a-10 omal a-10 omr a-10 once a-11 one-shot mode tmr 13-7 op a-11 opabdr a-11 opaber a-11 opabfr a-11 opdbr a-11 opfifo a-11 opgdbr a-11 or a-11 oshr a-11 osr a-11 overflow error spi 11-17 ovrf a-11 p pab a-11 pd a-11 pdb a-11 pe a-11 per a-11 peripheral descriptions 1-28 pf a-11 pfiu a-11 pflash a-11 pgdb a-11 phase frequency detector pll 6-9 pll a-11 block diagram 6-8 charge pump 6-9 phase frequency detector 6-9 pllcid a-11 pllcod a-11 pllcr a-11 plldb a-11 pllpdn a-11 plr a-11 pmccr a-11 pmcfg a-12 pmcnt a-12 pmctl a-12 pmdeadtm a-12 pmdismap a-12 pmfctl a-12 pmfsa a-12 pmout a-12 pmport a-12 pol a-12 polling host side hi8 16-30 por a-12 block diagram 7-4 features 7-3 method of operation 7-4 power, ground and peripheral signals 2-10 pram a-12 prog a-12 program sram 1-25 programming examples dma 9-13 psr a-12 pt a-12 ptm a-12 pulse output mode tmr 13-8 pur a-12 pwd a-12 pwm a-12 pwmen a-12 pwmf a-12 pwmrie a-12 pwmval a-12 q qdn a-12 qe a-12 quad timer 1-30 quadrature count mode tmr 13-6 r raf a-12 ram a-12 rdrf a-12 re a-12 receive 12-29 receive data with exception essi 12-63 receive enable 12-39 receiver block diagram sci 10-11 recovery from wait mode sci 10-22 register descriptions hi8 dsc side 16-8 register descriptions hi8 host side 16-9 register descriptions sci 10-23 register map tod 14-8 registers after reset dsc side hi8 16-15 reie a-12 reset handshake timing itcn 8-36 rev a-12 revh a-12 ridle a-13 rie a-13 index, rev. 4 index - viii freescale semiconductor rom a-13 rpd a-13 rsrc a-13 rwu a-13 s sa a-13 sbk a-13 sbo a-13 sbr a-13 sci 1-29 , a-13 baud rate generation 10-7 baud rate tolerance 10-17 control register (scicr) 10-23 control register 2 (scicr2) 10-27 data frame format 10-6 data register (scidr) 10-31 dma operation 10-21 features 10-3 functional diagram 10-6 interrupt sources 10-32 loop operation 10-20 low power options 10-22 receive data (rxd) 10-4 receiver block diagram 10-11 receiver dma operation 10-21 receiver wake up with dma 10-21 recovery from wait mode 10-22 recovery from wait mode 10-32 register descriptions 10-23 run mode 10-22 sci0 and sci1 memory maps 10-5 single wire operation 10-20 status register (scisr) 10-28 stop mode 10-22 transmit data (txd) 10-4 transmit dma operation 10-21 transmitter block diagram 10-8 wait mode 10-22 sci (serial communications interface) 1-29 scibr a-13 scicr a-13 scidr a-13 scisr a-13 sclk a-13 scr a-13 sd a-13 sdk a-13 serial communications interface (sci) 1-29 sext a-13 signal description dma 9-3 signal description hi8 16-5 signal description itcn 8-4 signal description sim 4-6 signal descriptions essi 12-4 signal properties essi 12-4 signed count mode tmr 13-7 sim a-13 block diagram 4-4 clock generation concepts 4-14 clock signals 4-15 control register (scr) 4-9 features 4-3 generated clocks 4-15 interface signals 4-6 power mode controls 4-16 register descriptions 4-9 register map 4-8 resets 4-17 signal description 4-6 software control data 1 (scd1) 4-13 software control data 2 (scd2) 4-13 single wire operation sci 10-20 smode a-13 source address high (dmasah) 9-12 sp a-14 spdrr a-13 spdsr a-13 spdtr a-13 spi a-14 clock phase and polarity controls 11-11 data receive register (spdrr) 11-27 data shift odering 11-11 data size and control register (spdscr) 11-26 data transmission length 11-11 data transmit register (spdtr) 11-28 error conditions 11-17 external i/o signals 11-6 features 11-3 interrupts 11-29 master in/slave out (miso) 11-5 master out/slave in (mosi) 11-5 memory map 11-18 mode fault error 11-19 overflow error 11-17 pin descriptions 11-5 register descriptions 11-22 resets 11-28 serial clock (sclk) 11-5 slave mode 11-8 slave select (ss) 11-5 status and control register (spscr) 11-22 transmission data 11-15 index, rev. 4 freescale semiconductors index - ix transmission format when cpha = 0 11-11 transmission format when cpha = 1 11-13 transmission formats 11-10 transmission initiation latency 11-14 spmstr a-14 sprf a-14 sprie a-14 spscr a-14 spte a-14 sptie a-14 sr a-14 srm a-14 ss a-14 ssi a-14 stop mode 14-7 stop mode tmr 13-5 stop mode tod 14-7 swai a-14 sys_cntl a-14 sys_sts a-14 t tap a-14 tap block diagram jtag 17-5 tce a-14 tcf a-14 tcfie a-14 tck pin 17-5 tcsr a-14 tdi pin 17-5 tdo pin 17-5 tdre a-14 te a-14 teie a-14 terasel a-14 test clock input pin (tck) 17-5 test data input pin (tdi) 17-5 test data output pin (tdo) 17-5 test mode select input pin (tms) 17-5 test reset/debug event pin (trst /de ) 17-5 testr a-14 tfdbk a-14 tfref a-14 tidle a-15 tie and te0-2 bits 12-38 tiie a-15 timer compare interrupts 13-18 timer input edge interrupts 13-19 timer overflow interrupts 13-19 tirq a-15 tm a-15 tmel a-15 tmode a-15 tmr block diagram 13-4 capture register use 13-9 cascade count mode 13-7 compare registers use 13-9 count mode 13-6 counting modes definitions 13-5 edge count mode 13-6 features 13-3 fixed frequency pwm mode 13-8 functional description 13-4 gated count mode 13-6 interrupts 13-18 memory map 13-10 modes of operation 13-4 one-shot mode 13-7 pulse output mode 13-8 quadrature count mode 13-6 register descriptions 13-11 resets 13-18 signed count mode 13-7 stop mode 13-5 timer channel capture register (cap) 13-17 timer channel compare register 1 (cmp1) 13-16 timer channel compare register 2 (cmp2) 13-16 timer channel counter register (cntr) 13-18 timer channel hold register (hold) 13-17 timer channel load register (load) 13-17 timer channel status and control registers (scr) ( 13-14 timer compare interrupts 13-18 timer control registers (ctl) 13-11 timer input edge interrupts 13-19 timer overflow interrupts 13-19 triggered count mode 13-7 variable frequency pwm mode 13-8 tmr module memory map memory map tmr module 13-3 tmr pd a-15 tms pin 17-5 tnvhl a-15 tnvsl a-15 to a-15 tod 1-second interrupt flag and outputs 14-8 alarm interrupt flag and outputs 14-7 block diagram 14-4 clock scaler (todcsl) 14-11 index, rev. 4 index - x freescale semiconductor control status (todcs) 14-9 days alarm register (toddal) 14-14 days register (todday) 14-14 features 14-4 functional description 14-6 general information 14-7 hours alarm register (todhal) 14-13 hours register (todhr) 14-13 minutes alarm register (todmal) 14-13 minutes register (todmin) 14-12 register description 14-8 register map 14-8 scaler 14-6 seconds alarm register (todsal) 14-12 seconds counter (todsec) 14-11 stop mode 14-7 time units 14-6 tofie a-15 topneg a-15 tpgsl a-15 tprogl a-15 tranamit enable 1 (te1) 12-40 transmission data spi 11-15 transmission format when cpha = 0 spi 11-11 transmission format when cpha = 1 spi 11-13 transmission formats spi 11-10 transmission initiation latency spi 11-14 transmit data with exception essi 12-64 transmit enable 0 (te0) 12-40 transmit enable 2 (te2) 12-41 transmitter block diagram sci 10-8 trcvl a-15 triggered count mode tmr 13-7 trst /de pin 17-5 tstreg a-15 u uir a-15 upos a-15 uposh a-15 v variable frequency pwm mode tmr 13-8 vdd a-15 vdda a-15 vector map interrupt 8-32 vel a-16 velh a-16 vlmode a-16 vref a-16 vrm a-16 vss a-16 vssa a-16 w wait and stop mode operations itcn 8-35 wake a-16 wde a-16 wired or mode 11-10 wp a-16 wspm a-16 wsx a-16 wtr a-16 www a-16 x xdb2 a-16 xe a-16 xie a-16 xirq a-16 xne a-16 xram a-16 y ye a-16 z zci a-16 zcie a-16 zcs a-16 zsrc a-16 index, rev. 4 freescale semiconductors index - xi how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trad emarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc. 2005. all rights reserved. dsp5685xum rev. 4 7/2005 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the ri ghts of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. |
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